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Bloques Combinacionales en VHDL - 1103147

This document describes a VHDL project to implement a 4-bit full adder circuit and test it using a testbench. It includes the VHDL code for the full adder entity and architecture, as well as the testbench code. The testbench applies test inputs and verifies the output matches expected values. The document also describes a second assignment to implement a BCD to 7-segment display decoder circuit in VHDL.

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39 views4 pages

Bloques Combinacionales en VHDL - 1103147

This document describes a VHDL project to implement a 4-bit full adder circuit and test it using a testbench. It includes the VHDL code for the full adder entity and architecture, as well as the testbench code. The testbench applies test inputs and verifies the output matches expected values. The document also describes a second assignment to implement a BCD to 7-segment display decoder circuit in VHDL.

Uploaded by

CARLOS
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Práctica 04: Bloques combinacionales en VHDL

Por:
Carlos Antonio Guareño Vélez - 1103147
.
.
Experimento:
Full Adder de dos entradas de 4 bits

Objetivos:
Para el objetivo de esta practica es desarrollar un Sumador completo(full adder)
de dos entradas de 4 bits mediante VHDL. Comprobaremos su funcionamiento con
la herramienta EDA Playground haciendo un testbench y analizando las señales
resultantes.

Procedimiento:
Código Design
-- Implementar en VHDL un Full Adder de dos entradas de 4 bits
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
--Necesaria para el operador &
use IEEE.std_logic_unsigned.all;

entity full4bits is
port(
a, b : in std_logic_vector(3 downto 0);
S : out std_logic_vector(4 downto 0));
end full4bits;

architecture full4bits_ARCH of full4bits is


begin

S <= ('0'& a) + ('0'& b);

end full4bits_ARCH;

Codigo testbench
-- Testbench for OR gate
library IEEE;
use IEEE.std_logic_1164.all;

entity testbench is
-- empty
end testbench;

architecture tb of testbench is

-- DUT component
component full4bits is
port(
a, b : in std_logic_vector(3 downto 0);
S : out std_logic_vector(4 downto 0));
end component;

signal a_in, b_in: std_logic_vector(3 downto 0);


signal S_out: std_logic_vector(4 downto 0);

begin

-- Connect DUT
DUT: full4bits port map(a_in, b_in, S_out);

process
begin
a_in <= "1111";
b_in <= "1000";
wait for 1 ns;
assert(S_out= "10111") report "Fallo prueba 0" severity error;

a_in <= "1111";


b_in <= "1010";
wait for 1 ns;
assert(S_out= "11001") report "Fallo prueba 1" severity error;

a_in <= "1111";


b_in <= "1111";
wait for 1 ns;
assert(S_out= "11110") report "Fallo prueba 2" severity error;

a_in <= "1111";


b_in <= "0000";
wait for 1 ns;
assert(S_out= "1111") report "Fallo prueba 3" severity error;

-- Clear inputs
a_in <= "0000";
b_in <= "0000";

assert false report "Test done." severity note;


wait;
end process;
end tb;

Resultados:

Análisis:
Como podemos observar, los resultados de las 4 mostradas por S_out son
correctos, por lo que comprobamos su funcionamiento.

Asignación:
Display BCD a 7 segmentos
Objetivo:

Para el objetivo de esta practica es el de realizar un circuito decodificador BCD a 7


segmentos utilizando VHDL y EDA Plauground

Procedimiento:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity test is
port (
clk : in std_logic;
bcd : in std_logic_vector(3 downto 0);
segment7 : out std_logic_vector(6 downto 0)
);
end test;

architecture Behavioral of test is

begin
process (clk,bcd)
BEGIN
if (clk'event and clk='1') then
case bcd is
when "0000"=> segment7 <="0000001"; -- '0'
when "0001"=> segment7 <="1001111"; -- '1'
when "0010"=> segment7 <="0010010"; -- '2'
when "0011"=> segment7 <="0000110"; -- '3'
when "0100"=> segment7 <="1001100"; -- '4'
when "0101"=> segment7 <="0100100"; -- '5'
when "0110"=> segment7 <="0100000"; -- '6'
when "0111"=> segment7 <="0001111"; -- '7'
when "1000"=> segment7 <="0000000"; -- '8'
when "1001"=> segment7 <="0000100"; -- '9'

when others=> segment7 <="1111111";


end case;
end if;

end process;

end Behavioral;

Resultados:
library ieee;
use ieee.std_logic_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;

ENTITY test_tb IS
END test_tb;

ARCHITECTURE behavior of test_tb is


signal clk : std_logic := '0';
signal bcd : std_logic_vector(3 downto 0) := (others => '0');
signal segment7 : std_logic_vector(6 downto 0);
constant clk_period : time := 1 ns;
begin
uut: entity work.test PORT MAP (clk,bcd,segment7);
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
stim_proc: process
begin
for i in 0 to 9 loop
bcd <= conv_std_logic_vector(i,4);
wait for 2 ns;
end loop;
end process;

end;

Análisis:

Basándonos en el código del testbench podemos comprobar el correcto funcionamiento del circuito.

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