DIGITAL SYSTEM DESIGN (EC303PC)

MOOCS SWAYAM NPTEL COURSE AS DIGITAL CIRCUITS

COURSE PLANNER
I. COURSE OVERVIEW:

The course will make them learn the basic theory of switching circuits and their applications in detail.
Starting from a problem statement they will learn to design circuits of logic gates that have a specified
relationship between signals at the input and output terminals. They will be able to design
combinational and sequential circuits .They will learn to design counters, adders, sequence detectors.
This course provides a platform for advanced courses like Computer architecture, Microprocessors &
Microcontrollers and VLSI design. Greater Emphasis is placed on the use of programmable logic
devices and State machines.

II. PREREQUISITS:

1. The Pre-requisites for this Course is basic Boolean algebra for Digital Electronic Circuits.

III. COURSE OBJECTIVES:

1. To understand common forms of number representation in logic circuits

2. To learn basic techniques for the design of digital circuits and fundamental concepts
used in the design of digital systems.

3. To understand the concepts of combinational logic circuits and sequential circuits.

4. To understand the Realization of Logic Gates Using Diodes & Transistors.

IV. COURSE OUTCOMES:

S.No. Description Bloom’s Taxonomy Level

1. Understand the numerical information in different forms Understand(Level2)

and Boolean Algebra theorems.

2. Understand Postulates of Boolean algebra and to Understand(Level2)

minimize combinational functions.

3. Design and Analyze combinational and sequential Understand(Level2)

circuits.

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 4. Know about the logic families and realization of logic Knowledge, Understand
gates. (Level1, Level2)

V. HOW PROGRAM OUTCOMES ARE ASSESSED:

Leve Proficiency
Program Outcomes (PO)
l assessed by

Engineering knowledge: Apply the knowledge of mathematics,

Lectures,
science, engineering fundamentals, and an engineering
PO1 Assignments,
specialization to the solution of complex engineering problems 2
Exercises
related to Electronics & Communication and Engineering.

Problem analysis: Identify, formulate, review research literature, and

analyze complex engineering problems related to Electronics &
Hands on
PO2 Communication Engineering and reaching substantiated conclusions
2 Practice
using first principles of mathematics, natural sciences, and Sessions
engineering sciences.

Design/development of solutions: Design solutions for complex

engineering problems related to Electronics & Communication
Engineering and design system components or processes that meet Design
PO3
the specified needs with appropriate consideration for the public 3 Exercises,
health and safety, and the cultural, societal, and environmental Projects
considerations.

Conduct investigations of complex problems: Use research-based

knowledge and research methods including design of experiments, Lab sessions,
PO4
analysis and interpretation of data, and synthesis of the information 1 Exams
to provide valid conclusions.

Modern tool usage: Create, select, and apply appropriate techniques,

resources, and modern engineering and IT tools including prediction Design
PO5
and modeling to complex engineering activities with an 1 Exercises, Oral
understanding of the limitations. discussions

The engineer and society: Apply reasoning informed by the

contextual knowledge to assess societal, health, safety, legal and
PO6 cultural issues and the consequent responsibilities relevant to the
- -
Electronics & Communication Engineering professional engineering
practice.

II ECE I SEM
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 Leve Proficiency
Program Outcomes (PO)
l assessed by

Environment and sustainability: Understand the impact of the

Electronics & Communication Engineering professional engineering
PO7
solutions in societal and environmental contexts, and demonstrate - -
the knowledge of, and need for sustainable development.

Ethics: Apply ethical principles and commit to professional ethics

PO8
and responsibilities and norms of the engineering practice. - -

Individual and team work: Function effectively as an individual, and

PO9 as a member or leader in diverse teams, and in multidisciplinary Seminars
3
settings. Discussions

Communication: Communicate effectively on complex engineering

activities with the engineering community and with society at large,
PO10 such as, being able to comprehend and write effective reports and
- -
design documentation, make effective presentations, and give and
receive clear instructions.

Project management and finance: Demonstrate knowledge and

understanding of the engineering and management principles and
PO11
apply these to one’s own work, as a member and leader in a team, to - -
manage projects and in multidisciplinary environments.

Life-long learning: Recognize the need for, and have the preparation
Development
PO12 and ability to engage in independent and life-long learning in the
2 of Mini
broadest context of technological change. Projects
1: Slight (Low) 2: Moderate (Medium) 3: Substantial (High) - : None
VI. HOW PROGRAM SPECIFIC OUTCOMES ARE ASSESSED:

Proficiency
Program Specific Outcomes Level
assessed by

Professional Skills: An ability to understand the basic

concepts in Electronics & Communication Engineering and to apply
PSO 1 them to various areas, like Electronics, Communications, Signal Lectures
3
processing, VLSI, Embedded systems etc., in the design and and
implementation of complex systems. Assignmen
ts
PSO 2 Problem-Solving Skills: An ability to solve complex
Electronics and communication Engineering problems, using latest
2
Tutorials
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 hardware and software tools, along with analytical skills to arrive
cost effective and appropriate solutions.

Successful Career and Entrepreneurship: An understanding of

social-awareness & environmental-wisdom along with ethical
PSO 3 responsibility to have a successful career and to sustain passion and Seminars
3
zeal for real-world applications using optimal resources as an and
Entrepreneur. Projects

1: Slight (Low) 2: Moderate (Medium) 3: Substantial (High) - : None

VII. SYLLABUS:

Course syllabus: (JNTU)

UNIT - I: Number Systems: Number systems, Complements of Numbers, Codes- Weighted

and Non-weighted codes and its Properties, Parity check code and Hamming code.
Boolean Algebra: Basic Theorems and Properties, Switching Functions- Canonical and
Standard Form, Algebraic Simplification, Digital Logic Gates, EX-OR gates, Universal Gates,
Multilevel NAND/NOR realizations.
UNIT - II: Minimization of Boolean functions: Karnaugh Map Method - Up to five
Variables, Don’t Care Map Entries, Tabular Method, Combinational Logic Circuits: Adders,
Subtractors, Comparators, Multiplexers, Demultiplexers, Encoders, Decoders and Code
converters, Hazards and Hazard Free Relations.
UNIT - III: Sequential Circuits Fundamentals: Basic Architectural Distinctions between
Combinational and Sequential circuits, SR Latch, Flip Flops: SR, JK, JK Master Slave, D and
T Type Flip Flops, Excitation Table of all Flip Flops, Timing and Triggering Consideration,
Conversion from one type of Flip-Flop to another.
Registers and Counters: Shift Registers – Left, Right and Bidirectional Shift Registers,
Applications of Shift Registers - Design and Operation of Ring and Twisted Ring Counter,
Operation of Asynchronous and Synchronous Counters.
UNIT - IV : Sequential Machines: Finite State Machines, Synthesis of Synchronous
Sequential Circuits- Serial Binary Adder, Sequence Detector, Parity-bit Generator,
Synchronous Modulo N –Counters. Finite state machine-capabilities and limitations, Mealy
and Moore models.
UNIT - V: Realization of Logic Gates Using Diodes & Transistors: AND, OR and NOT
Gates using Diodes and Transistors, DCTL, RTL, DTL, TTL, CML and CMOS Logic
Families and its Comparison, Classification of Integrated circuits, comparison of various logic
families, standard TTL NAND Gate Analysis & characteristics, TTL open collector O/Ps,
Tristate TTL, MOS & CMOS open drain and tristate outputs, CMOS transmission gate, IC
interfacing- TTL driving CMOS & CMOS driving TTL.

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 TEXT BOOKS:
1. Switching and Finite Automata Theory- Zvi Kohavi & Niraj K. Jha, 3rdEdition,Cambridge . 2.
Modern Digital Electronics – R. P. Jain, 3rd Edition, 2007- Tata McGraw-Hill
REFERENCE BOOKS:
1. Digital Design- Morris Mano, PHI, 4th Edition,2006
2. Introduction to Switching Theory and Logic Design – Fredriac J. Hill, Gerald R. Peterson,
3rd Ed, John Wiley & Sons Inc.
3. Fundamentals of Logic Design- Charles H. Roth, Cengage Learning, 5th, Edition, 2004.
4. Switching Theory and Logic Design – A Anand Kumar, PHI, 2013
NPTEL Web Course: Digital Circuits
NPTEL Video Course: Digital Circuits
GATE Syllabus: Digital Circuits, Number systems; Combinatorial circuits: Boolean
algebra, minimization of functions using Boolean identities and Karnaugh map,
logic gates and their static CMOS implementations, arithmetic circuits,code
converters, multiplexers, decoders and PLAs; Sequential circuits: latches and flip‐flops,
counters, shift‐registers and finite state machines;
IES Syllabus:Digital Circuits (Section:6)Boolean Algebra& uses; Logic gates, Digital IC
families, Combinatorial/sequential circuits; Basics of multiplexers, counters/registers/
memories /microprocessors, design& applications.
VIII. COURSE PLAN (WEEK-WISE):

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II ECE I SEM
Page 11
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II ECE I SEM
Page 12
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IX. MAPPING COURSE OUTCOMES LEADING TO THE ACHIEVEMENT OF

PROGRAM OUTCOMES AND PROGRAM SPECIFIC OUTCOMES:
Course Program Outcomes Program
Outcomes Specific
Outcomes

PO P PO PO P PO P PO PO PO PO PS PS PS
PO2
1 O3 4 5 O6 7 O8 9 10 11 12 O1 O2 O3

CO1 3 3 1 2 1 - - - 3 - - 2 3 2 3

CO2 3 3 3 1 2 - - - 3 - - 1 3 1 3

CO3 1 2 3 1 1 - - - 3 - - 2 3 2 3

CO4 1 1 3 1 1 - - - 3 - - 1 3 1 3

Average 1.2
2 2.25 2.5 1.25 - - - 3 - - 1.5 3 1.5 3
5

Rounded
2 2 3 1 1 - - - 3 - - 2 3 2 3
Average

1: Slight (Low) 2: Moderate (Medium) 3: Substantial (High) - : None

II ECE I SEM
Page 13
X. QUESTION BANK (JNTUH) :
UNIT - I
Long Answer Questions:
S.No. Question Blooms Course
Taxonomy Outcom
Level e
1. Write the steps involved in unsigned binary subtraction Remember 1
using complements with examples.
a) Perform the subtraction with the following unsigned binary Apply 1
numbers by taking the 2’s complement of the subtrahend:
i. 100-110000 ii. 11010-1101
2.
(b) Construct a table for 4321 weighted code and

write 9154 using this code.

3. Find (3250-72532)10 using 10’s complement. Apply 1

(a) Perform arithmetic operation indicated below. Follow Apply 1

4. signed bit notation

i. 001110 + 110010 ii. 101011-100110

(a)Divide 01100100 by 00011001 Apply 1
5.
(b)Given that (292)10=(1204)b determine ‘b’

(a) What is the gray code equivalent of the Hex Number Understand 1
6. 3A7(b)Find the binary number code for the decimal numbers
from 0 to 9(c) Find 9’s complement (25.639)10

(a)Find (72532-03250)using 9’s complement. Apply 1

(b) Show the weights of three different 4 bit self
7.
complementing codes whose only negative weight is -4

and write down number system from 0 to 9.

Decimal system became popular because we have 10 fingers. Apply 1

A rich person on Earth has decided to distribute Rs. One lakh
equally to the following persons from various planets. Find
out the amount each one of them will get in their respective
8. currencies:

A from planet VENUS possessing 8 fingers

B from planet MARS possessing 6 fingers

II ECE I SEM
Page 14
 C from planet JUPITER possessing 14 fingers

D from MOON possessing 14 fingers

9. State and prove any 4 Boolean theorems with examples Understand 1

(a) Simplify to a sum of 3 terms: A’C’D’ + AC’ +BCD + Apply 1

10. A’CD’ + A’BC + AB’C’

(b) Given AB’ + AB =C, show that AC’ + A’C =B

Short Answer Questions:

S.No. Question Blooms Course
Taxonomy Outcom
Level e
1. Write short notes on binary number systems. Remember 1

2. Discuss 1‟s and 2‟s complement methods of subtraction. Understand 1

3. Discuss octal number system. Understand 1

4. State and prove transposition theorem. Apply 1

5. Show how do you convert AND logic to NAND logic? Apply 1

6. Describe a short note on five bit bcd codes. Remember 1

Illustrate about unit –distance code? State where they are Understand 1
7.
used.

8. State about error correcting codes? Remember 1

9. When do you say that a signal is asserted? Understand 1

State about logic design and what do you mean by positive Understand 1
10.
logic system?

UNIT - II
Long Answer Questions:
S.No. Question Blooms Course
Taxonomy Outcom
Level e
A combinational circuit has 4 inputs (A,B,C,D) and three Evaluate 2
1. outputs (X,Y,Z). XYZ represents a binary number whose
value equals the number of 1’s at the input

II ECE I SEM
Page 15
 i. Find the minterm expansion for the X,Y, Z

ii. Find the maxterm expansion for the Y and Z.

A combinational circuit has four inputs (A, B, C ,D), which Evaluate 2

represent a binary-coded-decimal digit. The circuit has
two groups of four outputs- S,T, U, V (MSB digit) and W,
2. X,Y,Z (LSB digit). Each group represents a BCD digit.
The output digits represent a decimal number which is five
times the input number. Write down the minimum
expression for all the outputs.

Simplify the following Boolean expressions using K-map and Analyze 2

implement them using NOR gates:

3. (a) F (A, B, C D) = AB’C’+ AC +A’CD’

(b)F (W, X, Y,Z)= W’ X’ Y’ Z’+ WXY’Z’+

W’X’YZ+WXYZ

Design BCD to Gray code converter and realize using logic Analyze 2
4.
gates.

5. Design 2*4 decoder using NAND gates. Analyze 2

Reduce the following expression using K-map Apply 2

6.
(BA+A’B+AB’)

Design a circuit with three inputs (A, B, C) and two outputs Analyze 2
7. (X,Y) where the outputs are the binary count of the
number of “ON” (HIGH) inputs

A certain 4 input gate called LEMON gate relizes the Analyze 2

switching function LEMON (A,B,C,D) = BC(A+D).
8.
Assuming that the input variables are available in both
primed and unprimed form:

Show a realization of the function f(w,x,y,z)= Apply 2

9. ∑(0,1,6,9,10,11,14,15) with only 3 LEMON B gate and
one OR gate.

Design a circuit with four inputs and one output where Analyze 2
10.
the output is ! if the input is divisible by 3 or 7.

II ECE I SEM
Page 16
Short Answer Questions:
S.No. Question Blooms Course
Taxonomy Outcom
Level e
1. Define K-map? Remember 2

2. Write the block diagram of 2-4 and 3-8 decoders? Understand 2

3. Define magnitude comparator? Remember 2

4. What do you mean by look-ahead carry? Remember 2

Simplify the Boolean function x′yz + x′yz′ + xy′z′ + xy′z Apply 2

5.
using K-map

6. How combinatorial circuits differ from sequential circuits? Understand 2

What are the IC components used to design combinatorial Understand 2

7.
circuits with MSI and LSI?

8. Define the importance of prime implications Understand 2

9. Locate the minters in a three variable map for f=∑m(0,1,5,7) Apply 2

Simplify the Boolean function x′yz + x′yz′ + xy′z′ + xy′z Apply 2

10.
without using K-map

UNIT - III
Long Answer Questions:
S.No. Question Blooms Course
Taxonomy Outcom
Level e
1. Compare RS and JK flip flop. Evaluate 3

Describe about T flip flop with the help of a logic diagram Understand 3
2. and characteristic table. Derive a T-flip-flop from JK and D
flip flop.

3. Differentiate combinational and sequential circuits. Understand 3

4. Explain the working principle of JK flip flop in detail. Understand 3

5. Derive a JK-flip-flop from SR flip flop. Create 3

6. Explain serial transfer in 4-bit shift registers Understand 3

II ECE I SEM
Page 17
 7. Explain about Binary Ripple counter. Understand 3

8. Define Latch. Explain different types of Latches in detail Understand 3

Examine with the help of a block diagram , the basic Understand 3

9.
components of a sequential circuit.

10. Explain the Ripple counter design. Mention its application Understand 3

Short Answer Questions:

S.No. Question Blooms Course
Taxonomy Outcom
Level e
1. Distinguish between a shift register and counter? Understand 3

2. What are the applications of shift registers? Understand 3

3. What are the applications of Flip-Flops? Understand 3

4. Discuss about a bidirectional shift register? Understand 3

5. How do you build a latch using universal gates? Analyze 3

6. What is the flip-flop memory characteristic? Understand 3

7. Distinguish between synchronous and asynchronous latch? Understand 3

8. What is meant by clocked flip-flop? Understand 3

9. Why a gated D latch is called a transparent latch? Understand 3

10. What are the two types of flip-flops? Understand 3

UNIT - IV
Long Answer Questions:
S.No. Question Blooms Course
Taxonomy Outcom
Level e
Explain the design of sequential circuit with an example. Understand 3
1.
Show the state reduction, State assignment.

2. Define BCD counter and Draw its state table. Remember 3

3. Design a sequential circuit with two D flip flops A and B. and Create 3

II ECE I SEM
Page 18
 one input x, when x=0, the

state of the circuit remains the same. When x=1, the circuit
goes through the state transition from 00 to 11 to 11 to 10
back to 00 and repeats.

Design a Modulo 12 up Synchronous counter using T flip Create 3

4.
flops and draw the circuit diagram

5. Design a decade counter. Create 3

Design a left shift and riht shift for the following data Create 3
6.
10110101

7. Design a serial binary adder using state diagram. Create 3

8. Design a parity bit generator using state diagram. Create 3

9. Design a sequence detector for sequence 1110. Create 3

10. Design a 4-bit asynchronous counter using FSM. Create 3

Short Answer Questions:

S.No. Question Blooms Course
Taxonomy Outcom
Level e
1. What is state diagram? Give an example. Understand 3

2. Distinguish Synchronous and asynchronous counter. Understand 3

What are the approaches to the Design of Synchronous Understand 3

3.
Sequential Finite State Machines

4. Discuss about serial binary adder. Understand 3

Draw the state diagram of a sequence detector for sequence Understand 3

5.
1010.

6. Discuss about parity bit generator. Understand 3

7. Design a mod-3 counter. Create 3

What are the advantages and disadvantages of acynchronous Understand 3

8.
counters?

9. What do you mean by terminal count? Understand 3

II ECE I SEM
Page 19
 10. State variable modulus counter? Understand 3

UNIT - V
Long Answer Questions:
S.No. Question Blooms Course
Taxonomy Outcom
Level e
Draw the circuit diagram of basic TTL NAND gate and Understand 4
1. explain the three parts with the help of functional
operation

DDesign a 4 input CMOS OR-AND INVERT gate. Explain the Create 4

2.
circuit with the help of logic dig and function table

3. Explain the CMOS circuit behavior with resistive load Create 4

Explain the CMOS circuit behavior with resistive load Create 4

4.
voltage TTL and low voltage

What is interfacing? Explain interfacing between low voltage Create 4

5.
TTL and low voltage

Short Answer Questions:

S.No. Question Blooms Course
Taxonomy Outcom
Level e
1. Differentiate between the TTL and DTL logic families. Understand 4
2. Write about the TTL to CMOS interfacing Understand 4

Discuss about the fastest logic family and mention the typical Remember 4
3.
values of its various

OBJECTIVE QUESTIONS:

UNIT-1

1. The fraction (0.68)10 is equal to [ ]

a) (0.010101)2 b) (0.101)2 c) (0.10101)2 d) (0.10111)2

2. The Hexadecimal number A0 has the decimal value [ ]

a)80 b) 256 c) 100 d) 160

3. Given two numbers A & B in sign magnitude representation in an eight bit format A=00011110 &
B=10011100, A XOR B gives [ ]

II ECE I SEM
Page 20
a)10000010 b) 00011111 c) 10011101 d) 11100001

4. The value of binary 1111 is [ ]

a) 23-1 b) 24-1 c) 24 d) none of these

5. The minimum number of bits required to represent negative numbers in the range of -1 to -11 using
2’s complement arithmetic is [ ]

(a) 2 (b) 3 (c) 4 (d) 5

6. The following code is not a BCD code. [ ]

a) Gray code (b) Xs-3 code (c) 8421 code (d) All of these

7. A 15-bit hamming code requires [ ]

(a) 4 parity bits (b) 5 parity bits (c) 15 parity bits (d) 7 parity bits

8. If=5, thebase (radix) of the number system is [ ]

a) 5 (b) 6 (c) 7 (d) 8

9. The hexadecimal number system is used in digital computers and digital systems to [ ]

(a) Perform arithmetic operations (b) Perform logic operations

(c) Perform arithmetic and logic operations (d) Input binary data into the sys

10. Determine the value of base x if: (211)x = (152)8 [ ]

(a) 2 (b) 10 (c) 8 (d) 7

11. Determine the value of base x, if (193)x = (623)8 [ ]

(a) 16 (b) 4 (c) 2 (d) 5

12. Which of the following are called Universal gates [ ]

(a) NAND, NOR (b) AND, OR (c) XOR XNOR (d) OR, XOR

13. Indicate which of the following logic gates can be used to realized all possible
combinational logic functions. GATE1989 [ ]
(A) OR gate (B)NAND gates only (C) EX-OR gate (D) NOR & NAND gates
14. Boolean expression for the output of XNOR logic gate with inputs A and B is GATE 1993 [ ]

II ECE I SEM
Page 21
 (A) AB’ + A’B (B)(A(B)’ + AB(C) (A’ + (B)(A + B’) (D) (A’ + B’)(A + B)

15. The output of a logic gate is ‘1’ when all its inputs are at logic ‘0’. The gate is either
GATE 1994 [ ]

(A)a NAND or an EX-OR gate (B)a NOT or an EX-NOR gate

(C)an OR or an EX-NOR gate (D)an AND or an EX-OR gate
16.The output of the logic gate shown is GATE 1997 [ ]

(A) 0 (B) 1 (C) A (D) A’

17. 2’s complement representation of a 16 bit number (one sign bit and 15 magnitude bits) is FFFF. Its
magnitude in decimal representation is GATE 1993[ ]
(A)0 (B) 1 (C) 32,767 (D) 65,535

18.Two 2’s complement numbers having sign bits x and y are added and the sign bit of the result is z.
Then, the occurrence of overflow is indicated by the Boolean function.
GATE 1998 [ ]

A) xyz (B) x yz (C) x y z  xy z (D)xy + yz + zx

19.4 – bit 2’s complement representation of a decimal number is 1000. The number is
GATE 2002[ ]
(A) +8 (B) 0 (C) -7 (D) -8
20.The number of bytes required to represent the decimal number 1856357 in packed BCD (Binary
Coded Decimal) form is _______. GATE 2014[ ]
(A) 4 (B) 3 (C)2 (D) 8

21. Cyclic codes are also called ________________codes

22. The basic two types of BCD codes are _______________and________ codes.

23. The distance between code words 10010 & 10101 is ________.

24. Convert the binary code (110110)2 to Gray code ______

25. Conversion of 0.1289062 decimal number to its hexa equivalent is _______

II ECE I SEM
Page 22
26. In b’s complement method, the carry is ______ and in(b-1)’s complement method the
carry is _______

27. The MSB of a binary number has a weight of 512, the number consists of _______ bits.

28. ______ are codes which represent letters of the alphabets and decimal numbers as a sequence of 0s
and 1s.

UNIT-2

1.The short hand notation of min term m6 is [ ]

(a) (b) (c) ABC (d)

2. In Boolean algebra A+AB= _____

3. Boolean expression xy+yz+ = _______on reduction.

4. The given expression Y=A+AB+ABC in SOP form is ________

5. In K-map each of the cell represents one of the _________ possible products [ ]

(a)2n (b)2-n (c)n2 (d)All the above

6. The minimum number of bits required to represent negative numbers in the range of -1 to -11 using
2’s complement arithmetic is [ ]

(a)2 (b) 3 (c) 4 (d) 5

7. The following code is not a BCD code. [ ]

a)Gray code (b) Xs-3 code (c) 8421 code (d) All of these

8. A 15-bit hamming code requires [ ]

(a)4 parity bits (b) 5 parity bits (c) 15 parity bits (d) 7 parity bits

9. The logic expression (A+B)(+) can be implemented by giving the inputs A and B to a two-input [ ]

(a)NOR gate (b) NAND gate (c) X-OR gate (d) X-NOR gate

10. Which of the following Boolean algebraic expressions is incorrect? [ ]

(a)A+B=A+B (b) A+AB=B (c) (A+B)(A+C)=A+BC (d) (A+)(A+B)=A

11. The hexadecimal number system is used in digital computers and digital systems to []

II ECE I SEM
Page 23
(a) Perform arithmetic operations (b) Perform logic operations

(c) Perform arithmetic and logic operations (d) Input binary data into the system.

12. The logic expression A+B can be implemented by giving inputs A and B to a two-input [ ]

(a)NOR gate (b) NAND gate (c) X-OR gate (d) X-NOR gate

13. A gate is enabled when its enable input is at logic 0. The gate is []

(a)NOR (b) AND (c) NAND (d) None of these

14. The output of a logic gate is 1 , when all its inputs are at logic 0.The gate is either [ ]

(a)a NOR or an X-NOR (b) a NAND or an X-OR

(c) an OR or an X-NOR (d) an AND or an X-OR

15. In b’s complement method, the carry is ______ and in(b-1)’s complement method the
carry _______

16. The MSB of a binary number has a weight of 512,The number consists of ________

17._________ are codes which represent letters of the alphabets and decimal numbers as a sequence of
0s and 1s.

18. The interconnection of gates to perform a variety of logical operations is called______

19. The NOR gate can function as a NOT gate if ________

20. The implicants which will definitely occur in the final expression are called_______

21. The prime implicant mode of a bunch of 0s is called a ______

22. ______ is a process of converting familiar numbers or symbols into a coded format.

23. A decoder with 64 output lines has ______ select lines.

24. A decimal – to – BCD encoder is a ____ line to _____line encoder.

UNIT-3

1. The combinational circuits are______ than sequential circuits [ ]

A)slower B) faster C) same speed D) None

2. In combinational circuits the o/p depends on ________i/p [ ]

A)present B) past C) A & B D) None

II ECE I SEM
Page 24
3. Full adder circuit adds _______number of bits at a time [ ]
A) 5 B) 2 C) 5 D) 3

4. Half adder circuit adds _______number of bits at a time [ ]

A) 5 B) 2 C) 5 D) 3

5. Serial binary adder is a _______circuit [ ]

A)combinational B) sequential C) A or B D) None

6. A 4 bit parallel adder is designed using _______number of full adders [ ]

A) 2 B) 4 C) 5 D) 3

7. The logic expression for carry of half adder circuit is_____ [ ]

A) A’B B) AB C) AB’ D) None

8. The logic expression for sum of half adder circuit is_____ [ ]

A) A’B B) A xor B C) AB’ D) None

9. In a half subtractor circuit borrow expression is________ [ ]

A) A’B B) AB C) AB’ D) None

10. The logic expression for difference of half subtractor circuit is_____ [ ]
A) A xor B xor C B) B xor C C) A xor B D) None

11. The logic expression for sum of full adder circuit is_____ [ ]
A) A’BC B) A xor B xor C C) B xor C D) None

12. The logic expression for carry of full adder circuit is_____ [ ]
A) ABC B) A xor B xor C C) B xor C D) None

13. In a full subtractor circuit difference expression is________ [ ]

A) A xor B xor C B) B xor C C) A xor C D) B xor C

14. In a full subtractor circuit borrow expression is________ [ ]

A) A xor B xor C B) B xor C C) A xor C D) None

15. The full adder circuit is implemented using _____number of half adder circuits [ ]
A) 3 B) 1 C) 2 D) 4

16. The full subtractor circuit is implemented using _____number of half subtractor circuit
[ ]
A) 3 B) 1 C) 2 D) 4

17. Complement of a bit in adder - subtractor circuit is [ ]

A)inverter B) XOR C) AND D)None

18. Carry look ahead adder reduces _________ [ ]

A)carry propagation time B) carry generation time C) sum generation time D) None

II ECE I SEM
Page 25
19. For an n-bit adder there are _______ gate levels for the carry to propagate from input to output
[ ]
A)3n B) 4n C) 2n D) None

20. In carry look ahead adder C i+1=___________ [ ]

A)Gi+PiCi B) Gi+Pi+1Ci C) Gi+1+PiCi D)None

21. In magnitude comparison of A,B the output of a xor gate if they are equal is ---------
22. In magnitude comparison of A,B the output of a xnor gate if they are equal is --------
23. In magnitude comparison of A,B the output of a xor gate if they are unequal is --------
24. In magnitude comparison of A,B the output of a xnor gate if they are unequal is --------
25. Minimum number of half adders required for 2 bit multiplier is ----------
26. If A=1010 and B=0100 .Then output of a 4 bit parallel adder is______
27. A decoderwith n input provides _______minterms at the output.
28. A encoder has --------number of inputs and --------number of outputs
29. The number of output lines in 1X4 demultiplexer is_______
30. The number of AND gates required to implement 3 X 8 decoder along with 3 not gates is__
31. To implement full adder ---------size decoder is required
32. A 4X16 decoder can be designed using _____ number of 3x8 decoders
33. An octal to binary encoder is implemented using 3_____ gates
34. The number of select inputs in 32X1 multiplexer is_______
35. The binary variable (A=B) is equal to _____ only if all pairs of digits of the two numbers are equal

36. In a 4X2 priority encoder with D3 with highest priority the output XY for input 1111 is_____
37. The decimal adder is also known as ________adder
38. Multiplexer is also called as
39. Demultiplexer is also called as
40. The decimal adder is also known as ________adder
41. The number of 4X1 multiplexers required to design 16X1 multiplexer is ____
42. A 2bit multiplier can design using minimum of
43. A ripple counter's speed is limited by the propagation delay of -------

44. To operate correctly, starting a ring counter requires --------

UNIT-4

1. The output Y of a 2-bit comparator is logic 1 whenever the 2 bit input A is greater than the 2 bit
input B. The number of combinations for which the output is logic 1, is
A. 4 B. 6 C. 8 D. 10

GATE 2012 [ ]

2. A switch-tail ring counter is made by using a single D flip flop. The resulting circuit is a
GATE 1995 [ ]
A. SR flip flop B. JK flip flop C. D flip flop D. T flip flop

3. An SR latch is a GATE 1995 [ ]

A. Combinational circuit B. Synchronous sequential circuit

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 C. One bit memory element D. One clock delay element

4. The present output Qn of an edge triggered JK flip-flop is logic ‘0’. If j = 1, then Qn+1 is
GATE 2005 []
A. Cannot be determined B. Will be logic ‘0’

C. Will be logic ‘1’ D. Will race around

5. A 4 bit modulo-16 ripple counter uses JK flip-flops. If the propagation delay of each flip-flop is 50
nsec, the maximum clock frequency that can be used is equal to ____.
GATE 1990 []

A. 20 MHz B. 10 MHz C. 5 MHz D. 4 MHz

6. Synchronous counters are ________ than the ripple counters.GATE1994 [ ]
A. Slower B. Faster C. Moderate D. None

7. A 4 bit ripple counter and a 4 bit synchronous counter are made using flip flops having a
propagation delay of 10 ns each. If the worst case delay in the ripple counter and the synchronous
counter be R and S respectively, then GATE 2003 [ ]
A. R = 10 ns, S = 40 ns B. R = 40 ns, S = 10 ns

C. R = 10 ns, S = 30 ns D. R = 30 ns, S = 10 ns

8. In sequential Circuits, the output variable depends on ______of the input variable. []
A. Present State B. Past State C. Both D. None

9. The Serial adder is a _______Circuit. []

A. Combinational B. Sequential C. Both D. None

10. The outputs of any sequential circuit are always ______to each other.
A. Complementary B. Independent C. Pearson D. None

11. In S-R latch, if S=R=1, the present state of the latch is. [ ]
A. 1 B. 0 C. Undetermined D. None

12. The D- latch sometimes called as _____ Latch. [ ]

A. Flipflop B. Buffer C. TransparentD. None

13. _____ and______are building blocks of Sequential Circuits. [ ]

A. Flipflop B. Latches C. Both D. None

14. In ______Triggering, the output of Flipflop responds to the input changes only when its enable
input is Low. [ ]
A. Negative Level B. Positive Level C. Edge D. None

15. If S=0, R=1 and CP = 0 to which Qn= 0\1, the S-R Flipflop will be in __State. [ ]
A. No change B. 1 C. 0 D. Undetermined

16. The Basic building block of D- flipflop is ____Flipflop. [ ]

A. J-K B. Master-Slave C. S-R D. None

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17. The output Qn+1is delayed by one clock period for an D- Flipflop to which it is called as
____Flipflop. []
A. J-K B. Master-Slave C.S-R D. Delay

18. For the Inputs J=0, K=0, the output Q will be in ____state. []
A. Reset B. Undertermined C.Nochange D. Delay

19. In JK flipflop, when J = K = 1, the output the Flipflop will be in ____state. []

A. Reset B. Undertermined C. Toggling D. Delay

20. _____will not be an clock input of the Master-slave Flipflop. [ ]

A. Edge Triggered B. Level Triggered C.Both D. None

21. The ____ Flipflop is a modification of JK Flipflop.

22. If P = C = 0, the flipflop will be in _____ State.
23. For Moore Sequential Circuit, the output depends on____ State.
24. The state reduction technique avoids ______states.
25. The Input and Output of a register can be controlled by connecting ____.
26. The _____ are used to transfer and storage of data in the registers.
27. The acronym of SIPO is______.
28. The _____ register has capability of both shifts and parallel load.
29. The______counters are simple in construction for more no. of states.
30. The Major limitation of Ripple counter is_____.

UNIT-5

This set of Digital Electronics/Circuits Multiple Choice Questions & Answers (MCQs)
focuseson “Diode-Transistor Logic(DTL)
1. Diode–transistor logic (DTL) is the direct ancestor of _____________
a) Register-transistor log b) Transistor–transistor logic
c) High threshold logic d) Emitter Coupled Logic
2. In DTL logic gating function is performed by ___________
a) Diode b) Transistor c) Inductor d) CapacitoR
3. In DTL amplifying function is performed by ___________
a) Diode b) Transistor c) Inductor d) Capacitor
4. How many stages a DTL consist of?
a) 2 b) 3 c) 4 d) 5
5. The full form of CTDL is ___________
a) Complemented transistor diode logic b) Complemented transistor direct logic
c) Complementary transistor diode logic d) Complementary transistor direct logic
6. The DTL propagation delay is relatively ___________
a) Large b) Small c) Moderate d) Negligible
7. The way to speed up DTL is to add an across intermediate resister is ___________
a) Small “speed-up” capacitor b) Large “speed-up” capacitor
c) Small “speed-up” transistor d) Large ” speed-up” transistor
8. The process to avoid saturating the switching transistor is performed by ___________
a) Baker clamp b) James R. Biard c) Chris Brown d) Totem-Pole
9. A major advantage of DTL over the earlier resistor–transistor logic is the ___________

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a) Increased fan out b) Increased fan in c) Decreased fan out d) Decreased fan in
10. To increase fan-out of the gate in DTL ___________
a) An additional capacitor may be used b) An additional resister may be used
c) An additional transistor and diode may be used d) Only an additional diode may be used--
-
XIII. WEBSITES:

1. www.asic-world.com
2. www.nptel.ac.in
3. www.learnabout-electronics.org
XIV . MOOCS SWAYAM NPTEL COURSE AS DIGITAL CIRCUITS

(onlinecourses.nptel.ac.in/noc18_ee33) – 12week course.

XV. JOURNALS:

INTERNATIONAL

1. International journal of Analog and Digital Electronics

2. International journal of Digital Electronics
3. International journal of Electronic Security and Digital Forensics
XVI. CASE STUDIES / SMALL PROJECTS:

1. Digital Fan speed regulator

2. Traffic controller

3. Adaptive lighting system for automobiles

4. Automatic LED emergency light.

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