ADAMA SCIENCE & TECHNOLOGY UNIVERSITY

SCHOOL OF ELECTRICAL ENGINEERING & COMPUTING

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENG.

Program: SOFTWARE ENGINEERING

1. Vision of ASTU
 ASTU aspires to be the first choice in Ethiopia and the premier center of excellence in
applied science and technology in Africa by 2030.
2. Mission of ASTU
M1: Produce ethical and internationally competent graduates in applied science and
Technology through quality education.
M2: Conduct problem solving research.
M3: Provide demand driven community service.
M4: Serve as center for innovative knowledge and technology transfer for various
industries.
3. Program Education Objectives (PEO)
What students able to do after graduation in 3-5 years.

PEO Statement
PEO-1 To provide graduates with a strong foundation in mathematics, science and
engineering fundamentals to enable them to devise and deliver efficient solutions
to challenging problems in Electronics &Communications Engineering.
PEO-2 To produce ethically competent and technically qualified Electronics and
Communication Engineers with the potential to become leaders in Industries and
Companies associated with Electronics and Communication Engineering, and able
to pursue research or have successful career in Academia.
PEO-3 To produce Electronics and Communication Engineers who are committed to
sustainable development of Electronics and Communication Systems Companies
and Industries for the betterment of society and nation.

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 PEO-4 To prepare graduates that can critically analyze existing literature in an area of
specialization and ethically develop innovative and research-oriented
methodologies to solve the problems identified to support the socio-economic
development of the nation.

4. Mapping of PEO with Missions

M
M1 M2 M3 M4

PEO-1
√

PEO-2 √

PEO-3 √

PEO-4 √

5. Program outcomes (PO):

What students should know, understand, perform and able to do up on the graduation.

PO Statement
An ability to identify, formulate, and solve complex engineering problems by
PO1
applying principles of engineering, science, and mathematics.
An ability to apply engineering design to produce solutions that meet specified
PO2 needs with consideration of public health, safety, and welfare, as well as global,
cultural, social, environmental, and economic factors.
PO3 An ability to communicate effectively with a range of audiences.
An ability to recognize ethical and professional responsibilities in engineering
PO4 situations and make informed judgments, which must consider the impact of
engineering solutions in global, economic, environmental, and societal contexts.
An ability to function effectively on a team whose members together provide
PO5 leadership, create a collaborative and inclusive environment, establish goals, plan
tasks, and meet objectives.
An ability to develop and conduct appropriate experimentation, analyze and
PO6
interpret data, and use engineering judgment to draw conclusions

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 An ability to acquire and apply new knowledge as needed, using appropriate
PO7
learning strategies.

6. Mapping of PO with PEO

PEO PEO-1 PEO-2 PEO-3 PEO-4
PO
PO-1 √
PO-2 √
PO-3 √
PO-4 √
PO-5 √
PO-6 √
PO-7 √
PO-8 √
PO-9 √
PO-10 √
PO-11 √
PO-12 √

7. Course Syllabus

1 School: Electrical Eng. & Computing Department: Electronics & Communication Eng.

2 Course Major Mandatory

Category

Course Name Digital Logic Design

Course Code: ECEg3201

3 Synopsis: In this course, students will study various digital logic families such as TTL, ECL, and
CMOS, the logic gates under these families, and the electronic circuit techniques
used to implement them. Subsequently, they will learn Boolean algebra, logic

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 expressions, number systems and combinational logic design, including logic
minimization and hazards. In addition, with the understanding of combinational
logic design, students will learn how to design sequential systems, including
analysis of the behavior of synchronization elements and system timing design.
Finally, in this course, students will have hands-on design experiences by carrying
out experiments with component-level devices and designing digital systems.

4 Name(s) of
Academic Staff:

5 Semester and Semester: I Year: III

Year offered:

6 Credit Hour: 4

7 Prerequisite/ ECEg2201 Electronics Circuits I

Co-requisite: (if
any)

8 Course Learning Outcome (CLO): At the end of the course the student will be able to do:

CLO1 Distinguish the analog and digital systems and apply positional notations, number systems
and computer codes in digital systems.

CLO2 Understand the concepts of a logic gates to construct various logic circuits

CLO3 Apply Boolean algebra and Karnaugh maps to simplify and design logic circuits.

CLO4 Design and implement combinational and sequential logic in digital systems

CLO5 Design shift registers for various applications in digital systems

CL06 Apply the concept of combinational and sequential circuits in memory devices

9 Mapping of the course Learning Outcomes to the program Learning Outcomes, Teaching Methods
and Assessment:

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 Program Learning Outcomes (PO)

Assessment
Outcomes (CLO)
Course Learning

PO1 Teaching Methods

PO2
PO3
PO4

PO5

PO6

Assignment
PO7

Laboratory

Final Exam
Mid Exam
L T P O

Quiz
CLO1 √ √ √ √ √

CLO2 √ √ √ √ √ √ √ √ √ √

CLO3 √ √ √ √ √ √ √ √ √ √ √

CLO4 √ √ √ √ √ √ √ √ √ √ √ √ √ √

CLO5 √ √ √ √ √ √ √ √ √ √ √ √

CLO6 √ √ √ √ √ √ √ √ √

Indicate the relevancy between the CLO and PO by ticking “√”on the appropriate relevant box

10 Transferable Skills (if applicable)

(Skills learned in the course of study which can be useful and utilized in other settings)

1 Computer Systems

2 Computer Architecture

3 VLSI circuits and systems

11 Distribution of Student Learning Time (SLT)

Teaching and Learning Activities

Guided learning Guided Independent Total (SLT)

CLO (F2F) Learning Learning

Course Content Outline
(NF2F)
(NF2F)

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 L T P O

Chapter 1: 15hr

INTRODUCTION, NUMBER CLO1 √ √ √ √ √

SYSTEMS AND CODES

1.1 Analog Vs Digital Quantities

and Representations
1.2 Advantages and limitations
of Digital over analog system

1.3 Types logic Families

1.4 Decimal number AND

Binary number
1.5 Decimal to binary
conversation

1.6 Hexadecimal number

AND Octal number

1.7 1’s and 2’s compliment of

binary number
1.8 BCD codes and its uses

Chapter 2: √ √ √ √ √ 20hr
CLO2
Digital Logic Gates
2.1 The NOT gate, logic
symbol, output expression

2.2 The AND gate, logic

symbol, output expression

2.3 The OR gate, logic symbol,

output expression

2.4 The NAND gate, logic

symbol, output expression

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2.5 The NOR gate, logic
symbol, output expression

2.6 The EX-OR AND EX-NOR

gate, logic symbol, output
expression

Chapter 3: 20hr

Boolean algebra and CLO3 √ √ √ √ √

Logic expression
simplification

3.1 Boolean Operation and

Expression
3.2 Basic Theorems, Laws and
Rules of Boolean Algebra
3.3 Boolean Functions and
Truth Tables
3,4 Standard and Canonical
forms of Boolean Algebra

3.5 Simplification of Boolean

Functions:
Algebraic Simplification

Karnaugh Maps Or K-Maps

3.6 Techniques for Minimal

SOP and POS Forms
3.7 The Use of Don’t Care
Conditions

Chapter 4: √ √ √ √ √ 20hr

Analysis and Synthesis of CLO4

Combinational Logic
Circuits

4.1 Design of Combinational

Logic Circuits

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4.2 Basic combinational logic
circuits

4.3 Implementing
Combinational logic

4.4 Universal property of

NAND and NOR gates
4.5 Functions of combinational
logic
4.5.1 Basic Adder
4.5.2 Comparator
4.5.3 Encoder and Decoder
4.5.4 Multiplexer and
Demultiplexer
4.5.5 Parity
generator/checker
Chapter 5: √ √ √ √ √ 20hr
CL04
Sequential logic circuit

5.1. Sequential logic circuit

5.1.1 Flip flops

5.1.2 Latches
5.1.3 Edge triggered flip
flops
5.1.4 Master slave flip flops

Applications

5.2. Counters

5.2.1 Asynchronous counters

5.2.2 Synchronous counters
5.2.3 Design of synchronous
counters
Chapter 6: √ √ √ √ √ 15hr
CL05
Shift registers
6.1 Basic shift registers
6.2 Serial in serial out
registers
6.3 Serial in parallel out
Registers

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6.4 Parallel in serial out
Registers
6.5 Parallel in parallel out
registers, Jonson’s counter
Chapter 7 CL06 √ √ √ √ √ 20 r.

Memory and
Programmable Logic
7.1 Random-Access Memory
7.2 Memory Decoding
7.3 Read-Only Memory
7.4 Programmable Logic Array
7.5 Programmable Array Logic
Total 130hr

Assessment

Continuous Assessment Percentage

Total-50(%) F2F NF2F SLT

1 Attendance 0% √
(Mandatory)

1 Quiz 5% √ 1hr.

2 Lab-report 15 % √ √ 14hr

3 Assignment 10% √ √ 10hr

4 Mid exam 20% √ 2hr

Total 27 hr.

Final Exam Percentage 50 F2F NF2F SLT

(%)

Final Exam √ 3hr

Grand Total SLT 160 hr.

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 L = Lecture, T = Tutorial, P = Practical, O = Others, F2F = Face to Face, NF2F = Non Face to Face

Note: indicates the CLO based on the CLO’s numbering in item 9.

Special 1 MATLAB Software

requirements and
resources to 2 Computer lab
deliver the course
(e.g. software, 3 Simulation Room
computer lab,
simulation room 4
…etc.)
5

Textbook and 1 Morris M. Mano: Digital Design (4th Edition)

reference:
2 R. J. Tocci and N. S. Widmer: Digital Systems – Principles and
(note: ensure the Applications, 9th Ed, Prentice Hall, 2004

latest edition 3 Stephen Brown, ZvonkoVranesic: Fundamentals of Digital Logic with

/publication) Verilog Design, McGraw-Hill Science/Engineering/Math; 1st edition 2002

4 T.L. Floyd: Digital Fundamentals, 9th edition, Prentice Hall

8. Course Instructors

S.No 1 2 3
Instructor Mr.Tadesse Hailu Mr.Tesfaye Benti Mr.Gemechu Dengi
and contact tade1739@gmail.com Email: Email:
address Phone: 0910033082 tbentib@gmail.com gdengia@gmail.com
Office:(B504) R-7 Phone:
Ph :961091363: 917039172
Office: Office(B606)
Remark

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 9. Course Calendar
Weeks T and L activities Assessment Types CLO Assessment
Wk1 Chapter-1 CLO1
Wk2 Ch-2Lect and Lab
Wk3 Ch-2 Lect and Lab Assignment 1 CLO 1
Wk4 Ch-2 Lect and lab
Wk5 Ch-2 Lect and lab quiz
Wk6 Ch-3 Lect and lab
Wk7 Mid term CLO 1,2
Wk8 Ch-3 lect and lab
Wk9 Ch-3 lect and lab Assignment 2 CLO 3
Wk10 Ch-4 lect and lab
Wk11 Ch-4 lect and lab
Wk12 Ch-5 lecture Clo4
Wk13 Ch-5 Lecture
Wk14 Ch-6 Lecture Clo5
Wk-15 Ch-6 Lecture
Wk16 Final Exam CLO1,2,3,4,5

10.Pass Requirements
 Attempt all assessment
 Must achieve 40% and above in Final Exam
 80% Lecture attendance
 100% Laboratory attendance
11. Academic Integrity
12.Grading Policy
Raw Mark Corresponding
Corresponding fixed number Grade
interval (100%) Letter Grade

[90,100] A+ 4.0

[85,90) A 4.0

[80,85) A- 3.75

[75,80) B+ 3.5

[70,75) B 3.0

[65,70) B- 2.75

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 [60,65) C+ 2.5

[50,60) C 2.0

[45,50) C- 1.75

[40,45) D 1.0

[0,40) F 0

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