IMEL7002

Digital Integrated Circuits

2022
Instructors:
Prof. Chi Hang, Chan (Ivor)
University of Macau
Institute of Microelectronic

Lecture 2: Process and Inverter

 CMOS Process

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2 Lecture 2 2
 A Modern CMOS Process
gate-oxide

TiSi2 AlCu

SiO2
Tungsten

poly
p-well n-well SiO2
n+ p-epi p+

p+

Dual-Well Trench-Isolated CMOS Process

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3 Lecture 2 3
 Circuit Under Design
VDD VDD

M2
M4

Vin Vout Vout2

M1 M3

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4 Lecture 2 4
 Its Layout View

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5 Lecture 2 5
 CMOS Process Walk-Through
p-epi (a) Base material: p+ substrate
with p-epi layer
p+

Si N
34
SiO (b) After deposition of gate-oxide and
p-epi 2 sacrificial nitride (acts as a
buffer layer)
p+

(c) After plasma etch of insulating

trenches using the inverse of
the active area mask
p+

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6 Lecture 2 6
 CMOS Process Walk-Through
SiO
2
(d) After trench filling, CMP
planarization, and removal of
sacrificial nitride

n
(e) After n-well and
V adjust implants
Tp

p
(f) After p-well and
V adjust implants
Tn

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7 Lecture 2 7
 CMOS Process Walk-Through
poly(silicon)

(g) After polysilicon deposition

and etch

n+ p+

(h) After n+ source/drain and

p+ source/drain implants. These
steps also dope the polysilicon.

SiO
2

(i) After deposition of SiO2

insulator and contact hole etch.

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8 Lecture 2 8
 CMOS Process Walk-Through
Al

(j) After deposition and

patterning of first Al layer.

Al
SiO
2
(k) After deposition of SiO 2
insulator, etching of via’s,
deposition and patterning of
second layer of Al.

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9 Lecture 2 9
 Advanced Metallization

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10 Lecture 2 10
 Advanced Metallization

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11 Lecture 2 11
 Design Rules

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12 Lecture 2 12
 3D Perspective

Polysilicon Aluminum

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 Design Rules

• Interface between designer and process engineer

• Guidelines for constructing process masks
• Unit dimension: Minimum line width
– scalable design rules: lambda parameter
– absolute dimensions (micron rules)

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14 Lecture 2 14
 CMOS Process Layers
Layer Color Representation

Well (p,n) Yellow

Active Area (n+,p+) Green
Select (p+,n+) Green
Polysilicon Red
Metal1 Blue
Metal2 Magenta
Contact To Poly Black
Contact To Diffusion Black
Via Black

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15 Lecture 2 15
Layers in 0.25 mm CMOS process

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16 Lecture 2 16
 Intra-Layer Design Rules
Same Potential Different Potential

9 2
0
Well or Polysilicon
6
10 2
3 3
Active Metal1
Contact
or Via 2
3 Hole 3
2 2 4
Metal2
Select

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17 Lecture 2 17
 Transistor Layout
Transistor

3 2

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18 Lecture 2 18
 Vias and Contacts
2
4
Via
1 1
5
Metal to
Metal to 1 Poly Contact
Active Contact 3 2

2
2

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19 Lecture 2 19
 Select Layer
2
Select
3
2

1
3 3

2 5

Well
Substrate

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20 Lecture 2 20
 CMOS Inverter Layout
GND In VD D

A A’

Out

(a) Layout

A A’
n
p-substrate Field
+ + Oxide
n p
(b) Cross-Section along A-A’

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21 Lecture 2 21
 Layout Editor

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22 Lecture 2 22
 Design Rule Checker

poly_not_fet to all_diff minimum spacing = 0.14 um.

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23 Lecture 2 23
 Sticks Diagram
V DD 3

In Out
• Dimensionless layout entities
• Only topology is important
• Final layout generated by
“compaction” program
1

GND

Stick diagram of inverter

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24 Lecture 2 24
 Packaging

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25 Lecture 2 25
 Packaging Requirements

• Electrical: Low parasitics

• Mechanical: Reliable and robust
• Thermal: Efficient heat removal
• Economical: Cheap

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26 Lecture 2 26
 Bonding Techniques
Wire Bonding

Substrate

Die

Pad

Lead Frame

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27 Lecture 2 27
 Tape-Automated Bonding (TAB)

Sprocket
hole

Film + Pattern Solder Bump

Die
Test
pads
Lead
frame Substrate

(b) Die attachment using solder bumps.

Polymer film

(a) Polymer Tape with imprinted

wiring pattern.

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28 Lecture 2 28
 Flip-Chip Bonding

Die

Solder bumps
Interconnect
layers

Substrate

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29 Lecture 2 29
 Package-to-Board Interconnect

(a) Through-Hole Mounting (b) Surface Mount

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30 Lecture 2 30
 Package Types

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31 Lecture 2 31
 Package Parameters

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32 Lecture 2 32
 Multi-Chip Modules

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33 Lecture 2 33
 Digital Integrated
Circuits

The Wire

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34 Lecture 2 34
 The Wire

transmitters receivers

schematics physical

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35 Lecture 2 35
Interconnect Impact on Chip

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36 Lecture 2 36
 Wire Models

All-inclusive model Capacitance-only

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37 Lecture 2 37
 Impact of Interconnect Parasitics

 Interconnect parasitics
 reduce reliability
 affect performance and power
consumption
 Classes of parasitics
 Capacitive
 Resistive
 Inductive

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38 Lecture 2 38
Nature of Interconnect

Local Interconnect Pentium Pro (R)

Pentium(R) II
Pentium (MMX)
Pentium (R)
Pentium (R) II

Global Interconnect
(Log Scale)
No of nets

SGlobal = SDie
SLocal = STechnology

Source: Intel
10 100 1,000 10,000 100,000
Length (u)
39
INTERCONNECT

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40 Lecture 2 40
Capacitance of Wire Interconnect

Vin Vout
Fanout
Simplified
Model CL

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41 Lecture 2 41
Capacitance: The Parallel Plate Model


cint  di WL S 1
S Cwire  
t di S  SL SL

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42 Lecture 2 42
Permittivity

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43 Lecture 2 43
 Fringing Capacitance

H W - H/2

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44 Lecture 2 44
 Fringing versus Parallel Plate

(from [Bakoglu89])

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45 Lecture 2 45
 Interwire Capacitance

fringing parallel

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46 Lecture 2 46
Impact of Interwire Capacitance

(from [Bakoglu89])

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47 Lecture 2 47
Wiring Capacitances (0.25 mm CMOS)

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48 Lecture 2 48
INTERCONNECT

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49 Lecture 2 49
Wire Resistance

R= L
HW

L Sheet Resistance
H Ro

R1 R2
W

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50 Lecture 2 50
Interconnect Resistance

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51 Lecture 2 51
Dealing with Resistance

 SelectiveTechnology Scaling
 Use Better Interconnect Materials
 reduce average wire-length
 e.g. copper, silicides
 More Interconnect Layers
 reduce average wire-length

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52 Lecture 2 52
Polycide Gate MOSFET
Silicide

PolySilicon

SiO2

n+ n+

Silicides: WSi 2, TiSi 2, PtSi 2 and TaSi

Conductivity: 8-10 times better than Poly

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53 Lecture 2 53
Sheet Resistance

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54 Lecture 2 54
Modern Interconnect

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55 Lecture 2 55
 Example: Intel 0.25 micron Process
5 metal layers
Ti/Al - Cu/Ti/TiN
Polysilicon dielectric

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56 Lecture 2 56
INTERCONNECT

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57 Lecture 2 57
 Interconnect
Modeling

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58 Lecture 2 58
 The Lumped Model

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59 Lecture 2 59
 The Lumped RC-Model The
Elmore Delay

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60 Lecture 2 60
 The Ellmore Delay RC Chain

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61 Lecture 2 61
 Wire Model

Assume: Wire modeled by N equal-length segments

For large values of N:

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62 Lecture 2 62
 Step-response of RC wire as a
function of time and space

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63 Lecture 2 63
RC-Models

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64 Lecture 2 64
 Driving an RC-line
Rs
(rw,cw,L)
V out

Vin

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65 Lecture 2 65
Design Rules of Thumb

 rc delays should only be considered when

tpRC >> tpgate of the driving gate
Lcrit >>  tpgate/0.38rc
 rc delays should only be considered when the
rise (fall) time at the line input is smaller than
RC, the rise (fall) time of the line
trise < RC
 when not met, the change in the signal is slower
than the propagation delay of the wire

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66 Lecture 2 66
 Digital Integrated
Circuits
A Design Perspective

The Inverter

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67 Lecture 2 67
The CMOS Inverter: A First Glance
VDD

Vin
Vout

CL

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68 Lecture 2 68
CMOS Inverters
VDD

PMOS

2
Out
In
Metal1

Polysilicon

NMOS
GND

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69 Lecture 2 69
 CMOS Inverter
First-Order DC Analysis
VDD VDD

Rp
VOL = 0
Vout VOH = VDD
Vin = 0
Vout VM = f(Rn, Rp)
Vin = 1
Rn

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70 Lecture 2 70
 CMOS Inverter:
First Order Transient Response
VDD

tpHL = f(Ron.CL)
= 0.69 RonCL
ln(0.5)
Vout
Vout
1 VDD
CL
Ron
0.5
0.36

t
Vin = V DD RonCL

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71 Lecture 2 71
 Voltage Transfer
Characteristic

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72 Lecture 2 72
PMOS Load Lines

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73 Lecture 2 73
 CMOS Inverter Load Characteristics
I Dn
Vin = 0 Vin = 2.5

PMOS Vin = 0.5 Vin = 2 NMOS

Vin = 1 Vin = 1.5

Vin = 1.5 Vin = 1

Vin = 1.5 Vin = 1

Vin = 2 Vin = 0.5

Vin = 2.5 Vin = 0

Vout

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74 Lecture 2 74
 CMOS Inverter VTC
Vout NMOS off
PMOS res
2.5 NMOS s at
PMOS res
2

NMOS sat
1.5

PMOS sat
1

NMOS res
PMOS sat NMOS res
0.5

PMOS off

0.5 1 1.5 2 2.5 Vin

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75 Lecture 2 75
 Switch Threshold as a function of
Transistor Ratio
1.8

1.7

1.6

1.5

1.4
V (V)

1.3
M

1.2

1.1

0.9

0.8 0 1
10 10
W p /W n 10
EE141
 Determining VIH and VIL
Vout

VOH

VM

Vin
VOL
VIL VIH

A simplified approach

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77 Lecture 2 77
 Inverter Gain
0

-2

-4

-6

-8
gain

-10

-12

-14

-16

-180 0.5 1 1.5 2 2.5

V (V)
in

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78 Lecture 2 78
 Gain as a function of VDD

2.5 0.2

2
0.15

1.5

(V)
V out (V)

0.1

Vo
ut
1

0.05
0.5

Gain=-1
0
0 0 0.05 0.1 0.15 0.2
0 0.5 1 1.5 2 2.5
V (V)
V (V) in
in

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79 Lecture 2 79
 Simulated VTC
2.5

1.5
(V)
out
V

0.5

0
0 0.5 1 1.5 2 2.5
V (V)
in

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80 Lecture 2 80
Impact of Process Variations
2.5

2
Good PMOS
Bad NMOS
1.5
Vout(V)

Nominal

1 Good NMOS
Bad PMOS
0.5

0
0 0.5 1 1.5 2 2.5
Vin (V)

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81 Lecture 2 81
 Propagation Delay

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82 Lecture 2 82
 CMOS Inverter Propagation Delay
Approach 1
VDD

Vin = V DD tpHL = CL Vswing/2

Iav

Vout CL
~
Iav CL kn VDD

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83 Lecture 2 83
 CMOS Inverter Propagation Delay
Approach 2
VDD

tpHL = f(Ron.CL)
= 0.69 RonCL
ln(0.5)
Vout
Vout
1 VDD
CL
Ron 0.5
0.36

t
Vin = V DD RonCL

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84 Lecture 2 84
CMOS Inverters
VDD

PMOS

1.2mm
=2
Out
In
Metal1

Polysilicon

NMOS
GND

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85 Lecture 2 85
 Transient Response
3

2.5
?
2
tp = 0.69 CL (Reqn+Reqp)/2
1.5
(V)

tpHL
out

tpLH
V

0.5

-0.5
0 0.5 1 1.5 2 2.5
-10
t (sec)
x 10

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86 Lecture 2 86
 Design for Performance

 Keep capacitances small

 Increase transistor sizes
 watch out for self-loading!
 Increase VDD (????)

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87 Lecture 2 87
 Delay as a function of VDD
5 .5

4 .5

4
t (normalized)

3 .5

3
p

2 .5

1 .5

1
0 .8 1 1 .2 1 .4 1.6 1 .8 2 2 .2 2 .4
V (V)
DD

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88 Lecture 2 88
 Device Sizing
-11
x 10
3.8

3.6 (for fixed load)

3.4

3.2
t (sec)

3
p

2.8
Self-loading effect:
2.6 Intrinsic capacitances
dominate
2.4

2.2

2
2 4 6 8 10 12 14
S

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89 Lecture 2 89
 NMOS/PMOS ratio
-11
x 10
5

tpLH tpHL
4.5

tp  = Wp/Wn
t (sec)

4
p

3.5

3
1 1.5 2 2.5 3 3.5 4 4.5 5


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90 Lecture 2 90
 Impact of Rise Time on Delay
0.35

0.3
tpHL(nsec)

0.25

0.2

0.15
0 0.2 0.4 0.6 0.8 1
trise (nsec)

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91 Lecture 2 91
 Inverter Sizing

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92 Lecture 2 92
 Inverter Chain

In Out

CL

If CL is given:
- How many stages are needed to minimize the delay?
- How to size the inverters?

May need some additional constraints.

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93 Lecture 2 93
 Inverter Delay
• Minimum length devices, L=0.25mm
• Assume that for WP = 2WN =2W 2W
• same pull-up and pull-down currents
• approx. equal resistances RN = RP
• approx. equal rise tpLH and fall tpHL delays
W
• Analyze as an RC network

Delay (D): tpHL = (ln 2) RNCL tpLH = (ln 2) RPCL

W
Load for the next stage: C gin 3 Cunit
Wunit
 Inverter with Load
Delay

RW

CL
RW Load (CL)
tp = k RWCL
k is a constant, equal to 0.69
Assumptions: no load -> zero delay
Wunit = 1

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95 Lecture 2 95
 Inverter with Load
CP = 2Cunit Delay
2W

W
Cint CL

Load
CN = Cunit

Delay = kRW(Cint + CL) = kRWCint + kRWCL = kRW Cint(1+ CL /Cint)

= Delay (Internal) + Delay (Load)

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96 Lecture 2 96
Delay Formula

Delay ~ RW C int  C L 

t p  kR W C int 1  C L / C int   t p 0 1  f /  

Cint = Cgin with   1

f = CL/Cgin - effective fanout
R = Runit/W ; Cint =WCunit
tp0 = 0.69RunitCunit

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97 Lecture 2 97
 Apply to Inverter Chain
In Out

1 2 N CL

tp = tp1 + tp2 + …+ tpN

 C gin, j1 
t pj ~ Runit Cunit 1 
 C 
 gin, j 
N 
N
C gin, j1 
t p   t p, j  t p0  1 , C gin,N 1  C L
j1 i1  Cgin, j 

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98 Lecture 2 98
Optimal Tapering for Given N

Delay equation has N - 1 unknowns, Cgin,2 – Cgin,N

Minimize the delay, find N - 1 partial derivatives

Result: Cgin,j+1/Cgin,j = Cgin,j/Cgin,j-1

Size of each stage is the geometric mean of two neighbors

C gin, j  C gin, j 1C gin, j1
- each stage has the same effective fanout (Cout/Cin)
- each stage has the same delay

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99 Lecture 2 99
Optimum Delay and Number of Stages

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100 Lecture 2 100
Example

In Out

1 f f2 CL= 8 C1
C1

CL/C1 has to be evenly distributed across N = 3 stages:

f 38 2

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101 Lecture 2 101
Optimum Number of Stages
For a given load, CL and given input capacitance Cin
Find optimal sizing f
ln F
C L  F Cin  f N Cin with N 
ln f
t p0 ln F  f  

t p  Nt p0 F /  1 
1/ N
  
  ln f ln f


tp t p0 ln F ln f 1  f
  0
f  ln2 f
For  = 0, f = e, N = lnF f  exp1  f 

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102 Lecture 2 102
 Optimum Effective Fanout f
Optimum f for given process defined by 
f  exp1  f 
fopt = 3.6
for =1

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103 Lecture 2 103
 Impact of Self-Loading on tp
No Self-Loading, =0 With Self-Loading =1

60.0

40.0
u/ln(u)

x=10,000

x=1000

20.0 x=100

x=10

0.0
1.0 3.0 5.0 7.0
u

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104 Lecture 2 104
 Normalized delay function of F

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105 Lecture 2 105
 Buffer Design
N f tp
1 64 1 64 65

1 8 64
2 8 18

1 4 16 64 3 4 15

1 64 4 2.8 15.3
2.8 8 22.6

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106 Lecture 2 106