Lecture No.

Course Name

Electronic (3)

Instructor Dr. Samia Heshmat

email samia.heshmat@aswu.edu.eg 30 September 2024

CMOS VLSI Design

 Course Objectives
◼ To know semiconductor devices and technology of
semiconductor
◼ How to use VLSI Design system to make sample for
devices
◼ To study basic steps of fabrication process ( heated
oxidation and impurities propagation – depositing
of conducting layer – photographic – fabrication by
using ions penetration)

CMOS VLSI Design Slide 2

 Course Objective
◼ Design process of Integrated circuit and test of
integrated circuit
◼ Study some devices examples: changing of charging
devices (CCD) – microwave devices – fiber optics
devices and famous integrated circuit 741, 565, 555

CMOS VLSI Design Slide 3

 Course Format
• 8 ~13 lectures
• Lectures’ Quiz :→5
• Lab and PPT work : → 15
• Class Works : →15
• Midterm : → 15
• Final exam : → 100
• Total degree : →150

CMOS VLSI Design Slide 4

References - Textbooks
Main book
– Weste and Harris.

– CMOS VLSI Design

(4th edition)

❑ Credits: David Harris

❑ Harvey Mudd College

❑ (Material taken/adapted from

Harris’ lecture notes)

CMOS VLSI Design Slide 5

References - Textbooks
2nd book

– Jan M. Rabaey.

– Digital Integrated Circuits

(1st edition)

CMOS VLSI Design Slide 6

 Outline
❑ A Brief History

❑ Preview

❑ MOS Transistors

❑ CMOS Logic

CMOS VLSI Design Slide 7

 A Brief History
❑ 1958: First integrated circuit
– Flip-flop using two transistors
– Built by Jack Kilby at Texas Instruments
❑ 2003
– Intel Pentium 4 processor (55 million transistors)
– 512 Mbit DRAM (> 0.5 billion transistors)
❑ 53% compound annual growth rate over 45 years
– No other technology has grown so fast so long
❑ Driven by miniaturization of transistors
– Smaller is cheaper, faster, lower in power!
– Revolutionary effects on society

CMOS VLSI Design Slide 8

 Annual Sales
− 1018 transistors manufactured in 2003

– 100 million for

every human on
the planet
– In 2014,
semiconductor
production facilities
made some 250
billion billion (250 x
1018) transistors.

CMOS VLSI Design Slide 9

Invention of the Transistor
❑ Vacuum tubes ruled in first half of 20th century Large,
expensive, power-hungry, unreliable
❑ 1947: first point contact transistor
– John Bardeen and Walter Brattain at Bell Labs
– Read Crystal Fire
by Riordan, Hoddeson

CMOS VLSI Design Slide 10

 Transistor Types
❑ Bipolar transistors
– npn or pnp silicon structure
– Small current into very thin base layer controls
large currents between emitter and collector
– Base currents limit integration density
❑ Metal Oxide Semiconductor Field Effect Transistors
– nMOS and pMOS MOSFETS
– Voltage applied to insulated gate controls current
between source and drain
– Low power allows very high integration

CMOS VLSI Design Slide 11

MOS Integrated Circuits
❑ 1970’s processes usually had only nMOS transistors
– Inexpensive, but consume power while idle

Intel 1101 256-bit SRAM Intel 4004 4-bit Proc

❑ 1980s-present: CMOS processes for low idle power
CMOS VLSI Design Slide 12ＺＱz
 Moore’s Law
❑ 1965: Gordon Moore observed that plotting the number of
transistors that can be most economically manufactured on a
chip gives a straight line on a semilog scale
❑ Transistor counts have doubled every 26 months
1,000,000,000

100,000,000
Integration Levels
Pentium 4
Pentium III
10,000,000 Pentium II
Pentium Pro SSI: 10 gates
Transistors

Pentium
Intel486
1,000,000

100,000
80286
Intel386
MSI: 1000 gates
8086
10,000

4004
8008
8080
LSI: 10,000 gates
1,000

VLSI: > 10k gates

1970 1975 1980 1985 1990 1995 2000

Year

CMOS VLSI Design Slide 13

 Preview
❑ As the number of transistors on a chip has grown
exponentially, designers have come to rely on
increasing levels of automation to seek corresponding
productivity gains.
❑ Many designers spend much of their effort specifying
functions with hardware description languages and
seldom look at actual transistors.
❑ The best way to learn VLSI design is by doing it. A set
of laboratory exercises are available at
www.cmosvlsi.com to guide you through the design of
your own microprocessor chip.

CMOS VLSI Design Slide 14

 MOS Transistors
❑ Semiconductor devices are electronic
components that exploit the electronic properties of
semiconductor materials, principally Silicon (Si -14),
Germanium (Ge - 32), and as well as organic
semiconductors.
❑ Semiconductor devices have replaced thermionic
devices (vacuum tubes) in most applications. They use
electronic-conduction in the solid state as opposed to
the gaseous state or thermionic emission in a high
vacuum.
CMOS VLSI Design Slide 15
 MOS Transistors
❑ Semiconductor devices are manufactured both as
single discrete devices and as integrated
circuits (ICs), which consist of a number - from a few
(as low as two) to billions - of devices manufactured
and interconnected on a single semiconductor
substrate, or wafer.

❑ Semiconductor materials are useful because their

behavior can be easily manipulated by the addition of
impurities, known as doping.

CMOS VLSI Design Slide 16

 MOS Transistors
❑ Semiconductor conductivity can be controlled by
introduction of an electric or magnetic field, by
exposure to light or heat; thus, semiconductors can
make excellent sensors.

❑ Current conduction in a semiconductor occurs via

mobile or "free“ electrons and holes, collectively known
as charge carriers.

CMOS VLSI Design Slide 17

 MOS Transistors
❑ Doping a semiconductor such as Silicon with a small
amount of impurity atoms, such as Phosphorus (P) or
Boron (B), greatly increases the number of free
electrons or holes within the semiconductor.

❑ When a doped semiconductor contains excess holes it

is called “p-type”, and when it contains excess free
electrons it is known as “n-type”, where p (positive
for holes) or n (negative for electrons) is the sign of the
charge of the majority mobile charge carriers.

CMOS VLSI Design Slide 18

 MOS Transistors
❑ The semiconductor material used in devices is doped
under highly controlled conditions in a fabrication
facility, to control precisely the location and
concentration of p- and n-type dopants. The junctions
which form where n-type and p-type semiconductors
join together are called p-n junction.

CMOS VLSI Design Slide 19

 MOS Transistors
❑ Integrated circuits: many transistors on one chip.

❑ Very Large Scale Integration (VLSI): very many

❑ Complementary Metal Oxide Semiconductor

– Fast, cheap, low power transistors

❑ Today: How to build your own simple CMOS chip

– CMOS transistors
– Building logic gates from transistors
– Transistor layout and fabrication
CMOS VLSI Design Slide 20
 Silicon Lattice
❑ Transistors are built on a silicon substrate
❑ Silicon is a Group IV material
❑ Forms crystal lattice with bonds to four neighbors

Si Si Si

Si Si Si

Si Si Si

CMOS VLSI Design Slide 21

 Dopants
❑ Silicon is a semiconductor
❑ Pure silicon has no free carriers and conducts poorly
❑ Adding dopants increases the conductivity
❑ Group V: extra electron (n-type)
❑ Group III: missing electron, called hole (p-type)

Si Si Si Si Si Si
- +

+ -
Si As Si Si B Si

Si Si Si Si Si Si

CMOS VLSI Design Slide 22

 p-n Junctions
❑ A junction between p-type and n-type semiconductor
forms a diode.
❑ Current flows only in one direction

p-type n-type

anode cathode

CMOS VLSI Design Slide 23

 nMOS
❑ Four terminals: gate, source, drain, body
❑ Gate – oxide – body stack looks like a capacitor
– Gate and body are conductors
– SiO2 (oxide) is a very good insulator
– Called metal – oxide – semiconductor (MOS)
capacitor Source Gate Drain
Polysilicon
– Even though gate is SiO2
no longer made of metal
n+ n+

p bulk Si

CMOS VLSI Design Slide 24

 nMOS Operation
❑ Body is commonly tied to ground (0 V)
❑ When the gate is at a low voltage:
– P-type body is at low voltage
– Source-body and drain-body diodes are OFF
– No current flows, transistor is OFF
Source Gate Drain
Polysilicon
SiO2

0
n+ n+
S D
p bulk Si

CMOS VLSI Design Slide 25

 nMOS Operation
❑ When the gate is at a high voltage:
– Positive charge on gate of MOS capacitor
– Negative charge attracted to body
– Inverts a channel under gate to n-type
– Now current can flow through n-type silicon from
source through channel to drain, transistor is ON
Source Gate Drain
Polysilicon
SiO2

1
n+ n+
S D
p bulk Si

CMOS VLSI Design Slide 26

 pMOS
❑ Similar, but doping and voltages reversed
– Body tied to high voltage (VDD)
– Gate low: transistor ON
– Gate high: transistor OFF
– Bubble indicates inverted behavior
Source Gate Drain
Polysilicon
SiO2

p+ p+

n bulk Si

CMOS VLSI Design Slide 27

 Power Supply Voltage
❑ GND = 0 V
❑ In 1980’s, VDD = 5V
❑ VDD has decreased in modern processes
– High VDD would damage modern tiny transistors
– Lower VDD saves power
❑ VDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, …

CMOS VLSI Design Slide 28

Transistors as Switches
❑ We can view MOS transistors as electrically
controlled switches
❑ Voltage at gate controls path from source to drain
g=0 g=1

d d d
nMOS g OFF
ON
s s s

d d d

pMOS g OFF
ON
s s s

CMOS VLSI Design Slide 29

CMOS Logic

CMOS VLSI Design Slide 30

 CMOS Inverter

A Y VDD
0
1

A Y

A Y
GND
CMOS VLSI Design Slide 31
 CMOS Inverter

A Y VDD
0
1 0 OFF
A=1 Y=0

ON
A Y
GND
CMOS VLSI Design Slide 32
 CMOS Inverter

A Y VDD
0 1
1 0 ON
A=0 Y=1

OFF
A Y
GND
CMOS VLSI Design Slide 33
 CMOS NAND Gate
A B Y
0 0
0 1 Y
1 0 A
1 1
B

CMOS VLSI Design Slide 34

 CMOS NAND Gate
A B Y
0 0 1 ON ON
0 1 Y=1
A=0
1 0 OFF
1 1
B=0
OFF

CMOS VLSI Design Slide 35

 CMOS NAND Gate
A B Y
0 0 1 OFF ON
0 1 1 Y=1
A=0
1 0 OFF
1 1
B=1
ON

CMOS VLSI Design Slide 36

 CMOS NAND Gate
A B Y
0 0 1 ON OFF
0 1 1 Y=1
A=1
1 0 1 ON
1 1
B=0
OFF

CMOS VLSI Design Slide 37

 CMOS NAND Gate
A B Y
0 0 1 OFF OFF
0 1 1 Y=0
A=1
1 0 1 ON
1 1 0
B=1
ON

CMOS VLSI Design Slide 38

 CMOS NOR Gate
A B Y
0 0 1 A
0 1 0
1 0 0 B
1 1 0 Y

CMOS VLSI Design Slide 39

 3-input NAND Gate
❑ Y pulls low if ALL inputs are 1
❑ Y pulls high if ANY input is 0

CMOS VLSI Design Slide 40

 3-input NAND Gate
❑ Y pulls low if ALL inputs are 1
❑ Y pulls high if ANY input is 0

Y
A
B
C

CMOS VLSI Design Slide 41

 Complementary CMOS
❑ Complementary CMOS logic gates pMOS
pull-up

– nMOS pull-down network

network
inputs
– pMOS pull-up network output

– static CMOS nMOS

pull-down
network

Pull-up Pull-up ON
OFF From table: The output of a CMOS logic
Pull-down Z (float) 1 gate can be in four states.
OFF The 1 and 0 levels - encountered
Pull-down 0 X where either the pull-up or pull-down
ON (crowbar) is OFF and the other structure is ON.
When both pull-up and pull-down The crowbarred (or contention) X level
are OFF, the high-impedance or exists when both pull-up and pull-down
floating Z output state results. are simultaneously turned ON
CMOS VLSI Design Slide 42
 CMOS Gate Design
❑ Activity:
– Sketch a 4-input CMOS NOR gate

A
B
C
D
Y

CMOS VLSI Design Slide 43

 CMOS Gate Design
❑ Activity:
– Sketch a 3-input CMOS NAND gate

Y
A
B
C

CMOS VLSI Design Slide 44

 Series and Parallel
❑
a a a a
nMOS: 1 = ON g1
a
0 0 1 1

❑
g2
pMOS: 0 = ON b
0
b
1
b
0
b
1
b
(a) OFF OFF OFF ON

❑ Series: both must be ON a a a a a

❑ Parallel: either can be ON g1

g2
0

0
0

1
1

0
1

1
b b b b b
(b) ON OFF OFF OFF

a a a a a

g1 g2 0 0 0 1 1 0 1 1
b b b b b

(c) OFF ON ON ON

a a a a a

g1 g2 0 0 0 1 1 0 1 1
b b b b b

(d) ON ON ON OFF

CMOS VLSI Design Slide 45

Conduction Complement
❑ Complementary CMOS gates always produce 0 or 1
❑ Ex: NAND gate
– Series nMOS: Y=0 when both inputs are 1
– Thus Y=1 when either input is 0
– Requires parallel pMOS Y
A
B
❑ Rule of Conduction Complements
– Pull-up network is complement of pull-down
– Parallel -> series, series -> parallel

CMOS VLSI Design Slide 46

 Compound Gates
A compound gate performing a more complex logic function
in a single stage of logic is formed by using a combination of
series and parallel switch structures.
A C A C
B D B D
❑ Compound gates (a) (b)
can do any inverting
C D
function A B C D
A B

❑ Ex: (c)
(d)

C D
A
A B
B
Y Y
C
A C
D
B D
(f)

(e)

Y = A B + C D (AND-AND-OR-INVERT, AOI22)
CMOS VLSI Design Slide 47
 Example: O3AI
❑ Y = ( A+ B + C) D
OR-AND-INVERT-3-1 (OAI31) gate.

CMOS VLSI Design Slide 48

 Example: O3AI
❑ Y = ( A+ B + C) D

A
B
C D
Y
D
A B C

CMOS VLSI Design Slide 49

 Signal Strength
❑ Strength of signal
– How close it approximates ideal voltage source
❑ VDD and GND rails are strongest 1 and 0
❑ nMOS pass strong 0
– But degraded or weak 1
❑ pMOS pass strong 1
– But degraded or weak 0
❑ Thus nMOS are best for pull-down network

CMOS VLSI Design Slide 50

 Pass Transistors
❑ Transistors can be used as switches
When an nMOS or pMOS is used alone as an imperfect switch,

s d

s d

CMOS VLSI Design Slide 51

 Pass Transistors
❑ Transistors can be used as switches
When an nMOS or pMOS is used alone as an imperfect switch,
g g=0 Input g = 1 Output
s d 0 strong 0
s d
g=1 g=1
s d 1 degraded 1

g g=0 Input Output

g=0
s d 0 degraded 0
s d
g=1
g=0
s d strong 1

CMOS VLSI Design Slide 52

 Transmission Gates
❑ Single pass transistors produce degraded outputs

CMOS VLSI Design Slide 53

 Transmission Gates
❑ Single pass transistors produce degraded outputs
❑ Complementary Transmission gates pass both 0
and 1 well
Input Output
g = 0, gb = 1 g = 1, gb = 0
g
a b 0 strong 0
a b g = 1, gb = 0 g = 1, gb = 0
a b 1 strong 1
gb

g g g
a b a b a b
gb gb gb

CMOS VLSI Design Slide 54

Compound Gates

Pass Transistors

Transmission Gates

CMOS VLSI Design Slide 55

Compound Gates: an example is AND-OR-Invert (AOI)
logic constructed from the combination of one or more AND
gates followed by a NOR gates. Construction of AOI cells is
particularly efficient using CMOS technology where the
total number of transistor gates can be compared to the
same construction using NAND logic or NOR logic. The
complement of AOI Logic is OR-AND-Invert (OAI) logic
where the OR gates precede a NAND gate.
Pass Transistors

Transmission Gates

CMOS VLSI Design Slide 56

Compound Gates
Pass Transistors: Transistors are used as switches to
pass logic levels between nodes of a circuit, instead of as
switches connected directly to supply voltages. This
reduces the number of active devices, but has the
disadvantage that the difference of the voltage between
high and low logic levels decreases at each stage. Each
transistor in series is less saturated at its output than at its
input.
Transmission Gates

CMOS VLSI Design Slide 57

Compound Gates

Pass Transistors
Transmission Gates: made up of two MOS transistors,
nMOS and a pMOS are connected in parallel - only the
drain and source terminals of the two transistors are
connected together. Their gate terminals are connected to
each other via a NOT gate (inverter), to form the control
terminal.

CMOS VLSI Design Slide 58

 Tristates
❑ Tristate buffer produces Z when not enabled

EN
EN A Y
0 0 A Y
0 1
1 0
EN
1 1
A Y

EN

CMOS VLSI Design Slide 59

 Tristates
❑ Tristate buffer produces Z when not enabled
EN A Y
EN
0 0 Z
0 1 Z A Y
1 0 0
1 1 1
EN
It is a device that allows you to control when an
output signal makes it to the bus. When the tri- A Y
state buffer's control bit is active, the input of
the device makes it to the output. This is when EN
the "valve" is open.
CMOS VLSI Design Slide 60
 Nonrestoring Tristate
❑ Transmission gate acts as tristate buffer
– Only two transistors
– But nonrestoring
• Noise on A is passed on to Y

EN

A Y

EN
CMOS VLSI Design Slide 61
 Tristate Inverter
❑ Tristate inverter produces restored output
– Violates conduction complement rule
– Because we want a Z output

A
EN
Y
EN

CMOS VLSI Design Slide 62

 Tristate Inverter
❑ Tristate inverter produces restored output
– Violates conduction complement rule
– Because we want a Z output
A A
A
EN
Y Y Y
EN

EN = 0 EN = 1
Y = 'Z' Y=A

CMOS VLSI Design Slide 63

 Multiplexers
❑ A multiplexer chooses the output from among
several inputs based on a select signal.
❑ 2:1 multiplexer chooses between two inputs
chooses input D0 when the select is 0 and input D1
when the select is 1. S

S D1 D0 Y D0 0
Y
0 X 0
D1 1
0 X 1
1 0 X
1 1 X

CMOS VLSI Design Slide 64

 Multiplexers
❑ 2:1 multiplexer chooses between two inputs
chooses input D0 when the select is 0 and input D1
when the select is 1.

S
S D1 D0 Y
0 X 0 0 D0 0
0 X 1 1
Y
D1 1
1 0 X 0
1 1 X 1

CMOS VLSI Design Slide 65

 Gate-Level Mux Design
❑ Y = SD1 + SD0 (too many transistors)
❑ How many transistors are needed?

CMOS VLSI Design Slide 66

 Gate-Level Mux Design
❑ Y = SD1 + SD0 (too many transistors)
❑ How many transistors are needed? 20

D1
S Y
D0

D1 4 2
S 4 2 Y
D0 4 2
2

CMOS VLSI Design Slide 67

 Transmission Gate Mux
❑ Nonrestoring mux uses two transmission gates

CMOS VLSI Design Slide 68

 Transmission Gate Mux
❑ Nonrestoring mux uses two transmission gates
– Only 4 transistors
S

D0
S Y
D1

CMOS VLSI Design Slide 69

 Inverting Mux
❑ Inverting multiplexer
– Use compound AOI22
– Or pair of tristate inverters
– Essentially the same thing
❑ Noninverting multiplexer adds an inverter

D0 S D0 D1 S
S D1 S S
Y Y D0 0
S S S S Y
D1 1

CMOS VLSI Design Slide 70

 4:1 Multiplexer
❑ 4:1 mux chooses one of 4 inputs using two selects

CMOS VLSI Design Slide 71

 4:1 Multiplexer
❑ 4:1 mux chooses one of 4 inputs using two selects
– Two levels of 2:1 muxes
– Or four tristates S1S0 S1S0 S1S0 S1S0

D0
S0 S1

D0 0
D1
D1 1
0
Y Y
1
D2 0 D2
D3 1

D3

CMOS VLSI Design Slide 72

 D Latch
❑ When CLK = 1, latch is transparent
– D flows through to Q like a buffer
❑ When CLK = 0, the latch is opaque
– Q holds its old value independent of D
❑ transparent latch or level-sensitive latch

CLK CLK

D
Latch

D Q
Q

CMOS VLSI Design Slide 73

 D Latch Design
❑ Multiplexer chooses D or old Q

CLK
CLK
D Q Q
1
Q D Q
0
CLK CLK

CLK

CMOS VLSI Design Slide 74

 D Latch Operation
Q Q
D Q D Q

CLK = 1 CLK = 0

CLK

CMOS VLSI Design Slide 75