®

Supply Chain 4.0

Printed Circuit Engineering Association

pcdandf.com
circuitsassembly.com
May 2022

T
H
E Filthy
FACTORY
Is cleaning doing
more harm than good?

4 Identifying Bandwidth
4 Embedded Passive Considerations
4 Vanguard EMS Gets Ahead
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 MAY 2022 • VOL. 39 • NO. 5

FIRST PERSON
6 THE ROUTE PRINTED CIRCUIT


Live shows are worth the wait.
Mike Buetow DESIGN & FAB
MONEY MATTERS
16 ROI
Supply Chain 4.0. FEATURES
Peter Bigelow 24 SIGNAL DEGRADATION
Bandwidth for Modeling
17 BOARD BUYING and Measuring PCB Interconnects
A simple, practical way to identify bandwidth with a numerical
Negotiate everywhere.
analysis of defects in a single bit or single symbol response.
Greg Papandrew by YURIY SHLEPNEV, PH.D.

32 RF DESIGN
Embedded Resistor Copper Foil
TECH TALK for mmWave Applications
The rush of equipment for more RF applications is being
18 DESIGNER’S NOTEBOOK deployed across the world, with 5G and millimeter wave (mmWave) communications
Via options. expanding into the commercial space to take advantage of the wider bandwidth,
higher data rates and low latency that these frequency bands offer.
John Burkhert, Jr. by THOMAS SLEASMAN

22 MATERIAL GAINS 36 TEST BOARDS

Build back smarter. Revamping the SMTA Miniaturization Test Vehicle

Rev. 3.0 will incorporate user input. What should be on the next layout?
Alun Morgan by CHRYS SHEA

37 DECONTAMINATION cover story

53 GETTING LEAN
Why Lean Six Sigma?
The Risks of Electronic Hardware Exposure to Disinfectants
When fogging large production areas and office locations, airborne disinfectants
Filemon Sagrero not only travel to the general locations but are drawn into the HVAC air handling
systems, redepositing contamination throughout the system. Even when hardware
is covered during fogging, the risk of contamination grows every time.
55 SEEING IS BELIEVING by TERRY MUNSON and PHIL ISAACS
One-hour stand.
Robert Boguski 47 EMS
Vanguard EMS: Manufacturing the Smarter Way
How an EMS tracks defects by tying flying probe test to its novel MES.
57 SCREEN PRINTING by MICHAEL L. MARTEL
Green lit.
Clive Ashmore

60 TECHNICAL ABSTRACTS
ON PCB CHAT (pcbchat.com)
LATEST ECAD MARKET DATA
with WALLY RHINES

DEPARTMENTS NEW HDP INITIATIVES

with JACK FISHER and MADAN JAGERNAUTH
8 AROUND THE WORLD
14 MARKET WATCH NICKEL-LESS SURFACE FINISHES
with KUNAL SHAH
58 OFF THE SHELF
THE CADENCE-DASSAULT SYSTÈMES INTEGRATION
with MICHAEL JACKSON and STÉPHANE DECLEE

A Printed Circuit Engineering Association, Inc. publication. All rights reserved.

 ®

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VICE PRESIDENT, SALES & MARKETING
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MEMBERS
CHIEF CONTENT OFFICER
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PCEA.NET Eriko Yamato COLUMNISTS AND ADVISORS
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THE PRINTED CIRCUIT ENGINEERING ASSOCIATION, INC. BRANDS:
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PCB Update....................................................................pcbupdate.com SALES
PODCASTS VICE PRESIDENT, SALES & MARKETING
PCB Chat............................................................................pcbchat.com Frances Stewart 678-817-1286 | frances@pcea.net
EVENTS SENIOR SALES EXECUTIVE
PCB West........................................................................... pcbwest.com Brooke Anglin 404-316-9018 | brooke@pcea.net
PCB East............................................................................pcbeast.com
EDUCATION REPRINTS
PCB2Day........................................................................... pcb2day.com brooke@pcea.net
Printed Circuit University...........................printedcircuituniversity.com
AWARDS PROGRAMS EVENTS/TRADE SHOWS
Service Excellence Awards....................................circuitsassembly.com
EXHIBIT SALES
NPI Awards...........................................................circuitsassembly.com
pcdandf.com Frances Stewart 678-817-1286 | frances@pcea.net
DATABASE TECHNICAL CONFERENCE
Directory of EMS Companies.................................circuitsassembly.com Mike Buetow 617-327-4702 | mike@pcea.net

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4 PRINTED CIRCUIT DESIGN & FAB / CIRCUITS ASSEMBLY MAY 2022

THE ROUTE

Recent Meetings Revive

Future Possibilities
A
ND WE’RE BACK! stage for replacing drafting in vocational schools,
After a (too long) break, PCEA meetups from which generations of PCB designers matricu-
MIKE have restarted with a bang, with two local lated, with targeted college classes that prepare
BUETOW chapter meetings, plus the first national event in tomorrow’s engineers.
PRESIDENT
PCEA history. Supplementing this is the PCE-EDU program.
Professional development was the focus of both We can’t say enough about this curriculum. There
chapter meetings. This can be looked at two ways: are, at my count, three privately developed curricula
one in terms of technology advancements and the available for PCB design. Only one, however, is both
other tied to learning the basics of placement and current and written by a group of experienced design
routing. professionals. PCE-EDU was developed by Mike
The pandemic is driving change, not just to Creeden, Susy Webb, Rick Hartley, Gary Ferrari and
the way we work, but what we work on. Per John Steph Chavez. That’s more than 180 years of design
Watson of Altium, who spoke at both meetings, engineering experience right there. Creeden, Ferrari
“Advancements in technology are partially a result of and Hartley have chaired IPC standards task groups
the pandemic.” The industry “forced us into redoing for board design and high-speed, and Ferrari was
the way we do things.” coauthor of the original IPC CID program. Among
As reported by PCEA chief content officer Chelsey them, they have trained thousands of design engi-
Drysdale, Watson says designs for IoT, drones and neers worldwide. No one knows more about training
nanotechnology, among others, were “science fic- designers than this group.
tion” just a decade ago. Today, they are common- Launched last year, PCE-EDU has now certified
place, and others (additive manufacturing?) are right 100 designers. Explains Creeden, who also spoke at
behind them. both chapter meetings, “CPCD is crafted to create a
Yet, while today’s designs are typified by higher layout engineer/designer. The curriculum is techni-
frequencies, smaller boards, and bigger, heavier stack- cally up to date. I need to know why I push a button
ups, the industry is losing experience. A survey shared before I know which button to push.” Learn more at
by Watson suggests more than half of designers plan pcea.net/pce-edu-design-engineer-curriculum.
to retire in the next 12 months. Supplementing the chapter meetings, PCB East
While I don’t buy that, there’s no question the proved a successful return to the East coast of the US
profession is in transition. EEs are taking over more after a 13-year absence. More than 600 industry pro-
PCB design responsibilities, but when layout is only fessionals registered for the event. Highlights included
a small component of their overall job, developing Gene Weiner’s keynote, which traversed a host of new
proficiency is challenging. “A lot of EEs don’t want to technologies ranging from laminates to algorithmic
do PCB layout. They think it’s someone else’s respon- engineering, which converts labor-intensive engineer-
sibility,” said Watson. ing processes into algorithms, permitting physical
Let it be said colleges aren’t trade schools. We objects and entire machinery to be designed automati-
could debate the role of higher education for months, cally. He cited Continuous Laser Assisted Deposition
but changing the current model is not going to hap- Technology (CLAD), a nozzle-free laser-jetting tech-
pen overnight, if ever. PCEA, of course, supports the nology said to deposit material of any viscosity. The
efforts of companies like EMA Design Automation, materials that can be jetted range from solder masks
which has partnered with Rochester Institute of and pastes (Types 5 to 7), polyimides, epoxy and sili-
Technology to develop a college course on PCB design cone, Weiner said.
(and has plans to expand that to other universities). Weiner also noted the gains made in additive
Meanwhile, collaborations between community manufacturing. Nano Dimension supplemented that
colleges like Palomar in San Diego and high schools with a special AME Academy presentation, revealing
offer the infrastructure to rebuild the entry-level seg- the vast potential for printed electronics. While not
ment of the profession from the ground up, “start- a panacea, AM gives every engineer the potential for
ing,” as Watson says, “at step one for new designers quick design proof of concept. That alone makes it
with no experience.” Palomar also has two advanced worth further investigation. •
courses for seasoned designers and plans to offer
degree programs. Ultimately, the college plans to scale
its program statewide. mike@pcea.net
These are the types of programs that will set the @mikebuetow

6 PRINTED CIRCUIT DESIGN & FAB / CIRCUITS ASSEMBLY MAY 2022

AROUND THE WORLD

PCDF People Private Equity Firm Acquires Elvia PCB Group

Amazon Lab126 named Faisal NORMANDY, FRANCE – Private equity firm Tikehau Ace Capital has finalized the
Ahmed ECAD application engi- acquisition of 100% of the capital of Elvia PCB Group. Terms were not disclosed.
neer. He has more than 20 years' Alain Dietsch has been appointed CEO of Elvia PCB. He was previously CEO of
experience in PCB design, most
Cobham Electrical and Electronic Equipment.
recently at Cadence.
Bruno Cassin will leave his operational duties to join the supervisory board.
Anirudh Devgan, Ph.D., president and CEO, Elvia PCB had consolidated revenue of €60 million in 2019. The group manufac-
Cadence Design Systems, will be honored
tures PCBs for defense, aeronautics, space, industrial, telecom, automotive and medical.
with the 2021 Phil Kaufman Award for
Distinguished Contributions to Electronic
System Design during a ceremony May 12.
BH to Acquire LG’s In-Car Handset
NXP Semiconductor promoted Dan Beeker
to technical director. He has more than 40 Wireless Charging Business
years’ experience in engineering with Free-
scale and NXP. SEOUL – Printed circuit board fabricator BH said it will acquire LG Electronics’ in-car
handset wireless charging business unit for 136.7 billion won (US$111.5 million),
according to reports. BH will form a new subsidiary called BH EVS, and the acquisi-
PCDF Briefs tion is expected to be completed in August.
NextFlex announced $17 million in funding
BH said demand for in-car handset wireless charging units is some 20 million
for 18 new projects as part of its Project units per year. The firm expects orders worth US$2 billion in the next decade.
Call 6.0 to further promote FHE develop- BH CEO Lee Kyung-hwan will be CEO of BH EVS, and BH will own a 56%
ment and adoption throughout the US stake. DKT, another subsidiary of BH, will own a 44% stake.
advanced manufacturing sector.

Prototron Circuits installed a Maskless

model 5600 LED direct imager. CCL Maker NexFlex Receives Buyout Bids
Yokogawa Electric selected Zuken’s SEOUL – Six investors have submitted bids in a preliminary tender for 100% stake
CR-8000 electronic systems design soft- in NexFlex, according to reports. The sale price is estimated around 700 billion won
ware for all Japanese, Chinese and Korean (US$574 million).
subsidiary locations. NexFlex manufactures flexible copper-clad laminates for smartphone and TV
flex substrates. The firm supplies FCCLs to companies such as Samsung Electronics
and Apple.
CA People The company is currently held by private equity firm SkyLake Equity Partners. A
AIM Solder’s Andres Lozoya has been final candidate was expected to be shortlisted in April.
awarded a Lean Six Sigma Black Belt. Its annual revenue expanded to 150 billion won in 2021 from 69 billion won in 2019.
Apex Tool Group named Rich
Mathews chief marketing offi-
cer. He has over 30 years’ expe- Nano Dimension Opens HQ Near Boston
rience modernizing and grow- WALTHAM, MA – Nano Dimension opened a new US headquarters in the Boston sub-
ing consumer brands.
urbs. The move to Waltham, MA, enables the additive manufacturing OEM to work
ARC Technology Solutions closer to academic and research institutions, early adopters of its solutions for AME,
named Rich Flynn supply chain manager. printed electronics and Micro-AM.
Arch Systems appointed Cameron Sobie, The new headquarters will house expanded sales operations, customer support
Ph.D., senior staff factory data scientist. and fabrication facilities that will be used for customer open houses and continued
Arch Systems also appointed support for AME Academy events and local organizations.
Georg Fuerlinger (left) senior Veteran Gene Weiner has been retained as a consultant through his firm Weiner
account manager. Based in International Associates. In addition, Dana Korf, principal consultant, Korf Consul-
Vienna, Austria, Fuerlinger will tancy, has signed on as Nano Dimension’s new AME standards manager.
work with Arch Systems’ clients
Nano Dimension retains its presence in Sunrise, FL, as a marketing, sales support
and strategic partners through-
out Europe. and NaNoS printing services and logistics center.

Emerald EMS named Uma

Patravali president of the KLA Moves Frontline DfM to Cloud
Bestronics manufacturing divi-
sion. Patravali has a master’s MILPITAS, CA – KLA launched Frontline Cloud Services, a software solution that
in industrial engineering from accelerates design-for-manufacturability analysis and time-to-market for printed
Western Michigan and has circuit boards. The new cloud-based SaaS offering moves DfM analysis to the
worked for GE, Creation Tech-
cloud, which, according to the company, significantly reduces IT bottlenecks and the
nologies and Sanmina.
amount of time needed to run analyses.

8 PRINTED CIRCUIT DESIGN & FAB / CIRCUITS ASSEMBLY MAY 2022

 AROUND THE WORLD

Escatec appointed Ernest Sebak chief

executive officer. Sebak was formerly vice Asserting on-premises DfM analysis can take hours or days, KLA proposes a
president of Jabil’s Global Business Unit. cloud-based solution to tap greater compute power.
He succeeds CEO Patrick Macdonald, who “As a leader in PCB CAM, engineering and Industry 4.0 solutions, our custom-
is stepping down. ers share with us the bottlenecks that slow down their PCB manufacturing process,”
Incap Group appointed Miroslav Michalik said Eran Lazar, general manager, Frontline division, and vice president at KLA. “We
director of operations Slovakia. He will decided to tackle the challenges of DfM analysis by taking advantage of the unlimited
continue as managing director of Incap computational power of the cloud, while keeping the proven application intact. For
Slovakia.
PCB manufacturers eager to make the most of cloud-based efficiencies while main-
Kurtz Ersa hired Ian Orpwood taining exacting security protocols, we continually ensure Frontline Cloud Services
as North American director meets the highest security standards.”
of sales-soldering tools and
Per the company, customers running comparative tests on complex PCBs saw
equipment. Orpwood previ-
ously served as global director Frontline Cloud Services enable up to 90% faster DfM analysis speeds. For example,
of sales at OK International. one customer producing high-density interconnect PCBs saw analysis time shorten to
30 minutes from 75 hours when running the same DfM analysis on premises versus
Libra Industries promoted Matt
Tringhese to vice president of with Frontline Cloud Services. Another customer producing PCBs for miniLED ran a
global operations. Tringhese’s similar test, and analysis time was reduced to 20 minutes from nine hours.
career at Libra Industries
began in 2012 as a second shift
production supervisor. Altium Launches Electronic Design
Sanmina named Shawn Brady
Northeast business develop-
Program for College Students
ment manager. He has more
SAN DIEGO – Altium launched Altium Education, a free online curriculum and cer-
than 35 years’ experience in
EMS sales, most recently with tification program for college and university students interested in engineering and
Virtex. electronics design. This hands-on course takes college students from the basics of
electronics to designing their first printed circuit board.
ViTrox Technologies appointed
Guilherme Pereira as sales and Altium Education is for university and college students studying engineering and
support manager for the Bra- computer science. Designed for virtual, hybrid and physical classrooms, the cur-
zil region. Pereira has more riculum supplements engineering classes, and professors can incorporate it into their
than 15 years’ experience in current lesson plans.
AOI, AXI and ICT in assembly
The program features hands-on lessons focused on schematics, design layout
manufacturing.
and manufacturing. Students will receive guided instruction that culminates in the
completion of their own manufacturable PCB. An educator’s guide is provided for the
course. A free license of Altium Designer ECAD software is included for any student
CA Briefs enrolled in the course.
CGI Americas announced orders for more Upon course completion, students will obtain a certificate signifying they have
than $1.5 million for WOL-7 and WOL-8 successfully completed Altium’s course covering the fundamentals of PCB design.
cleanroom ovens.

ISU Petasys to Construct 4th Fab Shop in

Dynetics selected Benchmark Electronics
to manufacture electronic components for

South Korea
the company’s Enduring Shield mobile
ground-based weapon system.

EVS International appointed as manufac- DAEGU, SOUTH KOREA – Printed circuit board fabricator ISU Petasys plans to spend
turers’ representatives Ark Manufacturing
Solutions in Arizona, New Mexico and
54 billion won (US$44 million) to build a fourth factory here, according to reports.
Southern Nevada, Competitive Edge Solu- The site will manufacture multilayer boards.
tions in the New England US, and Wittco ISU Petasys currently makes boards for Nokia, Cisco, Juniper, Arista and others.
Sales in Southern California. The firm reportedly is looking to add Google to its client list.
LTKM Berhad, a leading chicken egg pro- The company said multilayer board demand is high because of 5G.
ducer, announced a composite proposal
under which the company will divest its
existing business and venture into elec- Simmtech to Open Factory in Penang
tronics manufacturing services.
PENANG – Simmtech Holdings will invest more than S$120 million to establish its first
Pillarhouse appointed Wittco Sales sales large-scale factory in Malaysia to address the global chip shortage, according to reports.
representative in Southern California, Once fully operational, the production facility is expected to employ more than
Southern Nevada and Baja Mexico.
1,000 staff and contribute more than 20% to the company’s global capacity.
Simmtech provides printed circuit boards and packaging substrates for the semi-
conductor industry.

10 PRINTED CIRCUIT DESIGN & FAB / CIRCUITS ASSEMBLY MAY 2022

 AROUND THE WORLD

TTM Breaks Ground at 1st Factory 800 staff, and the location will provide the option for further
in Penang expansion.
Construction is set to begin in October, and the site will be
PENANG, MALAYSIA – TTM Technologies in April broke fully operational by the end of next year.
ground at a new $130 million manufacturing plant here.
TTM’s expansion here is in direct response to customer
requirements for advanced technology PCB supply chain SEMI Wins $1M Grant to Create
resiliency and diversification in regions beyond China, the
firm says. The new plant will serve TTM’s global commercial
Microelectronics Apprenticeship
markets, including networking communications, data center MILPITAS, CA – SEMI, in partnership with Ignited Education,
computing, and medical, industrial, and instrumentation. Foothill College and Krause Center for Innovation, has won
The automated plant will be built on approximately 27 a $1 million California Apprenticeship Initiative New and
acres of industrial land at Penang Science Park. Construction Innovative Grant for the development of a semiconductor
is expected to take 12 to 15 months, followed by equipment pre-apprenticeship and apprenticeship program to expand the
installations in the middle of 2023. Pilot production is targeted pathway to careers in the microelectronics industry.
to begin in the second half of 2023, with volume production The SEMI Foundation and its partners will develop the
commencing in 2024, gradually ramping to full phase 1 capac- industry career training program to be offered by California
ity in 2025. community colleges and ultimately schools in other states. The
TTM expects the new plant to achieve run-rate revenue of program will connect CAI partners with SEMI member com-
approximately $180 million in 2025. The factory has also been panies to define job competencies that shape the coursework.
planned to support a 25% upside phase 2 expansion. The CAI funding will support the SEMI Foundation’s work
to build the SEMI Career and Apprenticeship Network (SCAN)

Katek to Buy SigmaPoint, aimed at helping overcome the US microelectronics industry’s

talent shortage as the federal government continues to invest in
Expand to North America apprenticeships. The grant also supports the foundation’s efforts
to promote a more inclusive workforce. SCAN will offer training
MUNICH – Katek has signed a comprehensive, exclusive term that equips workers with the technical skills needed to enter high-
sheet to acquire Canadian electronics manufacturing services demand, entry-level jobs in the microelectronics industry. It will
provider SigmaPoint Technologies. Financial terms were not also expand the pool of skilled workers for hiring companies.
disclosed. Closing is planned for the end of the second quarter, “Securing the CAI funding is a key step in building out
subject to official approvals. SCAN as we work to develop a national apprenticeship net-
The move expands Katek’s presence to include homeland work, recruit more people of color and women to the industry,
security and defense and strengthens the offering for Katek’s and create industry credentials recognized nationwide,” said
European customers in North America. Shari Liss, executive director, SEMI Foundation. “We look for-
SigmaPoint is one of Canada’s leading EMS providers, ward to continuing the vital work with our partners to expand
with annual sales over $100 million and 280 employees. Its access to jobs across the semiconductor industry and enable
largest customer in North America is one of Katek’s top five more people to enter rewarding careers.”
customers in Europe. Foothill College will develop coursework covering the com-
SigmaPoint CEO Dan Bergeron and the full management petencies for high-need positions in the microelectronics industry.
team will continue to lead SigmaPoint after the acquisition. Complementing the work of Foothill College, Ignited and the
The investment is part of Katek’s strategy of opening addi- Krause Center for Innovation will create middle school founda-
tional markets for high-value electronics. tions and high school pre-apprenticeship programs featuring
Rainer Koppitz, CEO, Katek, said, “As the number three engaging student experiences and teacher-training workshops.
electronics service provider in Europe, we are making good on
the promise to our European customers of a presence on the
VTech Mexico EMS Plant Nears
North American continent.”
Katek also is opening its first Asian plant in Malaysia. Production Readiness
TECATE, MEXICO – VTech’s first EMS facility outside Asia is

Neways to Construct EMS making progress toward establishing production. The pro-
audio focus supports wood and non-wood (semi-EMS) pro-
Factory in Slovakia duction.
The Mexico facility is able to fully leverage the Top 50
NOVA DUBNICA, SLOVAKIA – Neways said it plans to replace its EMS company’s supply chain in China and Malaysia. Its NPI
two electronics manufacturing sites in Slovakia with one new team supports Mexico through all stages from concept to mass
16,000 sq. m. factory, according to reports. The new site will production.
focus on PCB, cable harnesses and cabinet production. VTech acquired the plant in 2021 from QSC, where it
The company says the facility will potentially grow to manufactured wood enclosure loudspeakers.

MAY 2022 PRINTED CIRCUIT DESIGN & FAB / CIRCUITS ASSEMBLY 11

The Evolution of Advanced Technologies & Materials Continue!
MINIATURIZED TECHNOLOGY IS TRENDING | MATERIALS SUITES ARE CHANGING | COMPONENT SETS ARE EVOLVING

EARLY ENGAGEMENT WITH

PCB EXPERTS IS THE SOLUTION
• DFM GUIDANCE • ENGINEERING SUPPORT
• ADVANCED TECHNOLOGY EXPERTISE
The Solution Is APCT
Eliminate The Scramble For Recovery,
Engage Us Early For A Successful Launch

APCT Santa Clara HQ APCT Anaheim APCT Orange County APCT Wallingford APCT Global
408.727.6442 714.921.0860 714.993.0270 203.269.3311 203.284.1215
 APCT CAPABILITIES
TECHNOLOGIES
RIGID
Standard: 2 – 28 Layers
Advanced: 30 – 38 Layers
Development (NPI only): 40+ Layers
HDI; BLIND/BURIED/STACKED VIA
Lam Cycles: Up to 8x
Micro BGA Pitch: .2 Millimeters
FLEX / RIGID-FLEX
Standard Flex: 1 – 6 Layers
Rigid Flex: 4 – 22 Layers
Rigid Flex HDI Lam Cycles: Up to 2x
LEAD TIMES
RIGID
Standard: 20 Days
2 – 10 Layers: 24 Hours
12 - 24 Layers: 48 Hours
HDI; BLIND/BURIED/STACKED VIA
Via in Pad: 72 Hours
HDI : 5 – 15 Days*
* Depending upon # of Lam Cycles
FLEX / RIGID-FLEX
Flex 1 – 6 Layers: 5 – 15 Days
Rigid Flex 4 – 22 Layers: 7 – 15 Days
Rigid Flex HDI 2x Lam Cycles 20+ Days
QUANTITIES
• Prototypes • Mid-Production
• Production Orders - with offshore solutions offered by APCT Global
CERTIFICATIONS
• ISO 9001 Certified • ITAR Registered at all sites
• AS9100D Certified • IPC 6012 Class 3 & 3A
• MIL-PRF-31032 Certified • IPC-6013
(MIL-P-55110 Certified)
• IPC-1791 Trusted Electronics Qualified
• MIL-P-50884 Certified Manufacturers Listing (QML)*
*APCT Anaheim & Orange County Only

APCT Santa Clara HQ APCT Anaheim APCT Orange County APCT Wallingford APCT Global
408.727.6442 714.921.0860 714.993.0270 203.269.3311 203.284.1215
MARKET WATCH EDITED by CHELSEY DRYSDALE

COMPONENTS CREEP UP
Trends in the US electronics % CHANGE
Hot Takes
equipment market (shipments only) DEC. JAN. FEB. YTD%
■ Global semiconductor materials revenue grew 15.9% to
Computers and electronics products 1.2 1.9 1.2 5.9
$64.3 billion in 2021. (SEMI)
Computers -2.1 2.5 3.8 -0.9 ■ Total semiconductor sales will rise 11% in 2022, following
Storage devices 1.9 6.8 2.0 10.8 a 25% increase in 2021 and an 11% increase in 2020. (IC
Other peripheral equipment 7.1 -3.7 6.5 -3.6 Insights)
Nondefense communications equipment -0.3 8.0 0.9 14.3 ■ Worldwide semiconductor revenue totaled $595 billion in
2021, an increase of 26.3% from 2020. (Gartner)
Defense communications equipment 1.3 6.0 -1.6 8.5
■ The worldwide market for augmented reality and virtual
A/V equipment -7.3 34.5 -8.2 50.3
reality (AR/VR) headsets grew 92% year-over-year in 2021,
Components1 0.9 2.8 2.4 14.2 with shipments reaching 11.2 million units. (IDC)
Nondefense search and navigation equipment 0.3 1.0 -1.0 1.7 ■ Global fab equipment spending for frontend facilities is
Defense search and navigation equipment -0.1 0.8 1.2 1.6 expected to jump 18% year-over-year to an all-time high of
Medical, measurement and control 1.9 -0.3 0.8 2.8 $107 billion in 2022. (SEMI)
rRevised.*Preliminary. 1Includes semiconductors. Seasonally adjusted. ■ Spending on compute and storage infrastructure products
Source: U.S. Department of Commerce Census Bureau, Apr. 4, 2022
for cloud infrastructure, including dedicated and shared
environments, increased 13.5% year-over-year in the fourth

PCB Design Software Sales Leap ■

quarter of 2021 to $21.1 billion. (IDC)
The global PC monitor market continued its quarterly
14% YoY in Q4 decline in the fourth quarter, with unit shipments shrinking
5.2% compared to the same quarter in 2020. (IDC)
MILPITAS, CA – Sales of printed circuit board and multichip ■ By 2025, the market share of smartphones supporting Wi-Fi
module design software increased 13.9% to $333.7 million in 6 and 6E is estimated to surpass 80%. (TrendForce)
the period ended Dec. 31, the ESD Alliance announced in April. ■ Worldwide IC unit shipments will increase 9.2% this year to
The four-quarter moving average for PCB and MCM, 427.7 billion units. (IC Insights)
which compares the most recent four quarters to the prior ■ Worldwide sales of semiconductor manufacturing equip-
four, rose 15.1%. ment in 2021 surged 44% year-over-year to an all-time
Overall electronic system design (ESD) revenue increased record of $102.6 billion. (SEMI)
14.4% to $3.47 billion. The four-quarter moving average rose ■ Global shipments of smart home devices grew 11.7% in
15.8%. 2021 to more than 895 million. (IDC)
Companies tracked in the report employed 51,236 people
globally in the quarter, up 5.7% year-over-year and 0.1%
sequentially. US MANUFACTURING INDICES
Computer-aided engineering revenue increased 11.2% NOV. DEC. JAN. FEB. MAR.
to $1.06 billion, IC physical design and verification revenue PMI 61.1 58.8 57.6 58.6 57.1
decreased 2% to $625 million, semiconductor intellectual
New orders 61.5 61.0 57.9 61.7 53.8
property revenue jumped 25% to $1.3 billion, and services
Production 61.5 59.4 57.8 58.5 54.5
revenue increased 43% to $131 million.
The Americas was the largest reporting region by revenue, Inventories 56.8 54.6 53.2 53.6 55.5
up 21% to $1.58 billion. Europe, Middle East and Africa Customer inventories 25.1 31.7 33.0 31.8 34.1
(EMEA) rose 5.5% to $482.5 million, Japan fell 2.4% to $223 Backlogs 61.9 62.8 56.4 65.0 60.0
million, and Asia Pacific rose 14% to $1.19 billion. Source: Institute for Supply Management, Apr. 1, 2022

KEY COMPONENTS
NOV. DEC. JAN. FEB. MAR.
Global Semi Equipment Sales EMS (North America)1 1.43 1.55 1.58 1.52 1.44
Surge 44% in 2021 Semiconductors2 24.5% 28.3% 26.8%r 32.4%p TBD
MILPITAS, CA – Worldwide sales of semiconductor manufac- PCBs3 (North America) 1.10 1.17 1.18 1.16 1.05
turing equipment in 2021 surged 44% year-over-year to an
Computers/electronic products4 5.34 5.32 5.24r 5.17p TBD
all-time record of $102.6 billion, says SEMI.
Sources: 1IPC, 2SIA (3-month moving average growth), 3IPC, 4Census Bureau, ppreliminary, rrevised
China claimed the largest market for semiconductor
equipment for the second time with sales expanding 58% to
$29.6 billion to mark the fourth consecutive year of growth. the third position. Annual semiconductor equipment spending
Korea, the second-largest equipment market, registered a sales increased 23% in Europe and 17% in North America, which
increase of 55% to $25 billion, after showing strong growth continues to recover from a contraction in 2020. Rest of world
in 2020. Taiwan logged 45% growth to $24.9 billion to claim sales jumped 79% in 2021.

14 PRINTED CIRCUIT DESIGN & FAB / CIRCUITS ASSEMBLY MAY 2022

ROI

Here Comes Supply Chain 4.0!

Will it be able to handle unforeseen events better than its predecessor?

MANY ARE EXCITED and working diligently toward with Covid, were too sick to work, or decided to retire
enabling Factory (Industry or Tech) 4.0 to dramatically early to avoid contracting the virus at their workplace.
change their manufacturing and business environment, With everyone hunkered down, travel ground to a halt,
but maybe we should focus instead on Supply Chain further disrupting global transportation and logistics,
4.0, as that may change the manufacturing and busi- compounding the problem. The pandemic sucker-
ness environment more – and not in a good way! punched Supply Chain 3.0, and it is still reeling.
Businesses are currently operating within Sup- A third unforeseen event was war. Wars have taken
ply Chain 3.0. Supply Chain 3.0 has taken decades place during the evolution of Supply Chain 3.0. Most,
to refine into a highly efficient, cost-effective, global however, have been in relatively obscure locations or
supply chain. We know how we got here. Companies between countries whose only strategic export is oil. This
sought lower-cost skilled labor and a cost-friendly time the battles are on the border of Europe and between
operating environment in which to build manufactur- two countries with significant minerals and natural
ing facilities. As manufacturing shifted to these lower- resources, which are – or were – exported globally. With
cost areas, governments invested in infrastructure 90% of the world’s helium exported by one of the coun-
and education to attract ancillary businesses to invest tries and a significant percentage of palladium from the
there as well. Shipping and logistics improved thanks other, the impact on our industry in particular could be
to the advent of containerships, larger aircraft, better dramatic. A lack of helium negatively affects the already
roads and rail, and countries opening their borders to stressed chip manufacturing sector. Palladium shortages
trade. The result was a global supply chain in which will further drive up the cost of some surface finishes
components and parts are made almost everywhere used in electronics. The war is affecting scores of items.
and transported “just in time” to assembly sites, before Equally, air and sea transportation have been impacted
finished products are shipped to customers. with no-fly zones in place. “Risk” of a cascading effect
As impressive is how product development now on other materials, minerals and resources used in the
occurs globally with teams from different countries col- global supply chain is real. As recently as six months ago,
laborating 24/7 to develop the next great product. This most could not have predicted such an event taking place
efficient, cost-effective collaboration is again made pos- so close to Western Europe. Once again, an unforeseen
sible thanks to the development and refinement of com- event is challenging the robustness of Supply Chain 3.0.
munication. Supply Chain 3.0 is robust – a winner for all Which brings us to Supply Chain 4.0. What will it
companies and countries involved. After decades making look like? While many believe recent events mark the
Supply Chain 3.0 nearly perfect, what could go wrong? end of a global supply chain undoing, something so
As it turns out, a lot. complex and bedded in so much infrastructure most
It started with tariffs. Government economic saber likely will not happen, at least not anytime soon. Rath-
rattling in the form of tariffs levied on certain goods er, Supply Chain 4.0 may be a much more bloated,
incented manufacturers to reallocate resources to much less efficient, and less cost-effective version of
reduce the financial impact. A single tariff levied on Supply Chain 3.0.
a single item, in a single place, ricochets across the "Just in time" parts distribution may now be a thing
globe, negatively impacting the entire supply chain. of the past. Expect increased inventories and expense at
No one saw these coming. Tariffs were viewed as all levels. Geographic investment in factories will shift.
highly improbable in the contemporary world, where All players regardless of nationality will likely diversify
PETER BIGELOW
is president and
all economies are connected through a global supply and build facilities, probably smaller ones, in a variety
CEO of IMI Inc.; chain. Supply Chain 3.0 suddenly caused considerable of countries to hedge geopolitical and logistics risk. All
pbigelow@imipcb. stress, especially on logistics and transportation. this will take time, especially as all involved will look
com. His column The next unforeseen event was a pandemic. Covid at “risk” very differently in a world with less global
appears monthly. put a tremendous burden on all aspects of society. economic dependency. We are entering a period when
Daily disruptions have been roiling global economies supply-chain disruptions will be more the norm than
for over two years. The result has been component and not, and prudent businesspeople will be forced to add
product shortages. Some of these shortages have been cost and time within supply-chain calculations.
local. Others have impacted entire industries. Some So, as we deal with unforeseen events of the past
governments have resorted to shutting down entire half-decade, we’ll have to adapt to a “new” supply
cities, leaving manufacturing facilities idle. Working chain. Hopefully the next one will be more efficient for
remotely became the norm. Too many were infected a world filled with unanticipated events. •

16 PRINTED CIRCUIT DESIGN & FAB / CIRCUITS ASSEMBLY MAY 2022

 BOARD BUYING

In PCB Procurement, Negotiate All Over

Review pricing with current and outside suppliers to confirm you are paying
the going rate.

“We don’t have the bandwidth to move business.”

Business doesn’t always have to be moved to get
THAT'S WHAT A printed circuit board buyer told me better pricing, however. The PCB is usually eight to
recently. 12% of the BoM, and any savings found can either
Let’s unpack that because it could be a short- add to your bottom line or be passed on to the OEM
sighted attitude. customer, making it less tempting for them to move
When an EMS firm puts a PCB supplier on its business away from your company.
AVL, it often asks only for pricing on new projects. As a custom-made item, the printed circuit board’s
When it comes to existing work, the response is often, price is somewhat subjective, depending on technology
“We don’t move boards once they are placed,” or, “we required, volume needed, speed of delivery and loca-
don’t have time to rebid those,” or, “it takes too much tion of manufacture.
effort to move to another vendor.” PCB buyers should always review pricing with
Even in the face of rising board costs, many buyers present suppliers and go outside the company AVL
and procurement managers resist moving production to confirm what they’ve been paying is in line with
away from suppliers they’ve used for years. the going rate, especially on jobs that have been with
What about your company? Do the people respon- the same vendor for a long time. With good industry
sible for overseeing your supply chain and ensuring the knowledge, they’ll be able to negotiate intelligently.
most cost-effective operation make buying decisions EMS management should encourage buyers to make
based on lack of “bandwidth?” time to actively quote other qualified sources.
If so, it’s business malpractice. Are your board buyers leveraging their annual
Because when that is the prevailing mindset, the PCB spend, or are they being leveraged by a current
PCB supplier is aware of it. They know your board vendor?
buyer doesn’t want to upset the apple cart, and they It is not hard to explore the PCB market. For
will take advantage of that. OEM and EMS companies additional PCB supplier leads, buyers need to attend
that invest too much of their annual PCB spend with industry trade shows, read trade magazines, search
only one vendor are making a costly mistake. LinkedIn or ask their favorite component rep about
I understand a buyer’s concern for good quality good suppliers.
and consistent delivery, but you can get that from more Once that information is accumulated, get an
than one fabricator. And then it comes down to price. NDA and ask for several quotes. If the quotes are
Complacency will cost you money. When EMS firms competitive, ask for and follow up on references. If
focus only on winning new business, they are putting all looks well, then get your quality and production
their existing business at risk. departments involved by following your corporate
Many EMS companies are not being proactive to procedure for a new vendor addition. GREG
protect their existing assembly business from jumping At the same time, let your existing vendor base PAPANDREW
to a competitor, especially when it comes to the cost know you are looking elsewhere, even if the reason has more than 25
of the bare board. Although the common wisdom only has to do with price and not performance. At a years’ experience
is, once won, assembly programs will stay in place, minimum, this exercise will keep your vendors on their selling PCBs
in fact, over the last year several OEMs have asked toes when it comes to price, delivery and quality. directly for various
fabricators and
me to suggest new homes for their assembly work. Supplier diversification is vital to your success.
as founder of a
OEMs are taking a hard look at their assembly costs to Don’t get complacent with your PCB purchasing
leading distributor.
remain competitive and maintain profit margins. PCB practice. You may regret it. •
He is cofounder of
materials, metals and freight pricing are skyrocketing. Better Board Buying
It is good business to look at reducing costs wherever (boardbuying.com);
possible, especially on existing orders. It can be done greg@directpcb.com.
successfully without sacrificing quality.
And it’s not an excuse to say board buyers are
overwhelmed with responsibilities. Keeping the vendor
base on its toes is a core responsibility. More impor-
tant, it’s the job of upper management to ensure board
buyers regularly seek offers from other vendors to
compare with the prices they’re getting.

MAY 2022 PRINTED CIRCUIT DESIGN & FAB / CIRCUITS ASSEMBLY 17

DESIGNER'S NOTEBOOK

Selecting the Appropriate Through-Via Technology

for a PCB Project
Component manufacturers continue to seek breakthroughs, adding functions
and reducing size, while fan-out is left to the designer.
WHILE THE PRINTED circuit board is composed of Component manufacturers continually outdo
sheets of dielectric and conductor layers, it’s the vias themselves, adding functions while reducing size. The
that really bring a circuit to life and keep it going. end game is a “marketing breakthrough,” where the
Permitting signals to pass from one layer to another company can compare its chipset to the others and
makes this a 3-D puzzle that can scale to a staggering claim to take up the least amount of PCB real estate.
number of layers. While that claim may be technically true, the part
You don’t have to go back many decades to find where the fan-out is left to the designer is the unspoken
a time when we called them printed wiring boards. cost of chip-scale packaging.
(Officially, the standards still do.) Components were
mounted to what looked like a pegboard: rows of The standard plated through-hole via. The plated
evenly spaced holes where the leads of the part extend- through-hole via still has a long runway. On plenty of
ed through two or more of the holes. You just added devices, the pitch of the pins supports through vias in
wire. As far as routing consistency, every board was a the go-to size of 8-mil drill with 18-mil capture pads
one-off, built up one wire at a time. on all layers. This is the usual size for Class 2 commer-
Give credit to government agencies for driving cial applications and permits up to 90° of the drilled/
PCB technology toward higher reliability. Along the plated hole to break out from the 18-mil pad. Thicker
way, the “industrial complex” responded with the fol- boards want larger holes, as the fabricator doesn’t
lowing electronics innovations: want to deal with plating high aspect ratio holes. The
■ Individual transistors advanced to integrated cir- common 0.062" board thickness is in the sweet spot.
cuits using dual-inline package technology. (I will continue using mils for drill/pad sizes and
■ Axial- and radial-leaded passive through-hole com- metric units for device pitches. The two systems are
ponents gave way to surface mount types with and blended in the real world, where there are CAM
without leads. operators and SI/PI people who use mils, and they
JOHN BURKHERT ■ Quad flat packages (QFP) and similar devices came set the rules. Meanwhile, the chipmakers have settled
JR. is a career PCB along with a full perimeter of signal pins, plus a into decreasing the pin pitch from one rounded metric
designer experienced ground slug taking the central area inside the single number to another. I could call it 127µm or 5 mils.
in military, telecom,
ring of pins. The point is to be comfortable with the common units
consumer hardware
■ Ball grid array (BGA) packages now featured a par- of measure.)
and, lately, the
tial or full field of pins. Now, where was I?
automotive industry.
Originally, he was
Each of these general categories describe a water-
an RF specialist but shed advancement in device packaging as we went Class 3 design rules for high reliability. On the
is compelled to flip from one transistor to billions of them. The PCB high-reliability side, we still use the 8-mil drill but with
the bit now and then industry responded by transitioning to multiple layers a 23-mil pad on the outer layer and 21-mil innerlayer.
to fill the need for of etch, which protected the more vulnerable circuits These numbers are intended to ensure a minimum
high-speed digital and permitted higher circuit density. 2-mil annular ring of metal around the hole on every
design. He enjoys layer. This must account for layer-to-
playing bass and layer registration, along with hole loca-
racing bikes when
tion and size tolerance.
he's not writing
The vias described above are use-
about or performing
ful for routing DIP and QFP packages,
PCB layout. His
column is produced
along with the roomy BGA devices
by Cadence Design where the pin pitch equals or exceeds
Systems and runs 0.8mm. Be careful about managing
monthly. the vias in the thermal pad that makes
up the heart of the QFN/QFP package
types. You might get away with adding
a few regular vias between the paste
stencil openings.
When the device is consuming a
FIGURE 1. A typical mix of components found on a board that features considerable amount of current, more
through-hole vias. vias must be placed in the thermal pad.

18 PRINTED CIRCUIT DESIGN & FAB / CIRCUITS ASSEMBLY MAY 2022

 DESIGNER'S NOTEBOOK

The vias may be filled with a nonconductive material and You need to use the 1mm- or 1.27mm-pitch devices to pull
capped with metal plating so solder cannot migrate down the off a high-reliability (Class 3) fan-out. The number of layers
holes. Last, a conductive fill with little globs of copper mixed required grows quickly as each via blocks the routing channel
with strands of silver in an epoxy base is the plan for drawing on every layer. We’re lucky if we get two traces between the
out some serious heat. vias. Necking down traces to fit the geometry may not sit well
with those signal integrity folks.
Case study: Thermally conductive fill. The end of a fiberop-
tic cable has a transponder that converts light waves from the Rounding out the plated through-hole via discussion.
glass into electrical waves for copper and also generates the Thankfully, some FPGA and ASIC vendors still deal in pack-
light waves going the other direction using a laser. These photo ages that can be used with a 10- to 12-layer board with
detectors and lasers get very warm as the units strobe along at through-hole technology. Back-drilling may be required for the
10 to 400Gb per second. thicker boards. Extra thin traces and spaces may be required in
In one case, the mechanical engineer thought they had especially dense areas to allow the signals to escape from the
an answer that used a slot in the board and a pedestal in the inner part of the BGA devices.
housing to pass through the board and contact the bottom of In cases where the vias are incorporated with a heat-sink
the device. The engineer didn’t want to believe the PCB could pin, plugging and capping prevents solder migration, while
not have a +/-1-mil thickness tolerance. It was a 1mm board, vias filled with thermally conductive material can dissipate a
so the standard tolerance was +/-4 mils. That didn’t help the lot of energy.
engineer’s pedestal plan, but it’s always good when
the fabricator confirms your statements.
They tried everything: thermal pad, grease and
different heat sinks. Only one configuration had
a measurable difference: the one where I changed
the ground holes in the center pad from 10 mils
to 13 and had them filled with the expensive two-
step thermal epoxy fill. The measurable difference
was it met the spec, and we could ship products
to Cisco.

General-purpose PCBs continue to use plated

through-hole vias. Plated through-hole vias are
sufficient to fan out BGA packages with lower pin-
count and generous pin-to-pin spacing of 0.8mm
or more. It may be possible to use PTH vias on FIGURE 3. Opening up the solder mask for the vias provides a convenient
a 0.65mm-pitch BGA, although it uses a 16-mil method of attaching a jumper wire.
capture pad. It is likely you will hear from the
fabricator if you go this way, even if the finished
hole size is decreased to 6 mils. A row of large vias can be placed along the edge of a board
and cut off right down the middle for what’s called
a castellated via. The ground net or even various
signals can wrap around the edge or a slot some-
where within the board using castellated vias.
Other than components targeted for mobile
applications, many possibilities exist to build
a PCB using through-hole technology. Power
consumption may be higher while edge rates are
lower than their miniaturized counterparts. Some
of these more robust parts may only be available
in the high-temperature version.
If these things aren’t concerning, then perhaps
basic PCB technology can be used for simpler proj-
ects in a way that extends the expected lifespan.
You have to hope they keep on building those
FIGURE 2. A fan-out scheme for the FPGA shown in Figure 1. components. •

MAY 2022 PRINTED CIRCUIT DESIGN & FAB / CIRCUITS ASSEMBLY 18

Printed Circuit Engineering Professional
Table of Contents:

Chapter 1: Professional Overview Chapter 5: Flex Printed Circuits (FPC)

1.1 Printed Circuit Engineering Layout Overview – 5.1 Flex and Rigid-Flex Technology – Overview and
Profession overview Introductions to FPC
1.2 Basic Fabrication of a Printed Circuit Board – 5.2 Flexible Printed Circuit Types – IPC definition
Materials and construction 5.3 Flexible Circuits Applications – Industry sectors and
1.3 Basic Assembly of a Printed Circuit Board – usage
Materials and process 5.4 Materials for Flexible Circuits – Properties and
1.4 Basic Electronics in a PCB – Fundamental process
understanding and concepts 5.5 Design Start Considerations – Physical and electrical
1.5 Basic Printed Circuit Engineering Layout 5.6 FPC Stackup Constructions – Usage and process
Overview – Layout process 5.7 Flex Design Practices – Physical and electrical
1.6 Project Management (PM) – Enabling project aspects
success and accountability 5.8 Production Process Consideration – Process flow
1.7 Communication –throughout the process 5.9 Conductive Surface Finishes – Overview of types and
process
Chapter 2: Circuit Definition & Capture 5.10 Stiffeners – Types and applications
2.1 Libraries to Bill of Material (BOM) – Integrated 5.11 Shielding Material – EMI and EMC considerations
library: symbols, land patterns 5.12 Design for Manufacturability and Assembly – Unique
2.2 Surface Mount and Thru-Hole Technology – concerns building FPC
Components and process
2.3 Schematic Types and Conventions– Functional, Chapter 6: Documentation & Manufacturing Preparation
logic, flat and hierarchal 6.1 Documentation Overview – Prepare for the final
2.4 Schematic Symbol Placement – Orderly circuits design effort
improve comprehension 6.2 Resequencing Reference Designators – Back-
2.5 Schematic Review – Complete and accurate annotation
2.6 Circuit Board Types – Rigid, Flex and Printed 6.3 Silkscreen – Providing visual intelligence
Electronics 6.4 Industry Standards – Design, document and build
2.7 IPC – MIL Standards and Specifications – compliance
Reference listing of standards 6.5 Post-processing Procedure – Know what to expect at
2.8 Verification, Testing, Compliance & Qual. your company
Assurance 6.6 Manufacturing Deliverables – Documentation
2.9 Mechanical Board Information –Physical 6.7 Fabrication Drawing – Instructions to fabricate the
requirements bare board
2.10 Database Links and Iterative Data Exchange – 6.8 Assembly Drawing – Reference drawing used to
Development iterations assemble the PCA
6.9 Schematic Database and Drawing – Circuit capture
Chapter 3: Board Layout Data & Placement and BOM origin
3.1 Board Parameters Set-up – CAD – environment 6.10 Bill of Materials (BOM) – Controlling document
3.2 Stackup Design – Z-Axis relationship 6.11 Final Deliverables – Formats and creation process
3.3 Constraints and Rules – Define and implement 6.12 Transfer to Manufacturer – Manufacturing interface
accurate reliability
3.4 Placement for Assembly – Performance and Chapter 7: Advanced Electronics, EM Applications
buildability (During the review class only cursory coverage of Chapter 7
3.5 Placement of Components – Solvability, will be provided due to the advanced nature of this
performance, and manufacturing content.)
3.6 Schematic Driven Placement – Cross-probing 7.1 Energy Movement in Circuits –EM Theory
3.7 Placement Dense Digital Circuits – (LSI) Large 7.2 Critical Frequencies in Circuits on PC Boards
Scale Integration Frequency and Rise Time (Tr)
3.8 Placement Power Delivery – Source, distribution, 7.3 Transmission Lines in PC Boards – Relational nature
and usage in electronics
3.9 Placement Mixed Circuit (RF/HSD) – Together 7.4 Understanding Impedance of Transmission Lines –
3.10 Placement Review Milestone – Approval for routing Modification from layout
7.5 Impedance Control of Transmission Lines –
Chapter 4: Circuit Routing & Interconnection Controlling impedance in layout
4.1 General Overview of Routing – Fundamental 7.6 Controlling Impedance of Digital ICs – Controlled and
parameters set to specific values
4.2 Routing Dense Digital Circuits – Modular approach 7.7 Controlling Noise Margin – Critical lengths
4.3 Routing with Signal Integrity Applications – understanding
Managing energy fields 7.8 Crosstalk and Cross-coupling – Capacitive and
4.4 Routing Power Delivery – Source, Distribution, and inductive coupling
Usage 7.9 Controlling Timing of High-speed Lines – Timing
4.5 Routing RF Circuits – Managing dissipation and matched, not length
loss
4.6 Routing Review Milestone – Approval of routing
MATERIAL GAINS

Build Back Better – and Smarter

As the pandemic becomes endemic, restoring order to the world’s prices and
supply chains will take time and won’t be easy.

AS WE ALL adjust to the reality that Covid and its fulfill orders for new cars. Major manufacturers are
derivatives are here to stay, communities around the producing fewer vehicles and prioritizing their most
world are beginning to rebuild economically: returning in-demand models because they cannot source all the
to work, reviving businesses where possible and mak- electronic components needed.
ing new plans if not. On the other hand, pressures such as increasing
It is no surprise materials, inventory and shipping fuel prices, legislation on emissions, and the prospects
are in short supply and are often stuck in the wrong for restrictions on new combustion-engine vehicles
places. In some cases, services that companies used to should buoy demand for the latest most efficient
rely on are no longer available because the suppliers vehicles. And, while customers wait, demand for used
have gone out of business. Workforces are depleted, cars is increasing, driving market prices upward.
and some knowhow, skills and experience have been In the longer-term, semiconductor makers are
lost. Rebuilding is not as straightforward as opening working to increase capacity to service the demand.
the factory doors, picking up the tools that were put However, that takes time, and semiconductor demand
down at the beginning of 2020 and getting on with it. will continue to grow as the leading markets reach
Even now governments are still mandating measures government-imposed deadlines outlawing sales of
such as the sudden full lockdown of Shanghai, which combustion-engine vehicles.
has severely impacted road and air transport. We must Some of the worldwide supply problems resulting
still expect the unexpected! from the pandemic are short-term issues. As accept-
There certainly is the opportunity to build back able prices are negotiated (or alternative solutions are
better, but let’s not be simplistic. The world we built imagined and enacted), output resumes, and shipping
was highly sophisticated and interconnected – an returns to more normal routines, problems will subside;
ecosystem of ecosystems. It won’t be easy. It will take inflationary pressure should ease, and availability of
time. New leaders and innovators need to acquire the goods and services should improve. Other changes to
skills required to replace those we’ve lost. And we have the established order are here to stay, some part of the
other challenges too, like protecting the environment new post-pandemic reality and others due to strengthen-
and transitioning to more sustainable ways of living. ing environmental protection, including an emphasis on
As if that wasn’t enough, further new tensions are add- carbon offsetting and the switch to green energy.
ing to the pressure on resources and, as a result, prices. I’ve commented on the dynamics of supply-chain
As we work to restore order, established supply management before, and there is an even clearer justifi-
chains remain disrupted or broken. Even without cation and more urgent demand for closer collaboration
material shortages, the shortage of transportation between suppliers and customers to ensure the greatest
creates the same effect. Companies are struggling to possible efficiency. Sharing production plans enables
arrange the supplies they need to fulfill orders received partners to guarantee materials arrive in the right places
from their own customers. The disruption is transmit- at the right time. While “too little, too late” is as disas-
ted through the entire chain, changing the balance of trous as always, “too much, too soon” is a luxury that,
supply and demand. in the current economic climate, adds to costs consider-
The effect on the automotive industry is a highly ably. Saving these costs through better plan and data
visible case. It affects everyone making, selling and sharing is one of the many changes we need to make
ALUN MORGAN
buying cars. Over the past three decades or so, the as we adjust to the situation we find ourselves in. It is
is technology
electrification of mobility has provided many growth worth remembering the highest cost a manufacturer
ambassador at
Ventec International
opportunities for our industry and has delivered can experience is that of having no materials to process.
Group (ventec-group. increasingly efficient and intelligent vehicles that are It will be difficult to definitively declare the pan-
com); alun.morgan@ more satisfying to drive, safer, more comfortable and demic “over.” That may be best left to the World Health
ventec-europe.com. more economical. The electrification of the drivetrain Organization. We cannot beat Covid. It’s in the world,
is the ultimate stage of evolution when passenger cars and we must live with it, but we can be encouraged we
become, in essence, consumer electronic products. are finding ways to do this, and, as we restart economic
Today’s latest models are full of chips controlling activities, we can only be bullish, adopt the spirit of
everything from mirror dimming and mood lighting “build back better,” and strive to realize the cleaner
to internet connectivity, high-voltage battery manage- world we want to inhabit, make use of the experiences
ment and autonomous driving. Except they are not. we have gained and continue to work to make all our
Supply shortages mean carmakers are struggling to lives healthier, more secure, safer and happier. •

22 PRINTED CIRCUIT DESIGN & FAB / CIRCUITS ASSEMBLY MAY 2022

 This Indium Corporation webinar series addresses a range
of topics beneficial to anyone with technical involvement or
interest in electric vehicles and the automotive industry.

Technical Webinars
Voiding Mechanisms & Solutions For High-Density
Automotive Electronics – Presented by Dave Sbiroli
(May 11th)

Building More Reliable Assemblies for Higher Mission Profiles

– Presented by Karthik Vijay (June 28th)

Design Considerations for Board Layout & Material Selection

– Co-presented by Jonas Sjoberg and Ângelo Marques
(September 21st)

Best Practices For SMT Assembly & Root Cause Analysis

– Presented by Dave Sbiroli (October 12th)

JOIN our discussion!

Powered by:

indium.com/CAREL
SIGNAL INTEGRITY

Bandwidth for MODELING AND

MEASURING PCB Interconnects
Numerical analysis of defects in single bit and single
symbol response. by YURIY SHLEPNEV, PH.D.

Modeling and measuring digital serial interconnects is usually High-Speed Serial Data Signals
done in the frequency domain. That means the minimal and A digital signal in a serial link is a sequence of bits transmitted
maximal frequencies (or bandwidth) should be defined before through the PCB or packaging interconnects as a sequence of
analysis or measurement begins. The data rate and rise time pulses modulated by amplitude. The digital interconnect mod-
define the signal bandwidth, and the usual practice is to define eling problem is actually the analog problem of modeling the
the maximal frequency as either the inverse of the rise/fall propagation of pulses in the time domain.
time (or fraction of it) or as a multiple of the fundamental or Most often a simple two-level pulse amplitude modulation
Nyquist frequency.1 Such a simple bandwidth definition may (PAM2) is used. A lower voltage level corresponds to 0 and
work for some structures, but it may fail for others. Ultimately, a higher level to 1. Also, because the pulse amplitude does
an SI engineer must make the decision for a particular signal not return to zero, PAM2 is often called non-return-to-zero
type and interconnect structure.1 (NRZ). To transmit data with a speed of 6Gbps with NRZ
Here we introduce a simple, practical way to identify the or PAM2 modulation, one bit time is 166.6667ps. In space,
bandwidth with a numerical analysis of defects in a single it spreads over about 2.5cm (about 1") in PCB type dielectric
bit (SBR) or single symbol response (SSR). It begins with a (Dk=4).
brief introduction into structure and spectrum for 6Gbps and Four-level pulse amplitude modulation (PAM4) is becom-
112Gbps signals. Then, it proceeds with analysis of defects in ing more popular as the data rates increase, and the required
SBR and SSR introduced by the bandwidth deficiency for two link bandwidth for PAM4 is smaller.2 It uses four voltage
practical cases. The bandwidth is defined by a model with an levels to encode sequences of two bits: 00, 01, 10 and 11 (also
acceptable level of defects in either SBR or SSR. called symbols). To transmit 112Gbps or 56GBd (GigaBaud)

FIGURE 1. PCB and packaging interconnect scale in bits for 6Gbps NRZ signal (top) and in symbols for 112Gbps
PAM4 signal (bottom).

24 PRINTED CIRCUIT DESIGN & FAB / CIRCUITS ASSEMBLY MAY 2022

SIGNAL INTEGRITY

Spectra and Bandwidth of High-Speed

with PAM4 modulation, one symbol time is 17.8571ps. In a Data Signals
PCB dielectric with Dk=4, one symbol spreads in space over
2.677mm (about 105 mil). To understand the scale of PCB and Let’s look closer at the power spectral density (PSD) of 6Gbps
packaging interconnects, we can use the number of bits for NRZ signal with 50ps rise time for a pseudo-random bit
PAM2 or symbols for PAM4 signal spreading over the length stream PRBS7 (computed with Simbeor SDK) (FIGURE 2).
of the ideal link in the space domain (FIGURE 1). The signal in the frequency domain is a superposition of
The ruler in Figure 1 provides a scale in centimeters. A harmonics with rapidly decreasing magnitudes. Starting from
slowdown factor of two is used for the illustration of the spa- about 5GHz, harmonic amplitudes are below -18dB. The con-
tial spread in a typical PCB dielectric with Dk=4. We can see tribution of such harmonics cannot be ignored. The spectrum
at 6Gbps NRZ only a couple bits are simultaneously in the has a minimum at 1/Tbit (the time for one bit or the unit inter-
packaging part of interconnects (about 5cm or 2"), and about val) of 6GHz, but rises up to -18dB again.
10 bits are in the PCB part (about 25cm or 10") at the same The minimum bandwidth of a link to pass such a signal
time. is defined by the
With the data Nyquist frequency
rate increased (0.5/Tbit or 3GHz
to 112Gbps and in this case).3 As
PAM4 modula- demonstrated,1
tion used, we can accurate models
observe about 20 or measurements
symbols (40 bits must include the
for NRZ) over the harmonics above
package section of the fundamental or
interconnects and Nyquist frequency.
about 100 symbols Otherwise, the
(200 bits for NRZ) observed or com-
in the PCB inter- puted signal in the
connects. The illus- time domain would
tration in Figure 1 be significantly
is for the ideal link, FIGURE 2. A fragment of 6Gbps NRZ signal in time domain (left plot) and in fre- distorted. This is
one without any quency domain as the power spectral density in dB vs. frequency (right plot). because the power
kind of signal deg- in the signal har-
radation. In real monics above the
interconnects, the Nyquist frequency
signals degrade. is significant, and it
The degradation will define the sig-
can be predicted nal shape or distor-
with modeling or tion if not properly
analysis or mea- accounted for.
sured with scopes Notice most
or vector network of the spectrum
analyzers (VNAs). above the Nyquist
Mathemati- frequency is in the
cally, it is easier to microwave band.
model the digital So, what should
FIGURE 3. The insertion loss of the sample link (left). The power spectral density
signal degradation the bandwidth for
(PSD) of the incident signal shown in blue (stimulus). The PSD of the transmitted
in the frequency signal (response) shown in red (middle). The eye diagram (overlap of the pulses) the modeling or
domain, assuming shows the degradation of the ideal trapezoidal pulses (right). measurement for
the time domain such signals be?
signal is a superpo- Where should you
sition of harmonics. (Harmonics are sinusoidal signals in time stop the frequency sweep? Should it be 0.5/Trise or 1/Trise? At
domain.) At this point, the analog problem in the time domain this point, we do not have enough data to answer that.
becomes the problem of harmonics in the frequency domain. The real signal does not have a linear rise time as used
The first question is always what is the bandwidth of the for the spectrum evaluation above. It is not generated like
signal in the frequency domain, and over what bandwidth that, and even at the chip IO level, the lossy and dispersive
should we have to model or measure it? To answer this ques- interconnects smooth or filter the signal. The package may be
tion, we investigate what we would lose by neglecting the very destructive too. So, for illustrative purposes, let’s look at
harmonics above the maximal bandwidth frequency. the spectrum of the same signal after it passes through 50cm

26 PRINTED CIRCUIT DESIGN & FAB / CIRCUITS ASSEMBLY MAY 2022

 SIGNAL INTEGRITY

(about 20") of PCB stripline interconnect. The insertion loss up to 500GHz with Simbeor SDK (FIGURE 4).
of such a link is shown on the left graph in FIGURE 3, and cor- If the upper frequency estimate, 1/Trise, looked reason-
responding response spectrum is shown in the middle graph able in the case of 6Gbps (relatively easy to make models and
below (40GHz bandwidth). measurements), it is completely unrealistic here. The Nyquist
Figure 3 shows the rise time increases, and there is deter- frequency = 0.5/Tsymb; it is 28GHz in this case. The analysis
ministic (predictable) jitter due to the dispersion. (It is not or measurement up to this frequency will be highly insufficient,
jitter, but it is usually called that.) From the PSD plot, we can as most of the signal power above this frequency will be unac-
see considerable attenuation of the high-frequency harmonics. counted for. Notice the signal spectrum above the Nyquist
If the analysis must be done only for the transmission through frequency is in the mm-wave band (over 30GHz).
the interconnect, it can be done with high accuracy over the Fortunately, the spectrum changes dramatically when the
same or smaller bandwidth. Although, to define the bandwidth PRBS signal shown in Figure 4 on the left passes through
we need to quantify the errors introduced by the bandwidth 25cm (about 10") stripline interconnect, as shown in FIGURE
deficiency. As shown next, this can be done with the analysis 5 (500GHz bandwidth).
of single-bit response. It is rather unfortunate. If you look at the eye diagram on
The important point from this example is an interconnect the right, this is how a 112Gbps PAM4 looks when it passes
reduces the magnitude of the signal high-frequency harmon- through the 25cm of stripline on a typically designed PCB. It
ics for better or worse, and it should be accounted for in the does not look good and requires additional signal conditioning
bandwidth identification. to restore it.
So, what is the bandwidth for a 112Gbps PAM4 signal?
PAM4 Signal Analysis Should it be a multiple of Nyquist or fraction of the inverse
Next, let’s look at the spectrum of a 112Gbps PAM4 signal. rise time? We still need to evaluate the consequences of the
The TX, with 4ps rise time – a little optimistic – is computed bandwidth restriction. Technically, we must evaluate the time
domain signal distortion introduced by the
spectrum harmonics above the bandwidth
maximal frequency for a particular inter-
connect structure. As shown next, this can
be done with the single-symbol response.

Complications to the Spectral

Analysis of Ultra-High-Speed Sig-
nals
Here is what we have learned so far:
The signal source spectrum (computed or
measured) should define the bandwidth
required for modeling or measurements,
considering the expected channel insertion
loss, including all kinds of losses: absorp-
FIGURE 4. A fragment of 112Gbps PAM4 signal in time domain (left plot) and in
tion, reflections and leaks. The signal
frequency domain as the power spectral density in dB vs. frequency (right plot).
degradation reduces the
power in high-frequen-
cy harmonics and may
reduce the required band-
width as well. Though,
such signal degradation
and possible bandwidth
reduction is unfortunate
because it may degrade
the signal up to the point
of a complete link failure.
One more thing con-
tributes to the bandwidth.
We have not discussed
possible coupling or cross-
talk. The model band-
FIGURE 5. The insertion loss of the sample link (left). The power spectral density (PSD) of the inci-
dent signal shown in blue (stimulus). The PSD of the transmitted signal (response) shown in red width must be adjusted to
(middle). The eye diagram (overlap of the pulses) shows the degradation of the ideal trapezoidal account for the spectrum
pulses (right). of the coupled signals that

MAY 2022 PRINTED CIRCUIT DESIGN & FAB / CIRCUITS ASSEMBLY 27

SIGNAL INTEGRITY

are not attenuated much at the near side (near-end crosstalk or shown on the right of Figure 6. For the bandwidth 3GHz, the
NEXT, for instance). delay in RCM corresponds to the signal frontal delay at 3GHz.
However, as we can see from the red curve on the right plot,
Single Bit Response Numerical Experiments the model delay is smaller than expected, and we can still see
There is a universal way to estimate the bandwidth with the oscillations caused by the high-frequency harmonics. Even
numerical experiments. First, compute the single bit response if we somehow adjust the delay exactly to the value of the SBR
(SBR) of a 6Gbps NRZ signal passing through a 50cm stripline delay, that will not save the day. The harmonics above 3GHz
link. We use a 40GHz bandwidth as the benchmark and artifi- will distort the SBR in some way. One possibility to avoid it is
cially restrict the modeling bandwidth to 3, 6 and 12 GHz and to predict the signal attenuation above 3GHz. It may work for
compare the SBRs (FIGURE 6). a simple transmission line segment, but it will not work for a
The left plot in Figure 6 shows SBRs computed in Simbeor link with discontinuities, as discussed in the next example. So,
software with rational compact model (RCM) without the the answer for the bandwidth evaluated with the model with
delay extraction. The RCMs are causal, but they approximate the delay is still about 12GHz. Further increase of the band-
the original transmission parameter with high accuracy only width does not significantly change the SBR.
up to the bandwidth maximal frequency (BW number on the Will it work for another type of interconnect? Unfortu-
plots above). The RCM does not delay or attenuate the signal nately, no. The numerical experiment should be repeated. Also,
harmonics above that frequency. The high-frequency harmon- the result of such a numerical experiment will depend on the
ics appear as non-causal oscillations on the SBR. (Response software used to compute the SBR. It is important to validate
comes before the expected time.) If we restrict the bandwidth the software first. Capabilities of a particular software can
to the Nyquist frequency 3GHz, the SBR will show noncausal- be evaluated with a similar numerical experiment. Compute
ity with peak-to-peak voltage noise of about 40mV. That is SBR for a set of models with different bandwidths to see if the
over 10% of the benchmark SBR magnitude, computed with response converges with the increase of bandwidth. If software
the sufficient bandwidth 40GHz. That value may be consid- uses DFFT, increase the number of frequency samples to see
ered as the error measure due to the insufficient bandwidth. if the SBR converges when the number of samples increases.
In fact, the insufficient bandwidth usually shows up in time Also, compare the result to SBR computed with a different
domain as oscillations or other defects caused by a mishan- tool.
dling of the high-frequency harmonics. With the extension
of the bandwidth up to 6GHz (1/Tbit), the error is reduced Single Symbol Response Numerical Experiments
to 7mV, or about 2%, and the error is negligible with the Single symbol responses (SSR) for the 112Gbps PAM4 signal
bandwidth 12GHz. That is what the model or measurement discussed earlier and computed from S-parameters (left) mea-
bandwidth should be for this case, ideally. sured for a 5cm (about 2") link are shown in FIGURE 7.
Obviously, one can reduce the noncausality by the delay In this case, a 67GHz bandwidth is considered sufficient
extraction procedure. If the RCM is built with the frontal delay for SSR computation and used as the benchmark. It does not
extraction, the error due to insufficient bandwidth drops, as produce significant error (no visible noncausality in the SSR).

FIGURE 6. Single bit response (SBR) of a 50cm stripline link for the 6Gbps signal computed with different model band-
widths (BW) without the delay extraction (left plots) and with the delay extraction (right plots). dV is the error in SBR
caused by the bandwidth deficiency.

28 PRINTED CIRCUIT DESIGN & FAB / CIRCUITS ASSEMBLY MAY 2022

 6949: 2
F1
IAT

01
6
CE

RT
N

I F I C AT I
O
SIGNAL INTEGRITY

FIGURE 7. Magnitude and phase delay of transmission parameter of a 5cm stripline link (left). Single symbol responses (SSR) of
the link computed with two different bandwidths (BW) and with and without the delay extraction. dV is the error in SSR caused by
the bandwidth deficiency (middle). Eye diagrams computed with two different bandwidths (BW) and with and without the delay
extraction (right).

That means the power in the high-frequency harmonics above REFERENCES

67GHz is not significant for this structure. If the bandwidth 1. C.R. Paul, “Bandwidth of Digital Waveforms,” EMC Society Newsletter,
is reduced to 30GHz (a little over the Nyquist frequency), the #223, 2009.
error is about 40mV out of 420mV, or about 10%, for the 2. R. Stephens, “PAM4: For Better or Worse – Is PAM4 Worth the Hassle,”
SI Journal, Feb. 26, 2019.
model constructed with RCM and no delay extraction, and
3. H. Nyquist, “Certain Topics in Telegraph Transmission Theory,” Transac-
about 20mV (about 5%) with the frontal delay extraction. tions of the American Institute of Electrical Engineers, vol. 47, no. 2,
The SSR pulse magnitude is closer to the expected mag- April 1928.
nitude with the delay extraction, but it is a coincidence. The
rest of the SSR is different from the benchmark case. The stub
YURIY SHLEPNEV is president and founder of Simberian
effect appears on all three SSRs because the stub degrades not (simberian.com), where he develops Simbeor electromagnetic
only the frequencies around the resonance at about 55GHz, signal integrity software. He has a master’s in radio
but also at the lower frequencies (visible as oscillations of the engineering from Novosibirsk State Technical University and a
insertion loss on the left plot). The stub is a capacitive discon- Ph.D. in computational electromagnetics from Siberian State
tinuity at the frequencies below the first resonance. Though, University of Telecommunications and Informatics. He was the
the stub effect looks smaller on the SSR with the insufficient principal developer of electromagnetic simulator for Eagleware
bandwidth. and a leading developer of electromagnetic software for the
The eye diagrams for all three cases may look similar. simulation of signal and power distribution networks at Mentor
(They are shown on the right of Figure 7, with the eye mea- Graphics. His research has been published in multiple papers
and conference proceedings; shlepnev@siberian.com.
surements computed with a Simbeor eye analyzer tool.) The
eye diagram may not be suitable for a bandwidth-deficiency
evaluation. We cannot reduce the bandwidth below 67GHz
for this structure. Most likely, we have to increase the band-
width for interconnects with smaller reflections (no stubs) and
a smaller insertion loss. A numerical experiment should be the
next step for a more definite answer.
Numerical experiments are important when deciding the
bandwidth for PCB or packaging interconnect modeling and
measurements. By building models with an excessive band-
width, which requires only realistic transmission line models,
and observing the effect of the bandwidth reduction on the
simulated response, we can identify the minimum bandwidth
for the system investigation before the signal is excessively
distorted. •

30 PRINTED CIRCUIT DESIGN & FAB / CIRCUITS ASSEMBLY MAY 2022

RF DESIGN

EMBEDDED RESISTOR Copper Foil

for mmWave Applications
Embedded passives are being deployed for commercial
market applications. by THOMAS SLEASMAN

Recent advancements in mobile technologies have exponen- counts, maximum surface area for components, the lowest
tially increased demand for radio spectrum bandwidth. The possible insertion loss and system-acceptable attenuation
rush of equipment for more RF applications is being deployed characteristics.
across the world, with 5G and millimeter wave (mmWave) As 5G and mmWave communication are leveraged by
communications expanding into the commercial space to take the commercial marketplace, system architects and designers
advantage of the wider bandwidth, higher data rates and low envision thousands of flat-panel AESAs discreetly mounted
latency that these frequency bands offer. Cellular 5G and 6G, across the landscape. As frequency rises, so do the limits of the
low Earth orbit (LEO), mid Earth orbit (MEO), geosynchro- RF waves to travel through space, objects and variable envi-
nous communications networks, interconnected devices (inter- ronmental conditions. As a result, more antennas, repeaters
net of things), autonomous driving vehicles, defense and envi- and base stations are necessary to mitigate signal attenuation,
ronmental monitoring are all driving these needs. The antenna coupled with lower power and shorter propagation distances
and sensors necessary to manage the signals for these applica- at these short wavelength frequencies.
tions are similarly changing, becoming more sophisticated. One antenna technology design option is using thin-film
To ensure high-data-rate wireless connectivity, the broad- copper foil technology incorporating embedded passive mate-
band high-gain antennas necessary to manage high-frequency rials. Embedded passives can be slimmed-down SMT compo-
but lower-power signals are increasingly moving from dish nents built and mounted into the inner copper and dielectric
and horn to flat-panel active electronically steered antennas layers of the PWB laminate substrates. Embedding components
(AESA) for beam forming and massive MIMO designs. In allows designers to create smaller PCB/package sizes with bet-
response, the RF industry has developed new integrated cir- ter signal integrity and gain increased board surface space
cuits, materials, processes and equipment to build devices to for active component mounting because of a more efficient
manage these mission-critical sensor applications. wiring design. While components and mounting technologies
Much of the development and understanding of how to are evolving to meet the challenges of discrete devices within
engineer and build reliable and accurate transmit-and-receive PWBs, embedding thin-film-based resistors etched and formed
sensors for today’s environment were derived from phased array within the copper foil traces leverages decades of effectiveness
antennas and Ka/Ku-band radar engineering typically used in and robustness, no additional component buying and stocking,
defense applications. The AESA products being developed can no extra handling and placement of components, elimination
shape azimuth, elevation and antenna pattern as desired to gen- of wire bonding or solder processes within the depths of the
erate beams that target specific communications devices. PCB during the processes of multilayer build, and no cavity
Embedded resistor copper foils have a long history of or added space requirements and potential component waste
applications in military/defense antenna systems and remain should the subsequent multilayer laminations go awry. Embed-
well positioned to support the design and manufacture of the ded thin-film resistors further enhance reliability of PWBs in
flat-panel, PCB-based AESA antennas necessary to handle this part due to the aggressive sealing measures employed during
expanded antenna paradigm. the PCB’s lamination processes.
As AESA technologies used in the defense and space sec- Thin-film embedded resistors address many of the needs
tors are deployed for commercial applications, designers who of SMT passive resistors, while providing additional value that
may not have broad experience in implementing systems with can be factored into the overall completed PCB cost model.
this technology are faced with a must-have list of printed wir- Given the PCB layers must have copper routing lines and
ing board concerns, including tighter routing, higher layer spaces to move signals to and from active components, the

32 PRINTED CIRCUIT DESIGN & FAB / CIRCUITS ASSEMBLY MAY 2022

 RF DESIGN

resistor materials residing beneath those traces, while not free, where N is the ratio of length to width or number of squares
are already in place to be used to lower PCB costs. (N = L/W).
Due to the thin nature of embedded resistors (200- For a given sheet resistivity:
10000Å, 0.02-1.0µm), the resistors can be buried in innerlay- ■ Resistance of a square area equals the bulk sheet resistivity
ers of printed circuit boards without increasing the overall of the material.
thickness of the board. To do so, they employ internal cavities ■ One square of 25Ω/□ material will equal 25Ω regardless of
or occupy surface space for discrete SMT resistors (FIGURE 1). the size of the square.
These resistor networks become part of the etched and printed ■ To create different resistor values with a given sheet resistiv-
circuitry on the standard PCB layers, thereby eliminating the ity, adjust the length-to-width ratio or number of squares.
need for passive SMT resistors and the many solder con- • For example, to create a 50Ω resistor using Rs of 25Ω/□
nections, bonding issues material, adjust the length to twice the width:
and routing vias servic-
ing those components.
Resistor foils are alter-
natives to traditional
termination and pullup/
down SMT resistors
and widely utilized for
balancing resistors in
Wilkinson power divid-
ers. By removing discrete FIGURE 2. Resistance value is established in part by
FIGURE 1. Embedded passives resistor geometry.
SMTs from PCBs, inter-
can be placed in cavities and
become part of the circuitry. connecting traces and
vias claim less room, so
engineers can add other
functions and reduce the PCB size for smaller, higher frequency
applications and systems. EQ. 3.
Millimeter and higher frequencies mean smaller and more
tightly routed microstrip and stripline circuit designs and
reliance on stable Dk and Df high-frequency PCB dielectrics, Resistors can be patterned as bar type using multiple
smoother, thinner copper foils, and other advanced technolo- squares and further arranged in a serpentine type of multiple
gies to limit signal degradation. Thin-film embedded resistive squares. They can also be designed circular or form an arc.
material technology offers a solution for many high-speed,
low-loss, high-frequency applications where absolute perfor-
mance and reliability are essential.

Designing with Embedded Resistors

A
Among the myriad design decisions that must be made – func-
tion, size, interconnection with other boards, laminate materials,
thermal issues and components used – designers need to decide if
they intend to use buried resistors at the frontend of the process.
B
The basic design concept for embedded resistors can be
seen in the following equation:

EQ. 1.
where Rs is the sheet resistance of the resistor material desig-
nated as ohms per square (OPS).
The resistance value can be determined by material resistance
and geometry of the resistor according to the formula above.

FIGURE 3. Resistor patterns include a bar type with one (3a) or

EQ. 2. more squares (3b), as well as a serpentine pattern (3c).

MAY 2022 PRINTED CIRCUIT DESIGN & FAB / CIRCUITS ASSEMBLY 33

RF DESIGN

Embedded resistor suppliers provide design tools in which come in a range of standard resistor options from 10 to 1000Ω
the engineer can select resistance, power handling and toler- per square bulk sheet resistance.
ance to suggest the appropriate resistor dimensions.
Power dissipation, temperature rise and laminate substrate
used all have an effect of the working life and long-term sta-
bility of the resistor. In general, the larger the resistor area the
better, especially in designs where power and reliability are
critical.
Manufacturing embedded resistors with resistive copper
foil involves two print/image and develop steps and two or
three etch steps, depending on the resistor alloys being used.
Standard resistor alloys are nickel chromium (NiCr), nickel
phosphor (NiP), silicon (Si), aluminum (NCAS) and chromium
silicon monoxide (CrSiO). Considerations include the equip- FIGURE 5. Processes for defining resis-
ment setup for the photoresist application and subsequent tor elements. (Source: Ticer Technolo-
exposure and development, as well as process control for selec- gies and Coretec)
tive copper removal to define resistor length. These processes
can impact individual resistor tolerances. The inclusion of
the resistive foil layer between the substrate and copper layer As signal speed increases, so does the skin effect causing
and the print and etch process steps result in resistors having the electrical energy to move nearer to the surface of the cop-
customized ohmic values embedded inside PCBs after the PCB per traces in a PCB. At these higher speeds, roughness profiles
lamination process. and etching quality of embedded resistor foils are critical to
The OPS sheet resistance for sputtered and plated cop- achieve the best possible insertion loss characteristics. Fur-
per foils in roll form are controlled to a plus or minus 5% thermore, line, space and etched microwave structures like
coefficient of variance value. The manufacturing process is Wilkinson power dividers must become smaller to manage the
calibrated using precise measurement and SPC guidelines. The wavelengths.
roll-to-roll sputter and/or plated manufacturing produce a The final resistance tolerance is a function of delivered
thin, continuous, conformal resistor alloy coating that mirrors tolerance, the relative movement up and down in value dur-
the profile of the matte side of the copper foil. Trace width, ing dielectric lamination (annealing effect) and the precision
conductor spacing and etch rates are predictable to maintain of the copper and resistive material etch processes of the PCB
consistency with most modeling and design software. This fabricator. Precise etching process controls repeatedly produce
eliminates the need for excessive iterative engineering to move resistors with good tolerance.
from design to realized products.
Thermal Dissipation Factors
All aspects of the system’s thermal dissipation must be consid-
ered in the PCB design. Factors that affect thermal dissipation
in the system are circuit configuration; circuit thickness and
material type; thermal conductivity of the dielectric; proximity
of power or ground planes to resistors; ambient temperature;
additional system cooling or heat sinking; and resistor size
(total resistor area).
All electronic systems need to consider cost. This is par-
ticularly important as technologies developed for defense
applications are adopted for commercial applications. Under-
FIGURE 4. The resistor in the ground standing the total system cost drives designers to consider
plane requires an isolation area options, including embedded passives. Designers need to con-
between the ground plane and the
sider tradeoffs, such as using thin-film embedded resistor foils
resistor. (Source: Ticer Technologies)
to place most or all of the resistor networks on a layer or two
inside the board in place of SMT components. They need to
decide if reserving more surface real estate, simplified packag-
Embedded resistor foil products are available in roll form ing and improved signal integrity by using embedded resistor
and customer-specified sheet sizes. Foils are produced at a 51" foils would lower the overall cost of the system vs. standard
or 40" width cross-web standard, and production rolls are SMT devices. •
hundreds of LF in the down-web direction. This allows users
to work with various combinations of dielectric laminate cores THOMAS SLEASMAN is manager, sales and marketing, at
or PCB innerlayer layup processes. This flexibility allows users Ticer Technologies (ticertechnologies.com); tsleasman@
to scale to their preferred and most economical unit size. Foils ticertechnologies.com.

34 PRINTED CIRCUIT DESIGN & FAB / CIRCUITS ASSEMBLY MAY 2022

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 TEST BOARDS

Revamping the SMTA

MINIATURIZATION TEST VEHICLE
Rev. 3.0 will incorporate user input. What should be on the
next layout? by CHRYS SHEA

The current SMTA Miniaturization Test Vehicle was released to the board? That’s up to the SMTA community. What do
in 2018 and is projected to have an effective lifespan of three to users want on the next layout? Here are some ideas we’ve
five years. Its design has served the SMT community well – and received so far:
will continue to do so with an updated layout, bill of materials ■ More pad and aperture sizes for 01005s; built-in DoEs.
(BoM) and associated programming and analysis files slated ■ More pad and aperture sizes for 008004s; mask-define
for release in late 2022. some 008004s and build in DoEs.
The board is used for standard tests, such as solder paste ■ D-paks for voiding tests.
selection, wipe frequency and pad or aperture design, which ■ 0.4mm TSSOPs.
will remain the same in the new revision, albeit with some ■ More BTCs of different sizes; thermal vias in center pads.
components removed and others added. FIGURES 1 AND 2 ■ Stagger BGA layouts to mitigate “leading-edge effect.”
show the top and bottom sides of the board with the footprints ■ More 0.3 BGA pad configurations.
that will be removed outlined in orange, and ones that may be ■ Rotational placements at various angles.
removed outlined in blue: ■ LED footprints.
■ The 1206 and 0603 components will be completely elimi- ■ Areas to dispense and measure adhesives or other additive
nated, opening up several square inches of real estate on the materials.
populated side of the board. ■ Cu pillar flip chips.
■ The QFN layout will avoid copper pads on the opposite side Should the 0402s stay or go? What about the wet bridge
to make x-ray analysis easier. test patterns? I’m asking for user input through the month of
■ The SIR coupon will be removed, thereby eliminating the May, and layout efforts will begin this summer. SMTA Rev
need for the gold fingers on the short edge of the board, 3.0 is planned to make its debut Oct. 31 - Nov. 3 at SMTA
which in turn will eliminate the notch that requires machine International 2022 in Minneapolis.
board stop adjustments for the unpopulated side. It will also Have some ideas? Email me at chrys@sheaengineering.
free up about 6 sq. in. of real estate for print or reflow tests. com. I look forward to hearing from you. •
■ At least one set of the fine resolution spread tests will be
removed, freeing up even more space on the unpopulated side. CHRYS SHEA is president at Shea Engineering Services
With all the newly available real estate, what will we add (sheaengineering.com); chrys@sheaengineering.com.

FIGURE 1. SMTA Miniaturization Test Vehicle populated side. FIGURE 2. SMTA Miniaturization Test Vehicle unpopulated side.

36 PRINTED CIRCUIT DESIGN & FAB / CIRCUITS ASSEMBLY MAY 2022

 DECONTAMINATION

The Risks of Electronic Hardware Exposure

to DISINFECTANTS

Case studies show cleaning the workplace can harm materials

and equipment. by TERRY MUNSON and PHIL ISAACS

During the pandemic, cleaning and disinfecting common areas environments where people are exposed to other people.
and surfaces to protect and remove the Covid-19 virus and Wearing masks and isolating proved effective at reduc-
all other viruses and bacteria has become urgent. During this ing the spread, but there’s another side to disinfecting the
time manufacturers have turned to professional cleaning ser- areas where people work, live and play to allow the store,
vices or have assigned facilities departments the responsibility diner, office and manufacturing centers to return to normal
of properly disinfecting areas. Adding corrosive chemicals to operations. Many professional services offer disinfecting and
the working environment is a new condition. While the CDC cleaning for virus reduction, and they are easy to find and
issued guidelines for human exposure and documented the schedule (FIGURE 1). It is an important health and safety issue
timing and conditions when workers can return to a work area that all areas are cleaned and disinfected – all common spaces
after fogging, spraying and disinfecting, it missed the under- and working surfaces that put people at risk for exposure to
standing and risk of contamination the virus, but the risks should be
these corrosive chemicals can cause understood.
to exposed electronic hardware, Those who professionally disin-
components, material in produc- fect areas wear protective clothing
tion and production equipment. and respirators designed to elimi-
Below are case studies showing nate the risk of exposure, and they
the chemical effects and residue disinfect when people are not pres-
patterns negatively impacting hard- ent. Again, they are following the
ware and operating conditions. chemical/equipment manufacturing
As the pandemic altered our requirements for broadcasting dis-
world, we learned and isolated in infectants, many of which are cor-
ways we never expected. As the FIGURE 1. Aerosolized disinfecting surface treat- rosive chemicals.
SARS-CoV-2 virus spread, manu- ment of workstation. There are sprayers, foggers,
facturing facilities closed world- application spray bottles and wipes
wide to help slow the spread of for surfaces. Each method permits
the disease. Scientists and engineers deposition and volatilization of
sought methods to safely reopen chemicals over time. Most disin-
factories, prioritizing the effective- fectant applications are not applied
ness of disinfecting methods for the directly on electronic hardware, but
health and safety of the employ- because of the complexity of these
ees. Possible reliability impacts to operating electronic systems, they
electronic products and equipment may have draw-fans pulling air
were typically not of highest con- across the system to cool opera-
sideration. The initial unknown tional components (FIGURE 2). This
nature of the virus, its mode of air intake path allows airborne
spread, and length of time it lives contaminants to be deposited on
on surfaces resulted in a need to electronics.
apply disinfecting agents to the FIGURE 2. CFD airflow and heating of PC controller. When electronics manufactur-

MAY 2022 PRINTED CIRCUIT DESIGN & FAB / CIRCUITS ASSEMBLY 37

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 DECONTAMINATION

ing facilities are fogged to cover large areas where electronic hardware is being
produced, these pre-functional systems are exposed, and these surface residues are
deposited and sit on surfaces until the units are powered up in the field (FIGURE 3).
The effects of these residues pose a great risk of parasitic leakage, electrochemical
migration (shorting) and corrosion issues.
When fogging large production areas and office locations, airborne disinfectants
not only travel to the general locations but are drawn into the HVAC air handling
systems, redepositing this contamination throughout the system. (Air filters will cap-
ture the initial microdroplets, but as they dry the chemicals outgas and are delivered
to working areas as gases onto electronics.) Even when hardware is tented or covered
during fogging, the risk of contamination to hardware and systems grows every time
FIGURE 3. Aerosolized disinfecting sur- the area is disinfected (FIGURE 4).
faces. The lack of specific control over
the fog ... Case Study #1: Field Failures
In the first case study, medical areas
with tented equipment in surgical suites
fogged with disinfectant to remove
bacterial, viral and biological contami-
nation created a sterile environment for
patient and staff protection (FIGURES
5, 6 AND 7). The use of an aerosolized
disinfectant is an effective, fast method
of applying the disinfectant (typically
a corrosive residue) to large areas,
but each professional person is well
protected by personal protective equip-
ment (PPE).
In this case, we show data on equip-
FIGURE 4. ... means surface residues are ment in the tented suites in standby
deposited randomly ...
and ready-for-use states. The electronic
equipment was tented with surgical
draping cloths and was not exposed
directly to the disinfectant fog (station-
ary units to fog the entire room), which
ran for 15 minutes, then was allowed to
FIGURE 7. Ultra-low-volume fogging sit for 15 minutes before people could
machine.1 reenter the room. The functional prob-

FIGURE 5. ... and sit until the units are

powered up.

FIGURE 8. PCBA 1: four fogging cycles, exposure on the bottom side of the
PCBA.

FIGURE 6. Ultra-low- FIGURE 9. PCBA 1: two fogging cycles, exposure on the bottom side of the
volume fogging. PCBA.

MAY 2022 PRINTED CIRCUIT DESIGN & FAB / CIRCUITS ASSEMBLY 39

 DECONTAMINATION

lems in this case appeared after one or two fogging exposures Upon review of the localized extraction results and electri-
created by the moisture-laden disinfectant floating throughout cal test, new hardware exhibited acceptable residue levels and
the space. good, “clean” C3 results. The two field samples with different
Exposed hardware from the surgical suite – 30 days in the exposure (fogging) cycles experienced catastrophic failures and
field with four exposures and two exposures of fogging – was were returned for failure analysis. (These are real field applica-
compared to current production samples (FIGURES 8 AND 9). tions, not experiments.) The resulting failed hardware in the
Hardware failed in a critical respiratory control system (TABLE 1). field led to corrosion due to external contamination caused by
the exposure from fogging with an aerosolized
disinfectant.

Case Study #2: ICT Failures

Hardware in production and engineering
areas was exposed to fogging. The samples
experienced ICT and functional testing fail-
ures two to five days after fogging the
production area (FIGURES 12, 13 AND 14).
Each of the areas was inside a 50,000 sq. ft.
production facility and selected in relation to
the main aisle fogging areas.
Inspection of the areas showed no visible
signs of fluid on the floors and rack surfaces,
but small droplets appeared on box surfaces
three days after fogging. The ESD plastic
FIGURE 10. PCBA 1: four fogging cycles, disinfectant exposure on the bottom trays and tops of components showed tiny
side of the PCBA with cooling fans showing high chlorine residues from debris dry spots on the surfaces that were open,
on top of resistors (not from process residue) (no-clean = WOA)).
but not on the samples below the top layer.
The residues of the disinfectant chemically
matched the residues on the trays and top
layer of the PCBA surfaces (TABLE 2). These
residues are corrosive and moisture-absorb-
ing after they dry.

Case Study #3: RF Product

Corrosivity
For high-reliability and RF products, even
small amounts of parasitic leakage can cause
a change in impedance of the circuit, causing
undesirable results. Exposure of the work
area to fogging while the PCBAs were a
work-in-progress prior to potting in silicone
for ruggedization caused long-term imped-
FIGURE 11. PCBA 1: two fogging cycles, disinfectant exposure on the bottom side
of the PCBA with cooling fans showing high chlorine residues from debris on top ance changes in the circuit that were only
of resistors (not from process residue) (no-clean = WOA)). brought about through temperature cycling
in end-use after several months.
Board inspection showed no visible resi-
dues from the fogging, and resistivity of sol-
vent extract (ROSE) testing at a full board
level showed an acceptable amount of ionic
contamination as a result of the large surface
area being measured. The contamination
was at a level in which the corrosivity was
not enough to be detrimental to the PCBA
in the short term. Therefore, the issue was
not caught during ICT or functional testing.
Although tenting WIP trays was done
FIGURE 12. Hardware FIGURE 13. ... experi- FIGURE 14. ... up to at the manufacturing site, only the top and
exposed to fogging ... enced failures at test ... five days later. most of the sides were covered, leaving some

40 PRINTED CIRCUIT DESIGN & FAB / CIRCUITS ASSEMBLY MAY 2022

 DECONTAMINATION

TABLE 1. Ion Chromatography – Case Study #1

Ion Chromatography (Dionex ICS 3000 at Foresite) n/a = not applicable C3 Tester

Sample Description Fluoride Acetate Formate Chloride Nitrite Bromide Nitrate Phosphate Sulfate WOA MSA Lithium Sodium Ammonium Potassium Magnesium Calcium Results Time (Sec)
Foresite Recommended Limits
1 3 3 6 3 6 3 3 3 25 1 3 3 3 3 n/a n/a Clean >120
for PCBA (No-Clean - SMT)
ID PCBA from Production, Not in the Field

1 Area 1 Microprocessor Leads 0 0.52 0 0.45 0 0.34 0.05 0 0.98 18.65 0 0 1.51 0 0 0 0 Clean 180

2 Area 2 Capacitor SMT 0 0.35 0 0.69 0 0.54 0.03 0 1.34 15.36 0 0 1.69 0 0 0 0 Clean 180

3 Area 3 Open Solder Mask area 0 0.11 0 0.54 0 4.65 1.74 0 0.32 1.05 0 0 1.36 1.63 0 0 0 Clean 180

4 Area 4 DIMM Memory Module 0 0.29 0 1.25 0 3.88 1.24 0 0.24 12.33 0 0 1.41 2.26 0 0 0 Clean 180

PCBA #1 from Field 30 Days (exposed to 4 fogging cycles)

5 Area 1 Microprocessor Leads 0 15.24 0 28.98 0 8.65 12.34 0 21.31 15.65 0 0 11.58 14.24 0 0 0 Dirty 1

6 Area 2 Capacitor SMT 0 9.24 0 91.24 0 9.65 10.25 0 41.25 14.24 0 0 17.10 16.69 0 0 0 Dirty 1

7 Area 3 Open Solder Mask Area 0 10.27 0 15.64 0 1.24 5.68 0 9.54 0.52 0 0 11.58 21.24 0 0 0 Dirty 1

8 Area 4 DIMM Memory Module 0 16.35 0 21.41 0 6.35 9.98 0 15.66 10.14 0 0 17.10 18.92 0 0 0 Dirty 1

PCBA #2 from Field 30 Days (exposed to 2 fogging cycles)

9 Area 1 Microprocessor Leads 0 8.54 0 13.65 0 4.65 4.62 0 12.35 12.35 0 0 7.98 8.54 0 0 0 Dirty 1

10 Area 2 Capacitor SMT 0 6.98 0 41.21 0 3.88 3.21 0 24.68 9.98 0 0 13.32 14.68 0 0 0 Dirty 1

11 Area 3 Open Solder Mask Area 0 8.57 0 8.22 0 4.65 2.69 0 5.10 0.44 0 0 10.21 12.24 0 0 0 Dirty 1

12 Area 4 DIMM Memory Module 0 6.44 0 11.72 0 3.88 3.21 0 7.17 10.65 0 0 9.98 13.36 0 0 0 Dirty 1
Liquid Disinfectant Dried
13 0 121.41 0 231.54 0 0.22 11.24 0 148.54 10.65 0 0 81.35 101.27 0 0 0 Dirty 1
on Foil for Shipping
All Values in ug/in2

units much more exposed and prone

to future failure compared with other
units processed at the same time.
The photos show the cart tops were
tented, but ESD work surfaces were
not, creating a transfer point. Dis-
infectants do not negatively impact
ESD but are easily transferred with
direct board contact to the ESD mats
or tools.
Samples tested by localized (site- FIGURE 15. Areas not covered for fogging.
specific) extraction showed poor, FIGURE 16. Workbenches not covered,
“dirty” C3 performance, and three and open racks exposed on lower
samples from a cycle within three days of fogging showed the same chemical shelves.
signature as the disinfectant that was fogged. The samples with high levels of
contamination were field return samples, while the others were from different
stages of new build production.

Case Study #4: Design of Experiment

Since disinfecting near or around electronics has become a common periodic
event to prevent normal workers from virus exposure, it is time to understand
the environmental effect on electronic performance caused by these methods of
disinfecting. This case study analyzes the deleterious effects of common chemicals
used on and near electronic systems when delivered with ultra-low-volume (ULV)
fogging systems. The analysis includes surface insulation resistance (SIR) of test
boards with four test locations per board with no-clean flux residue on the assem-
bly and local ionics testing the mobility of the ions present.
Chemicals for fogging included hypochlorite; hydrogen peroxide; IPA; ben- FIGURE 17. SIR test board, pre-test.

MAY 2022 PRINTED CIRCUIT DESIGN & FAB / CIRCUITS ASSEMBLY 41

 DECONTAMINATION

zalkonium chloride 13%; thymol oil (botanical disinfectant and fungi-

cide); control (not exposed).

Findings. The samples exposed to fogging with a draw-fan permitted

residues from the disinfectant to create deposits on the surface of the test
coupons, which failed SIR testing for the hypochlorite, hydrogen perox-
ide, benzalkonium
chloride and thymol
oil. All disinfectants
were diluted with
tap water, which is
the recommended
FIGURE 18. SIR test board in draw box.
dilution material
for the ULV foggers.
The IPA and control
with no exposure
both showed good,
passing SIR results.
When this location
was assessed by
localized extraction
and tested by ion
chromatography, it
showed corrosive
effects as well on the
FIGURE 20. PCBAs 1 (top left); 2 (top right); 3 four chemicals that
(middle left); 4 (middle right); 5 (bottom left); 6
(bottom right).
failed SIR. The resi-
FIGURE 19. SIR test board with ULV fogger.

TABLE 2. Ion Chromatography – Case Study #2

Ion Chromatography (Dionex ICS 3000 at Foresite) n/a = not applicable Localized Test

Sample Description Fluoride Acetate Formate Chloride Nitrite Bromide Nitrate Phosphate Sulfate WOA MSA Lithium Sodium Ammonium Potassium Magnesium Calcium Results Time (Sec)
Foresite Recommended Limits
1 3 3 6 3 6 3 3 3 25 1 3 3 3 3 n/a n/a Clean >120
for PCBA (No-Clean - SMT)
ID Hardware Inside a Box Sealed
Area 1 Outside of Box
1 8.65 12.54 0 125.88 0 0 13.28 0 104.24 0 0 0 241.19 0 0 0 0 Dirty 1
on Plastic Label
2 Area 2 Inside Box on ESD Bag 0 0.15 0 2.34 0 0 0.41 0 1.55 0 0 0 2.71 0 0 0 0 Clean 180
Area 3 Inside Box
3 0 2.14 0 1.71 0 1.54 0.16 0 2.41 12.39 0 0 1.04 0.35 0 0 0 Clean 180
on PCBA Capacitor SMT
Area 4 Inside Box
4 0 1.87 0 1.46 0 1.27 0.22 0 1.97 10.41 0 0 1.71 0.27 0 0 0 Clean 180
on PCBA #2 Capacitor SMT
Hardware on Production Rack 3 Days after Fogging

5 Area 1 Empty Tray 10.21 21.35 0 74.21 0 2.14 10.88 0 26.98 0 0 0 184.65 0 0 0 0 Dirty 1

6 PCBA #1 Capacitor SMT 15.24 18.64 0 82.14 0 1.81 11.24 0 31.24 10.24 0 0 163.25 0.65 0 0 0 Dirty 1

7 PCBA #2 Capacitor SMT 19.65 21.41 0 74.61 0 1.24 10.21 0 29.11 12.15 0 0 174.24 0.36 0 0 0 Dirty 1

8 PCBA #3 Capacitor SMT 12.35 14.24 0 63.26 0 1.07 8.55 0 24.65 9.98 0 0 144.27 0.31 0 0 0 Dirty 1

9 Area 2 Empty Tray 3.65 5.24 0 21.35 0 0 3.29 0 10.24 0 0 0 64.25 0 0 0 0 Dirty 1

10 Area 3 Empty Tray 7.19 8.51 0 41.78 0 0 3.21 0 16.88 0 0 0 101.24 0 0 0 0 Dirty 1
PCBA #4 in Tray Area 3
11 9.74 9.74 0 63.54 0 1.25 7.94 0 10.27 12.32 0 0 94.65 0 0 0 0 Dirty 1
Capacitor SMT
PCBA #5 in Tray Area 3
12 8.81 6.44 0 54.21 0 1.11 8.11 0 12.04 15.34 0 0 102.41 0 0 0 0 Dirty 1
Capacitor SMT
Liquid Disinfectant Dried
13 121.41 85.65 0 541.57 0 0 121.65 0 265.54 0 0 0 1184.30 0 0 0 0 Dirty 1
on Foil for Shipping
All Values in ug/in2

42 PRINTED CIRCUIT DESIGN & FAB / CIRCUITS ASSEMBLY MAY 2022

 DECONTAMINATION

TABLE 3. Ion Chromatography – Case Study #3

Ion Chromatography (Dionex ICS 3000 at Foresite) n/a = not applicable C3 Tester

Sample Description Fluoride Acetate Formate Chloride Nitrite Bromide Nitrate Phosphate Sulfate WOA MSA Lithium Sodium Ammonium Potassium Magnesium Calcium Results Time (Sec)
Foresite Recommended Limits
3 2.5 2.5 2 2.5 2.5 2.5 2.5 3 n/a 0.5 2 2 2.5 2 n/a n/a Clean >120
for Bare Boards
Foresite Recommended Limits
1 3 3 6 3 6 3 3 3 25 1 3 3 3 3 n/a n/a Clean >120
for PCBA (Clean)
Foresite Recommended Limits
1 3 3 3 3 6 3 3 3 150 1 3 3 3 3 n/a n/a Clean >120
for PCBA (No Clean)
ID

1 Vial C5038 0 0 0 0.12 0 0 0.84 0 0.12 2.18 0 0 0.21 0 0.01 0 0.09 Clean 180

2 Vial C6F05 0 0.16 0 0.40 0 0 0.11 0 0 0 0 0 0.23 0 0.02 0 0 Clean 180

3 Vial C781B 0 1.05 0 0 0 0 0.01 0 0 0.55 0 0 0 0 0.01 0 0 Clean 180

4 Vial C9E34 0 14.79 5.42 10.99 0 161.27 0.03 0.44 3.30 21.47 0 0 0.76 3.02 9.04 1.32 1.64 Dirty 51

5 Vial C9235 0 0.11 0.69 0.11 0 0 0.04 0 0 0 0 0 0 0.28 0.01 0 0 Clean 180

6 Vial C4519 0 1.32 0 0.42 0 0.19 0.65 0 2.17 2.54 0 0 1.18 1.27 1.30 0.92 0.42 Clean 180

7 Vial CAD1A 0 1.53 0 0.71 0 1.51 0.20 0 0.65 1.64 0 0 0.13 0 0.31 0.02 0.38 Clean 180

8 Vial CAC06 0 2.25 0 0.95 0 1.24 0.13 0 1.09 1.59 0 0 0 0 2.21 0 0.02 Clean 180

9 Vial CABC8 0 1.31 0 0.83 0 4.68 0.10 0 0.42 0 0 0 0.22 0 0.25 0 0.50 Dirty 92

10 Vial CACF8 0 2.11 0 1.83 0 15.24 0.04 0 1.01 1.16 0 0 0 0 1.41 0.05 0.66 Dirty 8

11 Vial CADA6-X1 0 13.48 4.90 15.84 0 132.97 1.02 0.81 15.37 286.06 0 0 7.06 1.69 5.31 6.91 11.38 Dirty 29

12 Vial CADA9-D2 0 8.35 2.55 3.56 0 68.06 0.52 0.03 3.94 12.28 0 0 2.05 1.19 4.40 0.23 3.37 Dirty 53

Addendum Samples - Disinfectant

13 Sample A - Undiluted 0 136.81 71.42 13.332 0 0 5.07 0 27.64 0 0 0 5.523 0 62.11 8.80 13.35 Not Tested w/C3

14 Sample B - Diluted 128:1 0 0.89 0.43 83.11 0 0 0.17 0 0.75 0 0 0 41.40 0 0.04 0.80 2.99 Not Tested w/C3
All Values in ug/in2

Conclusions
due levels of these chemicals showed a large deposit of contami-
nation from the tap water, as well as the disinfectant chemicals. Surface disinfecting to reduce the presence of viral and bacteri-
The IPA showed a good, clean, localized test and passing SIR, al contamination is a critical process to create safe workplaces,
as did the control. These corrosive residues collect on surfaces but as hospitals have consistently proved, when a broadcast
and set up corrosion cells, causing intermittent performance aerosol method is used indoors, the risk of contamination vs.
and failing hardware in the areas where fogging occurs. disinfecting becomes a long-term problem. Aerosolized appli-

FIGURE 21. PCBA 1, case study #3: as received, not powered. FIGURE 22. PCBA 1, case study #3: exposed to fogging.

MAY 2022 PRINTED CIRCUIT DESIGN & FAB / CIRCUITS ASSEMBLY 43

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 DECONTAMINATION

TABLE 4. Ion Chromatography – Case Study #4

Ion Chromatography (Dionex ICS 3000 at Foresite) n/a = not applicable Localized Test SIR Testing Results

Sample Description Fluoride Acetate Formate Chloride Nitrite Bromide Nitrate Phosphate Sulfate WOA MSA Lithium Sodium Ammonium Results Time (Sec) 168 hr. 40°C/90%RH
Foresite Recommended Limits
1 3 3 3 3 6 3 3 3 25 1 3 3 3 Clean >120 Good Passing >1.0e8 ohms
for PCBA (No-Clean - SMT)
ID DOE Fog Exposure (All Dilutions were Made with Tap Water)

1 Sample 1 - Hypochlorite 3.91 15.65 0 81.24 0 6.65 0 0 23.65 0 0 0 28.65 0 Dirty 1 Failed - Limited at 1.0e6

Sample 2 - Hydrogen
2 3.26 4.68 0 9.24 0 3.16 0 0 2.16 0 0 0 6.65 0 Dirty 104 Failed - Limited at 1.0e6
Peroxide

3 Sample 3 - IPA 2.51 2.11 0 4.21 0 1.64 0 0 2.09 0 0 0 2.11 0 Clean 165 Pass 2.1e9 ohms

Sample 4 - Benzalkonium
4 3.63 4.81 0 113.15 0 9.87 0 0 36.35 0 0 0 41.24 0.27 Dirty 1 Failed - Limited at 1.0e6
Chloride (13%)

5 Sample 5 - Thymol oil 2.39 11.36 0 11.78 0 3.65 9.54 0 12.14 34.65 0 0 22.31 0 Dirty 57 Failed - 4.2e7 ohms
Sample 6 - Control
6 0 0.74 0 0.51 0 0.41 0 0 1.41 0 0 0 1.17 0 Clean 180 Pass 8.9e10 ohms
(No Exposure)
All Values in ug/in2

cations cover a large area but contaminate racks, trays, bins, tants, the workplace can be safe and fully functional without
boxes and equipment used in and on production hardware. creating a corrosive air-quality environment.
This method puts disinfectants in areas where few viruses or These case studies show a direct correlation to the applica-
bacteria are present: shelf tops, boxes, pallets, inside electronic tion of disinfectants in or around production hardware. We
equipment and on production hardware. must understand and qualify the workplace environment during
HVAC systems also pull the disinfectants into the system, production and WIP for electronic hardware, equipment used in
dispersing them back into the environment, impacting these production and testing, and all surfaces with which hardware
areas, even when not directly sprayed. Manufacturing offices will come in contact. These performance issues are not related
and common areas require good air purification to reduce to the electronics assembly process but the exposure to corro-
microdroplet exhalation from coughing and sneezing using sive contamination from the disinfecting environment. •
UVC and air-purification systems, along with face coverings
that dramatically reduce these risks. Using approved sprays
REFERENCES
and wipes, such as hydrogen peroxide or alcohol-based materi-
1. K. Middleton, Ph.D., “Cleaning and Disinfecting: Whole Room Fog-
als, reduces the viral load and permits better ways to protect
ging,” Cleanroom Technology Online, Jun. 1, 2020.
workers and electronic hardware.
Creating a safe workspace should include a clear plan for
worker safety but not at the expense of the equipment, product Ed.: This article was first published at the SMTA Pan Pacific Microelectron-
ics Symposium in January 2022 and is republished here with permis-
or working systems. There are times and places for broadcast
sion of the authors.
aerosol disinfecting, but with planning, organization and
understanding the corrosive nature of many of the disinfec-
TERRY MUNSON is president and founder of Foresite; terrym@
foresiteinc.com, and Phil Isaacs is senior engineer at IBM;
pisaacs@us.ibm.com.

FIGURE 23. Four fogging cycles. Exposure on the bottom side

of the PCBA. FIGURE 24. 4 ULV fogger.

MAY 2022 PRINTED CIRCUIT DESIGN & FAB / CIRCUITS ASSEMBLY 45

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 EMS

VANGUARD EMS:
Manufacturing the Smarter Way
Integrated flying probe testers and in-house MES have the
EMS firm leading the pack. by MICHAEL L. MARTEL

Vanguard EMS is one of the largest locally owned electronics In addition to circuit boards, many products are high-level
manufacturers in the Pacific Northwest, with a 77,000 sq. ft. assembly and box-build. Indeed, Vanguard is the FDA manu-
facility near Portland, OR. The company specializes in high- facturer of record for two final devices the firm produces from
reliability electronics products for the medical, aerospace and component assembly to the system level. That means Van-
defense, and infrastructure/industrial sectors. Some 70% of guard is permitted to ship directly to its customer’s customer.”
the firm’s customers are Fortune 500 companies. Founded in Because Vanguard’s origins lie with ex Tektronix engi-
1988 by Tektronix alumni, the company grew steadily and neers, test has been “part of our DNA” since the beginning,
was acquired in 2003 by Floyd Sutz, Vanguard’s CEO and an says Smith. “I don’t think there’s anybody on the West Coast
employee since 1995. who has test capability like we do. One of our primary goals
“Basically, everything we build has a high cost of failure,is to limit defects for the customer. We want to dramatically
reduce or eliminate time spent in the defect discovery and
especially out in the field,” said Chris Smith, director of sales.
“Defense and aerospace, for example, are about 55% of our repair and retest cycle. There’s a lot of waste around that.”
business. Medical is probably about 25%, and for those indus- “We evaluated several manufacturing execution systems
tries, these are products that are in the top five or 10% as farand found they were targeted more toward OEMs or manu-
facturers with fewer products and fixed flows,” said Joe Lariz,
as difficulty is concerned. That’s a high level, and yet this year
we will be marching up to about $70 million annually.” director of IT, and Anh Vu, director of manufacturing, via
email. “We needed a system that was
flexible vs. fixed, and we did not want
to take time trying to fit a square peg
into a round hole. In addition, we
wanted a system where our employees
could get everything they need, as
opposed to having to go to an MRP
system, document control system and
a shop floor control system. We spent
months interviewing our frontline
employees, asking them, ‘What do
you need to do your job effectively?’
This was the beginning of SMARTer
Manufacturing.
“We did not find [off-the-shelf
platforms] to be very adaptable for
our ever-changing customer needs, and
[we weren’t able] to easily adjust to
multiple quality standards and specific
customer requirements. In addition,
FIGURE 1. To meet stringent quality demands, Vanguard EMS seeks optimum flexibility we needed to be able to make it impos-
in manufacturing capability and capacity. sible to err in meeting standards and

MAY 2022 PRINTED CIRCUIT DESIGN & FAB / CIRCUITS ASSEMBLY 47

 EMS

customer requirements.” and technicians who use it, Vanguard engineers continue to
Enter SMARTer Manufacturing. That’s the name for refine and improve it.
Vanguard’s proprietary process flow and MES. According to Today, the entire Vanguard EMS production facility is
Smith, “SMARTer was designed from the ground up by our controlled through the novel MES. Beyond device records and
team members exclusively for electronics manufacturing. It’s tests, the MES governs who can work on a customer’s devices;
our no-compromise approach to building high-quality, reliable whether technicians have been appropriately trained; what
devices with comprehensive traceability.” tool, equipment or process has touched each device at every
The novel MES (FIGURE 2) began as a database that stage of manufacturing and more.
tracked every part, test and failure. Vanguard hired dedicated “Vanguard team members are unable to open customer
software engineers and programmers to develop the MES, documentation at their workstation, unless their ESD heel
and modeled its software validation program after AS9100 straps and wrist straps pass, and all their training records
requirements. The initial rollout phase took around 12 months are up to date and support all quality standards and cus-
from start to production release, and the system has been in tomer requirements. This is all managed in the barcode of their
place since 2007. By incorporating feedback from engineers employee badge and through an extensive plantwide barcod-
ing system,” said Lariz and Vu.
To complement its MES, Vanguard
uses INFOR Fourth Shift MRP and Agile
PLM, which links directly to SMARTer.

Passing the Test

Two Takaya APT-1400F series flying probe
testers are key resources in the SMART-
er system (FIGURE 3). These testers meet
the company’s requirements for accuracy,
speed and flexibility better than ICT fix-
tured testing, Vanguard says. Flying probe
testers are used when there isn’t time to
wait for an outside vendor to produce bed-
of-nails test fixtures, or the product isn’t at
the volume or maturity for ICT.
“Flying probe testing is the most flex-
ible tool to perform verification of product
build to specification,” said Roy McKen-
FIGURE 2. A Vanguard EMS employee works within the novel SMARTer MES. zie, Takaya Group manager. “On average,
you’re creating a test program in one to two
hours from CAD. You’re going through a
debug process that is six to 12 man-hours,
depending on the board. If it’s a very com-
plex, very large board, it can take a week,
but happily, there’s no additional hardware
required in your board testing.
“Generally, our flying probe tester cus-
tomers are testing boards within one to
three days once they get the first board off
the line because they’ve already developed
a program in advance. They are already
prepared in that they have the CAD, the
bill of materials and the schematics. The
program is ready by the time they get that
first board. At that point, they can debug
the program. Once that’s done, they’re
ready to proceed. Additionally, engineering
change orders are very easy, unless there’s
been a major change in the actual board
itself.
“Basically, you’re going into software
FIGURE 3. Vanguard staff use Takaya APT-1400F series flying probe testers. and saying, ‘Okay, this capacitor is now X

MAY 2022 PRINTED CIRCUIT DESIGN & FAB / CIRCUITS ASSEMBLY 49

 pcbchat.com
Recent Chats:
New HDP Initiatives The Latest ECAD Nickel-Less
with Jack Fisher Market Data Surface Finishes
and Madan Jagernauth with Wally Rhines with Kunal Shah

The Cadence-Dassault
Systèmes Integration
with Michael Jackson
and Stéphane Declee The PCB Podcast
 EMS

value instead of Y value.’ Verification is quick. The interval is

one to three days to testing, a comparatively short period of
time and the shortest in test technology today. If you’re going "WHEN A NEW KIT IS
to do any kind of testing in an automatic test environment, fly-
ing probe testing is the fastest from zero to testing your lot. As LAUNCHED TO THE FLOOR,
an example, should an ECO come down before the build with
fixtures, you’ll have to modify that fixture before that build THEY LOOK AT ALL THE
occurs. But conversely, with flying probe testers, you don’t
have to worry about that. You can make a change the day of
the build because it’s a simple software change.”
DEFECTS THAT HAPPENED
“Timing is essential to the SMARTer system,” Smith
added, “because we’re tracking defects throughout the entire IN THE KIT PRIOR,
process, and we can because we have test and inspection
equipment throughout the entire assembly process. As a AND THOSE GET FLAGGED
result, a defect with our SMARTer Manufacturing system is
not allowed to make it to the next step without being taken FOR ELIMINATION
care of at the step where the defect is found. A defect found
at the surface is addressed at that point; it’s taken care of, and
that reduces the number of defects overall. When we get to
IN THE NEXT RUN."
final testing, I can go to our [MES], pull up an assembly and
find all the defects related to that assembly, and I can even
zero-in on the actual solder joint where that defect occurred.
We then have a list of defects our employees can pick. They’re delivery and traceability of components, supplies, tools, peo-
all working from that list. ‘What component is it? What pin is ple and recipes are non-negotiables in the world of high-risk
it?’ We’ve got that information right at our fingertips, and the electronics. At Vanguard EMS, their manufacturing tools and
further upstream we can locate these defects and correct them, processes are designed to meet these high standards. •
the better. Whenever the team launches a new kit to the floor,
they look at all the defects that happened in the kit prior, and MICHAEL L. MARTEL is a freelance editor and marketer with 40
all those get flagged in the system for elimination as much as years’ experience in the SMT/PCBA industry; mmcmarketing@
possible in the next run.” gmail.com.
Many of the military products Vanguard builds are,
by their nature, constantly evolving – changes in design or
engineering ordered
by the customer,
Smith says. As such,
they are never sta-
ble enough to make
economic sense for
bed-of-nails testing.
Engineering changes
in bed-of-nails test-
ing cost a lot of time
and sometimes a rea-
sonable amount of
money – to change
the software, fixture
and any hardware
requirements.
“If you’ve got
a mature product,
you’re ready to go; if
you don’t, you gen-
erally don’t do this
because it’s not prac-
tical,” Smith said.
Device quality,
reliability, on-time FIGURE 4. Flying probes can test the top and bottom of a PCBA.

MAY 2022 PRINTED CIRCUIT DESIGN & FAB / CIRCUITS ASSEMBLY 51

 GETTING LEAN

‘Why’ Lean Six Sigma?

Lean Six Sigma training leads to effective, intrinsic problem-solving.

MUCH HAS BEEN written on the “how” of Lean Six Implementation challenges needed to be addressed.
Sigma. This column discusses the “why” behind Lean Initially, there was not enough detail in customer
Six Sigma. SigmaTron’s facility in Tijuana, Mexico, requirements for meaningful VOC analysis. KPIs were
began implementing its Lean Six Sigma program in based on yield rates rather than PPMs or DPMOs.
2018 as a way to instill a focused process improvement The data process was not measured or measurement
methodology in its automotive and medical customer system analysis (MSA) appropriate. The team’s lack of
projects. A consultant was brought in for initial train- expertise resulted in use of unsuitable process improve-
ing, and I volunteered to be the internal champion ment tools. However, the combination of training
after agreement that the necessary management sup- and hands-on experience gained as team members
port and resources would be put in place. The initial progressed through Six Sigma levels enabled them to
training sessions were designed to train the engineering identify the corrections needed to make the Lean Six
team as Green Belts and select production personnel as Sigma process highly effective.
Yellow Belts. As a Six Sigma Black Belt, my perspective has
One challenge in an electronics manufacturing changed from finding quick fixes to permanent solu-
services company is each customer has control of their tions. It has also extended my use of Six Sigma pro-
design. While some incorporate EMS-driven design cesses and tools into my personal life. I even developed
for manufacturability (DfM) recommendations, others a poka-yoke at home after losing my keys multiple
do not. Although SigmaTron’s production personnel times.
wanted to solve production problems as they arose, The benefits of Lean Six Sigma have become vis-
the root causes were often difficult to identify using ible to those outside the program. Projects in 2021
basic quality tools such as pareto charts without a resulted in a nearly $197,000 ROI, despite the disrup-
strong problem-solving methodology. With Lean Six tion on team interactions caused by Covid restrictions.
Sigma training, the team evolved from engineers and During recent audits for ISO 9000, IATF 16949 and
technicians trying to fix problems to a cohesive team VDA, the auditor said the Continuous Improvement
with the necessary tools to rapidly identify issues, department’s deployment of the Six Sigma methodol-
brainstorm possible root causes, test hypotheses, and ogy was a strength that complemented other meth-
implement the best solution. Issues that had taken odologies in place in the facility. Longer-term OEM
weeks to analyze with prior methods were addressed customers have commented on the improvements they
in days or hours. see in terms of the data-driven focus to problem solv-
Speed in problem resolution translates to better ing and the positive impact it has had on operational
yields, better schedule adherence, less rework and less excellence. In short, the benefits have more than justi-
scrap. Cycle time through the factory also improves fied the management support and resources provided
when minimal troubleshooting and debug is required to this program.
in test. In short, the ability to rapidly identify and The “why” behind Lean Six Sigma is more than
resolve issues saves money and time in many ways. cost or time savings. This philosophy is also more than FILEMON
The key advantages we saw early in the process a collection of tools and techniques. Instead, it is a SAGRERO
included: continuous learning process in which concepts change is continuous
■ The ability to find and eliminate causes of defects practitioners’ abilities to problem solve in highly effec- improvement
engineer and a
and errors using the define, measure, analyze, tive ways. Identifying ways to improve has become as
Six Sigma Black
implement, control (DMAIC)/rapid problem-solv- much a subconscious activity as breathing, and the
Belt at SigmaTron
ing methodology DMAIC process ensures root-cause assumptions and
International in
■ Reduction in cycle times and cost of operations good ideas are thoroughly tested, reviewed and docu- Tijuana, Mexico;
using value stream mapping (VSM) and single- mented before any changes are implemented. • filemon.sagrero@
minute exchange of die (SMED) tools sigmatronintl.com.
■ Improved productivity through adoption of Lean
principles and Kaizen events
■ The ability to better meet customer expectations
through voice of the customer (VOC) focus and key
performance indicator (KPI) measurements
■ Return on investment (ROI) and improved profit-
ability as improvements were implemented.

MAY 2022 PRINTED CIRCUIT DESIGN & FAB / CIRCUITS ASSEMBLY 53

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 SEEING IS BELIEVING

A One-Hour Stand
A self-proclaimed “visionary” doesn’t always understand the true meaning of
partnership.

IN A PERFECT world, there would be truth in advertising. laundering of his attire. Shabby chic. Nonconformity
It would be jaw-dropping to hear a politician say: as conformity. Visionaries want to make a statement,
“My statements yesterday regarding the ignorance and trivialities like rules are for Little People. So he
of voters on the issues of the day were not taken out declared to us, without prompting or an ounce of
of context. I meant every word I said, down to the shame, with that subcontinental swagger typical of
last comma, semicolon and exclamation point, and I those who write code, hit the jackpot once, and there-
stand by them. Many of you don’t even know what by think they know everything and deserve admittance
a semicolon is, much less how to use it. What’s more, to elite circles. They want to share their enlightenment.
exploiting that gift of voters’ ignorance has propelled They make their own rules. Thus, people need to be
my political career and enhanced my electoral viabil- reminded of their place in the Silicon Valley caste
ity. Systems are meant for gaming, and I’m seizing the system, pretensions to egalitarianism be damned. Be
moment my schooling and ambition has set for me. grateful Greatness has arrived to grant you time with
Here in the land where preparation meets opportunity, His Presence. Keep your prejudices to yourself. Maybe,
mine eyes have seen the glory. God Bless America!” just maybe, you’ll get in on the IPO.
Or to hear a certain classism laid bare with this He had a Great Idea. (Of course he did). He
frank preschool prospectus: needed help refining his process. Things weren’t quite
“Vanilla Bean Curd Country Daycare is obsessed fitting together. Parts were cracking – or breaking
with our Mission of empowering little ones to succeed apart prematurely while in use and still under war-
in life, especially when they matriculate and become ranty. This was embarrassing. Certainly not befitting
Big Ones with Influence. Fortunately for you, the a Visionary. The nominal design software data weren’t
aspiring parent of a Young Chancer, there’s us. One meshing with the actual part data. Heat maps were
must start early in the relentless pursuit, cultivation glowing red, not a good color. His additive manufac-
and maintenance of privilege through an awareness turing process was subtracting from his cashflow at an
and employment of the baser survival and mobility unplanned rate, and he needed to know why. The VCs
instincts. We are unabashedly proud to be the pro- were furrowing their brows and demanding answers.
verbial first cobblestone on that Machiavellian road. Where were the defects coming from? What was their
Right Daycare begets Right Preschool begets Right extent? For answers to these mysteries, he needed his
Kindergarten begets Right Elementary School begets parts CT scanned. Colleagues pointed him to us. Thus,
Right Prep School begets Right Ivy League School he came to be parked at an off-putting angle in front of
begets connections and prominence and money to our building. He needed help.
support multiple couplings, families and schooling for That’s us: We’re “The Help.”
children from those sources. Repeat the process with We had a CT scanner. He didn’t. His problem was
new children. (See our rankings.) Get real before you our solution. Thus, free exchange is born. Naturally,
get squashed. It’s a competitive world, and connections he wanted a Partnership, but first he had to dazzle.
matter more than ever. Make them here. Skip the line. He beckoned with warm, ingratiating buzzwords,
You’re with Our Kind. Get the cash flowing. What will or so he thought. Series A, B, C and D rounds of fund-
it be? Winner or loser? A lifetime beckons. With us, ing. Stanford pedigree. A-list board (gratefully lack-
your little darlings have ‘high’ and ‘worth,’ as in ‘High ing some of the same astute judges of character who
ROBERT
Net Worth,’ emblazoned on their skulls like QR codes. recognized potential in Elizabeth Holmes). Tons of
BOGUSKI is
You’ll thank us with your donations.” pending orders. Huge upside potential. Ad infinitum. president of Datest
This is not a perfect world. Agendas like those The firehose analogy is accurate: Overwhelm the prey Corp. (datest.com);
displayed above remain hidden. For a reason. We are with details. Don’t allow them to interject a doubt or rboguski@datest.
left to figure out motivations on our own. a skeptical question. Never stop talking. Allow them com. His column
So it is with Partnership. The term has become to bask in the glow. Control the subject and drive the runs bimonthly.
elastic. Seller beware. bandwagon. Cultivate greed and envy.
He pulled up one fine day in a Tesla. (It’s always We sat through a condescending PowerPoint about
a man.) The indicative license plate proclaimed his soon-to-be iconic company and its game-changing
M3MYS3LF&1. Sic transit gloria mundi. So was products, designed to make fluid flow faster downhill.
his lack of spatial reasoning: The vanity-plated roll- (Relative to what?) He is in search of trusted, durable
ing declaration was parked at a 30° angle to parallel. Partners who can help him make his product better
Sartorially to match: No tie. No socks. No obvious and get it to market faster. (That flow thing again.)

MAY 2022 PRINTED CIRCUIT DESIGN & FAB / CIRCUITS ASSEMBLY 55

 SEEING IS BELIEVING

Are we of like-minded ambition, enthused about joining him? Some will admit x-rays; some won’t.
What does “joining” mean? Does it come with a number That’s where honesty comes in. If it’s an unfamiliar appli-
assigned to it, with multiple trailing zeroes? cation, manufacturing technique, material, composite or coat-
Perhaps it’s a function of age, growing irascibility, and ing, we sometimes admit to the customer its newness (to us).
a keener awareness of one’s limited time on the planet, but We’re willing to learn, and for that we make a deal. We offer
these presentations, in their faux boosterism, blend together. to attempt a few test images to see if we can capture the view
All show. They’re slick. Slick as in B*O*R*I*N*G. Enduring the customer wishes to obtain, which is often vague due to lack
them means you won’t recover the hours spent listening to of a statement of work or technical ignorance both feigned
them. At slide 42 one wants to stand up and scream, “What and actual – or both! (See above.) These test images are usu-
do you want?” A common tactic is to deluge the recipient ally offered free of charge, as long as the customer isn’t a jerk.
with a stupefying torrent of information, hoping it will render If we succeed with those images, terrific. We can then discuss
the prey senseless, or at least more pliable, when negotiations a program that is mutually acceptable and work out the cost
begin. in collaboration
That’s why with the project
he considers us engineers. If we
“The Help.” don’t, then, as
Often this the saying goes,
is a moment of no harm, no
revelation in foul. We tried,
the test engi- and it didn’t
neering and cost the cus-
failure analysis tomer a thing.
world. The cli- No risk for
ent’s pattern of them. See you
answers to spe- next project.
cifics betrays Historically
technical igno- this approach
rance. As in, has worked
“We were hop- well. It works
ing you could really well with
devise a test engineers from
plan for us,” big-name com-
or, “We weren’t panies that
sure which Beware the tech "visionary" who inflates your "partnership.” often have labs
x-ray system with our own
approach was capabilities and
best for our needs. We were hoping you could write down more, but who lack the speed, flexibility and responsiveness
an inspection strategy for us to use for future statements of we offer. Two-day turnaround often is a compelling alterna-
work.” tive to six- or eight-week turnaround using internal corporate
You know, the kind good enough to go anywhere to any resources, especially if you don’t need a glossy report and rely
competitor to obtain a cheaper quote, otherwise known as on the images to tell the tale, most especially in line-down situ-
Free Engineering. Often, like a good trial lawyer, the client ations. The economics of urgency sells itself.
knows the answer to his question when he asks it. He’s merely Ease of use notwithstanding, this is a business proposition.
fishing for commitment. How far will he open up? What will The operating assumption remains that if we succeed – how-
a Partnership entail? ever success is agreed to and defined – the customer will pay.
But I digress. Slide 42 was the midpoint. The financial Free images are a means to an end, namely a successful work-
pitch was yet to come. ing inspection program, the terms of which are defined as we
Often we attempt to disarm wary or scheming customers go. That is understood. For most, it would seem obvious and
by employing blunt honesty. For many clients it is an invigorat- not need an explanation.
ing break from their day-to-day to hear us tell them we have Except to the Visionary with the parking problem.
no experience with their business and no clue what a good When I tell him he’ll have to pay a sum for our services,
part or system means to us. But we're willing to learn. We he reacts with the facial features of one who has ingested
are circuit board people who operate a great big CT scanning something unpleasant, probably at the orders of his mother,
machine. Inevitably, engineers find it advantageous to bring bringing back unsavory childhood memories of folk medicine.
requests to scan items that are not printed circuit boards. Thus infused, he speaks indignantly of looming betrayal of the
Included among these are additive-manufactured parts, some goodwill our Partnership is built on.
with exotic materials of varying thicknesses and densities. Built on? We only met an hour ago. •

56 PRINTED CIRCUIT DESIGN & FAB / CIRCUITS ASSEMBLY MAY 2022

 SCREEN PRINTING

When All the Lights are Green

The time to squeeze out more efficiency is when everything is in spec.

WHAT KIND OF approach do you generally take? Do iaturization’s challenges can elevate the solder budget.
you follow the “if it ain’t broke, don’t fix it” mantra, Leveraging sensor technology that monitors the paste
or are you more the “it’s good, but it could be bet- roll height allows operators to take the “Goldilocks”
ter” type? In electronics manufacturing, continuous approach: not too much, not too little – just the right
improvement is often discussed, but how much does amount of paste in front of the blade. On-target paste
your organization adhere to this philosophy when the volume reduces both material expense and the envi-
shop floor is humming and everything is within spec? ronmental cost of waste.
This is when process engineers should try to squeeze
out even more efficiency. Quality up. When it comes to improving quality,
Certainly, there is urgency around a process that is leveraging Six Sigma tools can further refine an in-
not running as it should. However, when all the lights specification process and move conditions on the very
on the line are green, there is likely opportunity for edge of acceptable to the center of the range. Data
more improvement than you realize. Consider chal- mining carried out through Excel or any other statis-
lenging the process through the lenses of incremental tics correlation method – including my favorites XBar
cost reduction and quality enhancement. and Range – can provide a view into process centering
In the stencil printing process, there are several and spread. Then, Cp and Cpk analysis will reveal the
possible avenues for lowering cost and raising quality, repeatability of the process. Perhaps there’s a green
even when everything is within spec: tick in the box, but only on the border of the “within
spec” range.
Cost down. The first and most obvious area for Using an SPI tool to data mine, one can pinpoint
resource optimization is understencil cleaning. This certain areas of the board that may be on the verge of
sub-process of stencil printing has several costs associ- moving from green to amber. Looking at elements like
ated with its operation, including time (output reduc- aperture design, processes and material sets (squeegees,
tion) and a fixed cost (fabric and solvent consumables) tooling, etc.) and making slight changes may deliver
for every clean. A majority of print platform suppliers more bandwidth to the process and quality to the
ship equipment with relatively liberal default settings product.
for fabric advance (how much is used for each clean) Last, using design of experiments (DoE) meth-
and solvent volume. This is based on assumptions a odology offers continuous improvement opportuni-
manufacturer may be cleaning a very dirty stencil with ties. This is a bit of a forgotten tool, but for process
numerous apertures across the entire length of the fab- engineers striving for quality utopia, it is essential.
ric, so high debris removal must be accommodated. In Many SPI software packages contain DoE functional-
essence, the defaults are set for worst-case scenarios, ity; some are more user-friendly and thorough than
as is fairly standard practice. Optimizing these settings others. DoE is not something to undertake before the
based on specific process conditions has the potential process is in control. Rather, DoE is about finding the
to reduce waste through streamlined consumables best optimal solution for the centered process, push- CLIVE ASHMORE
delivery. ing Cp/Cpk higher than where the process began. is global applied
process engineering
The other understencil cleaning analysis that Engaging in DoE is also quite revealing and identifies
manager at ASM
should be conducted is cleaning frequency. In addi- the most and least important elements of the printing
Assembly Systems,
tion to elevated consumables use, there is an output process. We often talk about stencil printing factors
Printing Solutions
cost: When you’re not printing, you’re not producing. such as speeds and pressures as if they are all equally Division (asmpt.
Leveraging sophisticated software and SPI tools can important; they’re not. Some elements, like separation com); clive.
deliver deep data analysis and a recommended clean- speeds, can have a massive amount of leeway in certain ashmore@asmpt.
ing frequency that allows the process to remain in applications. And some, such as print pressure, simply com. His column
control. Perhaps you’re cleaning too often, and that is do not. Contemporary DoE software tools are very appears bimonthly.
money wasted. slick, taking the areas you are interested in evaluating
Second, solder paste management is an area a pro- and running countless sequences to find the optimal
cess engineer should examine to further reduce cost. conditions and inputs.
Maximizing paste consumption can have a significant Extra time is a rarity these days, but when time is
impact on overall process cost. While solder mate- on your side, and the stencil printing operation is all
rial prices have stabilized in recent years, the move systems go, use the opportunity to make the process
toward Type 5 and even Type 6 pastes to handle min- even tighter and the output quality superior. •

MAY 2022 PRINTED CIRCUIT DESIGN & FAB / CIRCUITS ASSEMBLY 57

 MACHINES MATERIALS TOOLS SYSTEMS SOFTWARE

measurement in automotive and indus- HDR scanning to capture accurate data

trial inverters, voltage dividers for battery on glossy or matte surfaces. HDR algo-
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gers and test and measurement equip- lighting conditions, adjusting brightness
ment. Available in 0805, 1206, and 1210 and focus. Surfaces can be scanned in
case sizes, with resistance values from as little as 1 sec. Can perform pass/fail
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range of -55° to +155°C, and operating or other part scans.
PULSONIX V. 12.0 PCB DESIGN TOOL voltage up to 1,000V for largest case
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XJTAG 3.12 BOUNDARY SCAN edly saves energy and reduces thermal
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XJTAG v. 3.12 tool for debugging bound- ponents. Ideal for SMT devices with
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to plane rules. Has additional enhance-
Can work more efficiently with XJEase
ments to edit differential pair traces. Shenmao
code by providing powerful searches that
Pulsonix scan through all code files in project. shenmao.com

pulsonix.com
XJTAG HENKEL BERQUIST LIQUI FORM
SATURN PCB DESIGN TOOLKIT xjtag.com TLF 10000 GEL TIM
V. 8.08 Henkel Berquist Liqui Form TLF 10000
Saturn PCB Design Toolkit v. 8.08 is a one-part, high thermal conductivity dis-
freeware PCB calculator for microstrip, pensable gel provides heat transfer for
stripline, differential pair, via current, PCB high-power electronic components. Pro-
trace current, planar inductor, padstack, vides 10.0W/m-K thermal conductivity
crosstalk, Ohm’s Law, XC XL reactance, for applications where environments can
BGA land, Er effective, wavelength and be extreme or unpredictable and reli-
PPM. Incorporates current capacity of PCB ability is critical. High gap stability for
trace, via current and differential pairs. gaps ranging from 0.5 to 1.5mm. Thermal
KEYENCE VR-6000 3-D OPTICAL impedance of 0.45 Kcm2/W at 0.5mm
Saturn PCB PROFILOMETER bond line thickness. Thermal conductivity
saturnpcb.com VR-6000 3-D optical profilometer is of 10.0W/m-K. Fast and easy dispensing
designed with built-in motorized rota- and compatibility with a wide range of
VISHAY DRALORIC TNPV0805 tional unit. Reportedly takes 3-D mea- dispensing equipment options; stable
E3 RESISTORS surements around circumference of viscosity for less material waste. Lower
Draloric TNPV0805 automotive-grade part without blind spots. Wall thickness, dispensing pressure and assembly force
high-voltage thin-film flat-chip resistors undercuts and cross-sectional measure- place less stress on components.
combine operating voltages to 450V with ments can be taken without cutting or
tolerance of ±0.1% and TCR down to destroying target. Full surface data can Henkel

±10ppm/K. Typical applications for AEC- be captured with 0.1µm resolution. Offers henkel-adhesives.com/us/en/
Q200-qualified devices include voltage place-and-press interface partnered with

58 PRINTED CIRCUIT DESIGN & FAB / CIRCUITS ASSEMBLY MAY 2022

MACHINES MATERIALS TOOLS SYSTEMS SOFTWARE

ing microdots of UV adhesive in medical automatically, including radiation dose

device applications. information. Reportedly ideal for inspect-
ing radiation-sensitive components.
Techcon

techcon.com Viscom

viscom.com

EMIL OTTO EO-Y-14A, EO-Y-014C

FLUXES
EO-Y-014A and EO-Y-014C alcohol- and
water-based fluxes have been developed
for use in wave and selective solder-
ing. Solids content and acid value have
changed compared to EO-Y-014B; remain- TRI TR8100H SII ICT
ing formulation stays the same. Are char- TR8100H SII high-density pin count in- YINCAE DA158N DIE ATTACH
acterized by good soldering properties. circuit tester with vacuum fixture tar- ADHESIVES
EO-Y-014A has solids content of 2%; EO- gets low-voltage testing market. Is also DA158N die attach thermal conductive
Y-014C has solids content of 4%. Have for large, complex PCBAs. Reportedly and electrical insulating adhesives can
wide process window with high thermal ensures full pin contact, with up to 11,088 be fast cured at low temp. Reportedly
stability. Contain organic, halogen-free pin digital MUX-free architecture. Has have high thermal conductivity and can
activating additives formulated with low built-in auto-calibration and self-diag- achieve thin bonding line thickness; have
addition of synthetic resin. Can be used nostics. excellent bonding strength and thermal
for hand soldering and cable assembly. cycling performance. Can withstand
Test Research, Inc.
Alcohol content is 15%. extreme temp. (-273°C) without delami-
tri.com.tw/en/index.html nation. Can be used for die attach appli-
Emil Otto cations for harsh conditions and bare
emilotto.de chip protection in advanced packages
such as memory cards, chip carriers,
hybrid circuits and multichip modules.

Yincae

yincae.com

AKROMETRIX TABLETOP DIGITAL

VISCOM 3-D MXI SYSTEM X8011-III FRINGE PROJECTION 2.0 (TTDFP2)
Tabletop Digital Fringe Projection 2.0
X8011-III automated 3-D MXI resembles
(TTDFP2) provides fast and accurate sur-
TECHCON TS9800 SERIES JET VALVE exterior of iX7059 systems. To inspect
face topography for discontinuous sur-
TS9800 series jet valve dispensing sys- THTs or identify voids in surface solder-
faces at room temp. Includes optional
tem is comprised of TS9800 Piezo-actu- ing, analysis parameters can be selected
vibration isolating table. Accommodates
ated jet valve and TS980 smart controller. and adjusted quickly during operation.
samples up to 450mm x 450mm, with
Uses piezo, noncontact jetting technol- Provides overview of tools required to
variable field of vision ranging from 45
ogy for increased speed and accuracy create inspection plan for automatic
x 36mm to 192 x 240mm. Reportedly can
during dispensing process. Is capable x-ray inspection. 3-D reconstructions can
handle nearly any substrate, capable of
of dispensing dots and lines as small as be achieved with computed tomography.
capturing up to 5.3 million data points in
0.5nL at up to 1500Hz continuous and Options are available as part of XVR
1 sec. Has z-resolution down to 2.5µm.
2000Hz max bursts, jetting viscosities software. Individual layers of irradiated
up to 2 million cps. Modular features object provide nondestructive informa- Akrometrix
include external power source. TS980 tion on whether or not manufacturing akrometrix.com
Smart Controller offers touch-screen defect is present. Smart networking is
interface, reportedly featuring fast setup integrated into production line. Overlap
and easy calibration. Includes standard between MXI and AXI properties. Inspec-
internet port. Applications include edge tion data from 3-D SPI and post-reflow
sealing and end sealing of LCD and OLED systems can be compared at verification
displays; die bonding and frame bond- station with detailed 3-D MXI results.
ing for camera module assembly; jet- Manual x-ray system reads inspection
ting silicone phosphor in LED assembly; plan from production line to automati-
dispensing underfill in microelectronic cally approach only positions on assem-
package applications on PCBAs; apply- bly that need to be verified. Reports with
result and system data are generated

MAY 2022 PRINTED CIRCUIT DESIGN & FAB / CIRCUITS ASSEMBLY 59

TECHNICAL ABSTRACTS

In Case You Missed It

Additive Manufacturing Solder Joint Reliability

“Improved Modeling of Kinematics-Induced Geomet- “The Effect of Electric-Thermal-Vibration Stress Cou-

ric Variations in Extrusion-Based Additive Manufac- pling on the Reliability of Sn-Ag-Cu Solder Joints”
turing Through Between-Printer Transfer Learning” Authors: Xinlan Hu, et al.
Authors: Jie Ren, et al. Abstract: The damage of the package structure,
Abstract: The authors deal with the challenge by caused by the multi-stress coupling of various environ-
establishing a mathematical model that quantifies mental factors, can lead to electronic device failure.
the printing width variations along the printing paths Therefore, through the finite element method, the
induced by printing speed and acceleration. The model reliability analysis of three kinds of lead-free Sn-Ag-
provides vital information for predicting infill pattern Cu solders (SAC 105, SAC 305, SAC 405) in ball
nonuniformity and potentially enables using G-code grid array (BGA) packaging was conducted under the
adjustment to compensate for the infill errors in future conditions of thermoelectric coupling and random
research. In addition, since the model captures the vibration, respectively. The results, according to the
mechanism of kinematics-induced variations, it pro- modified Coffin–Mason model, indicate SAC 405 has
vides a way of between-printer knowledge transfer on the largest plastic strain range and the shortest fatigue
estimating printing errors. This article further proposes lifetime under thermoelectric coupling. As a counter-
an informative-prior-based transfer learning algorithm part, SAC 105 has the smallest plastic strain range and
to improve the quality prediction model for a printer the longest lifetime. However, under random vibration
with limited historical data by leveraging the shared load, by addressing the Miner linear damage rule, the
data from interconnected 3-D printers. A case study empirical formula of Manson high-cycle fatigue and
based on experiments validated the effectiveness of the Steinberg’s three band theory, the fatigue lifetime of
proposed methodology. (IEEE Transactions on Auto- SAC 405 is the longest, which is twice as much as SAC
mation Science and Engineering, March 2021, https:// 105 and SAC 305. Furthermore, based on the linear
ieeexplore.ieee.org/document/9380390) damage superposition approach, the fatigue lifetime
is predicted as SAC 305 < SAC 105 < SAC 405 under
multi-stress coupling of electric, thermal and random
Nanosolder vibration conditions. These results will provide theo-
retical support for improving the application reliability
“Molecular Dynamics Simulation on Wetting of Silver of packaging in complex environments. (Journal of
Nanosolder on a Diamond Surface” Electronic Materials, November 2021, https://link.
Authors: Muhammad Saad Ali, et al. springer.com/article/10.1007/s11664-021-09302-y)
Abstract: Analyzing the wetting behavior of silver
on a diamond substrate is crucial prior to joining and
printing diamond chips in electronics, bioimplants and Thin Films
cutting tool industries. The authors used molecular
dynamics models to overcome the hydrophobic behav- “Perovskite Oxide Ferroelectric Thin Films”
ior. It was observed the hydrophilic character was well Authors: Mingyue Tian, Lan Xu and Ya Yang
promoted when a nanosolder block of silver was col- Abstract: How to prepare high-performance
lided at a certain velocity on a diamond substrate in a Perovskite oxide thin-films is the most difficult chal-
hydrodynamic state, rather than when it was station- lenge for researchers. Multiple factors determine the
ary and then heated on diamond. Hydrodynamic wet- application area of thin films and influence the perfor-
ting led to rapid spreading, which in turn elucidated mance of thin films. The preparation of the material
a high rate of change in contact area to the highest determines its structure; the structure further influ-
11 832 Å2 and a high rate of decrease in contact angle ences the material's performance; and the performance
This column provides
to the lowest 23° at the highest contact velocity of decides the material's application, indicating these four
abstracts from recent
19.7km/s in minimum time. Therefore, hydrodynamic factors are inextricably linked. This article reviews the
industry conferences
wetting has a leading margin for silver coating on dia- preparation methods of perovskite oxide films and
and company white
papers. Our goal is
mond surfaces over temperature, slab separation and various factors that affect film properties, as well as
to provide an added hydrostatic wetting. This paper provides theoretical basic physical properties. This paper lists methods to
opportunity for readers insights for effective thin-film development in the least improve the physical properties of thin films and the
to keep abreast of possible time, with the lowest solder consumption. latest applications in various fields in recent years.
technology and (Physical Properties of Materials and Interfaces, April (Advanced Electronic Materials, March 2022, onlineli-
business trends. 2022, pubs.acs.org/doi/10.1021/acs.jpcc.2c00124) brary.wiley.com/doi/10.1002/aelm.202101409)

60 PRINTED CIRCUIT DESIGN & FAB / CIRCUITS ASSEMBLY MAY 2022

 The 2nd Edition of

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