DM74LS169A Synchronous 4-Bit Up/Down Binary Counter

August 1986
Revised April 2000

DM74LS169A
Synchronous 4-Bit Up/Down Binary Counter
General Description enabled will produce a low-level output pulse with a dura-
tion approximately equal to the high portion of the QA out-
This synchronous presettable counter features an internal
put when counting UP, and approximately equal to the low
carry look-ahead for cascading in high-speed counting
portion of the QA output when counting DOWN. This low-
applications. Synchronous operation is provided by having
level overflow carry pulse can be used to enable succes-
all flip-flops clocked simultaneously, so that the outputs all
sively cascaded stages. Transitions at the enable P or T
change at the same time when so instructed by the count-
inputs are allowed regardless of the level of the clock input.
enable inputs and internal gating. This mode of operation
helps eliminate the output counting spikes that are nor- All inputs are diode clamped to minimize transmission-line
mally associated with asynchronous (ripple clock) effects, thereby simplifying system design.
counters. A buffered clock input triggers the four master- This counter features a fully independent clock circuit.
slave flip-flops on the rising edge of the clock waveform. Changes at control inputs (enable P, enable T, load, UP/
This counter is fully programmable; that is, the outputs may DOWN), which modify the operating mode, have no effect
each be preset either HIGH or LOW. The load input cir- until clocking occurs. The function of the counter (whether
enabled, disabled, loading, or counting) will be dictated
cuitry allows loading with the carry-enable output of cas-
solely by the conditions meeting the stable setup and hold
caded counters. As loading is synchronous, setting up a
times.
low level at the load input disables the counter and causes
the outputs to agree with the data inputs after the next
clock pulse. Features
The carry look-ahead circuitry permits cascading counters ■ Fully synchronous operation for counting and
for n-bit synchronous applications without additional gating. programming.
Both count-enable inputs (P and T) must be LOW to count. ■ Internal look-ahead for fast counting.
The direction of the count is determined by the level of the
■ Carry output for n-bit cascading.
UP/DOWN input. When the input is HIGH, the counter
counts UP; when LOW, it counts DOWN. Input T is fed for- ■ Fully independent clock circuit
ward to enable the carry outputs. The carry output thus

Ordering Code:
Order Number Package Number Package Description
DM74LS169AM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
DM74LS169AN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

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DM74LS169A
Logic Diagram

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 DM74LS169A
Timing Diagram

Typical Load, Count, and Inhibit Sequences

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DM74LS169A
Absolute Maximum Ratings(Note 1)
Note 1: The “Absolute Maximum Ratings” are those values beyond which
Supply Voltage 7V the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Input Voltage 7V Characteristics tables are not guaranteed at the absolute maximum ratings.
Operating Free Air Temperature Range 0°C to +70°C The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Storage Temperature Range −65°C to +150°C

Recommended Operating Conditions

Symbol Parameter Min Nom Max Units
VCC Supply Voltage 4.75 5 5.25 V
VIH HIGH Level Input Voltage 2 V
VIL LOW Level Input Voltage 0.8 V
IOH HIGH Level Output Current −0.4 mA
IOL LOW Level Output Current 8 mA
fCLK Clock Frequency (Note 2) 0 25 MHz
Clock Frequency (Note 3) 0 20 MHz
tW Clock Pulse Width (Note 4) 25 ns
tSU Setup Time Data 20
(Note 4) Enable
20
T or P ns
Load 25
U/D 30
tH Hold Time (Note 4) 0 ns
TA Free Air Operating Temperature 0 70 °C
Note 2: CL = 15 pF, R L = 2 kΩ, TA = 25°C and VCC = 5V.
Note 3: CL = 50 pF, R L = 2 kΩ, TA = 25°C and VCC = 5V.
Note 4: TA = 25°C and V CC = 5V.

Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Typ
Symbol Parameter Conditions Min Max Units
(Note 5)
VI Input Clamp Voltage VCC = Min, II = −18 mA −1.5 V
VOH HIGH Level VCC = Min, IOH = Max
2.7 3.4 V
Output Voltage VIL = Max, VIH = Min
VOL LOW Level VCC = Min, IOL = Max
0.35 0.5
Output Voltage VIL = Max, VIH = Min V
IOL = 4 mA, VCC = Min 0.25 0.4
II Input Current @ Max VCC = Max Enable T 0.2
mA
Input Voltage VI = 7V Others 0.1
IIH HIGH Level VCC = Max Enable T 40
µA
Input Current VI = 2.7V Others 20
IIL LOW Level VCC = Max Enable T −0.8
mA
Input Current VI = 0.4V Others −0.4
IOS Short Circuit Output Current VCC = Max (Note 6) −20 −100 mA
ICC Supply Current VCC = Max (Note 7) 20 34 mA
Note 5: All typicals are at VCC = 5V and TA = 25°C.
Note 6: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 7: ICC is measured after a momentary 4.5V, then ground, is applied to the CLOCK with all other inputs grounded and all the outputs OPEN.

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 DM74LS169A
Switching Characteristic
at VCC = 5V and TA = 25°C
From (Input) RL = 2 kΩ
Symbol Parameter To (Output) CL = 15 pF CL = 50 pF Units
Min Max Min Max
fMAX Maximum Clock Frequency 25 20 MHz
tPLH Propagation Delay Time Clock to
35 39 ns
LOW-to-HIGH Level Output Ripple Carry
tPHL Propagation Delay Time Clock to
35 44 ns
HIGH-to-LOW Level Output Ripple Carry
tPLH Propagation Delay Time Clock to
20 24 ns
LOW-to-HIGH Level Output Any Q
tPHL Propagation Delay Time Clock to
23 32 ns
HIGH-to-LOW Level Output Any Q
tPLH Propagation Delay Time Enable T to
18 24 ns
LOW-to-HIGH Level Output Ripple Carry
tPHL Propagation Delay Time Enable T to
18 28 ns
HIGH-to-LOW Level Output Ripple Carry
tPLH Propagation Delay Time Up/Down to
25 30 ns
LOW-to-HIGH Level Output Ripple Carry (Note 8)
tPHL Propagation Delay Time Up/Down to
29 38 ns
HIGH-to-LOW Level Output Ripple Carry (Note 8)
Note 8: The propagation delay from UP/DOWN to RIPPLE CARRY must be measured with the counter at either a minimum or a maximum count. As the
logic level of the UP/DOWN input is changed, the ripple carry output will follow. If the count is minimum, the RIPPLE CARRY output transition will be in
phase. If the count is maximum, the RIPPLE CARRY output will be out of phase.

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DM74LS169A
Physical Dimensions inches (millimeters) unless otherwise noted

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
Package Number M16A

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 DM74LS169A Synchronous 4-Bit Up/Down Binary Counter
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Package Number N16E

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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