DRAM Technology

: Fundamentals, Challenges in DRAM, Future technology direction

Sept. 28. 2001

Kinam Kim

Semiconductor R&D Center

Samsung Electronics Co., Ltd.

Kinam Kim
ELECTRONICS
 Contents

1. Introduction
1.1. Overview of Si-technology
1.2. Brief review on Si-memories.

2. Fundamentals of DRAM
2.1. Data storage in DRAM cell
2.2. Sensing signal margin
2.3. Considerations for DRAM
2.4. Key process technologies for DRAM

3. Challenges in DRAM

4. Recent Studies for Future DRAM

Kinam Kim
ELECTRONICS
 1.1 Overview of Si-technology

- Trend of Information storage capacity

- Trend of Information processing capacity
- Trend of advances of semiconductor technology
- Trend of Fab.cost
- Trend of complexity of DRAM process

Kinam Kim
ELECTRONICS
 Information Storage Capacity of Si-Chips(DRAM)
1011 64Gb
Human Memory
16Gb
1010
4Gb

109 1Gb Encyclopedia

No.of Bits/Chip

256Mb
2hrs. CD Audio
30 sec HDTV
108
64Mb

16Mb
107
4Mb Book
1 min CD Audio
1Mb
106 1/4 sec HDTV
256Kb

105 64Kb
Page
1970 1980 1990 2000 2010
Year

Kinam Kim
ELECTRONICS
 Information Processing Capacity of Si-Chips(CPU)
105

104
Performance(MIPS)

Real time
103
3-D graphic

102

101

100

10-1
1970 1980 1990 2000 2010
Year
Kinam Kim
ELECTRONICS
 Advances of Semiconductor Technology

10
Minimum Feature Size(µm)

Optical Lithography
1

Optical Lithography Limit

0.1
New Gen. Lithography

Si-Device(CMOS) Limit(?)

0.01
1970 1980 1990 2000 2010
Year
Kinam Kim
ELECTRONICS
 Trend of the Cost of Semiconductor Fabs.
106

105
> 10.0 B$
Fab.
Cost of Fab (M$)
104
> 2.5 B$
Fab.
103

102

101

100
1970 1980 1990 2000 2010
Year
Kinam Kim
ELECTRONICS
 Process Complexity vs. DRAM generation
9

Process Complexity 7

0
1M 4M 16M 64M 256M1G 4G 16G 64G

Storage Capacity

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ELECTRONICS
- For the last 20 years, Si-technology has achieved great
success by “Shrink Technology” for higher density and higher
performance

* > x 1000 storage capacity

* > x 1000 performance
* > x 1/10 device size

- However, Si-technology based on “Shrink Technology” exposes many issues.

* Cost issues(Fab, Equipment, Process Complexity, Variation)

* Power issues
* Yield

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ELECTRONICS
 1.2. Brief review on Si-memories

DRAM SRAM Flash FRAM

WL
WL WL WL
Vcc
FG
Load
Capacitor
F-Cap.

BL BL BL BL BL
Vss

Q Q
V I
Pr
∆V =
∫I inj dt
Q = ∫ C (v)dv
C ox

V
V V V
1T + 1C 6Tr or 4Tr + 2Load 1T 1T + 1C (2T +2C)
Destructive Readout Non-destructive Readout Non-destructive Readout Destructive Readout
Refresh No refresh No refresh No-refresh
Volatile Volatile Non-volatile Non-volatile
8 F2 60~120 F2 4F2 6F2(12F2)

Kinam Kim
ELECTRONICS
 DRAM SRAM Flash FRAM
Mechanism Charging and dis- Switching of cross- Charging and dis- Dipole switching
for data storage charging of capacitor coupled inverters charging of floating of the ferro-cap.
gate
Access time < 100 ns < 50 ns ~ 100 ns < 100 ns
Write time < 100 ns < 50 ns ~ 10 µs < 100 ns
Write voltage <5V <5V > 10 V <5V
Erase time No need No need ~ ms No need
# of read/write cycles R&W:Infinite( >1015) R&W:Infinite( >1015) R: Infinite(1014~1015) R: >1010
W:~106 W: >1010
Data retention time 0 0 10 years ~ 10 years
Power ~ 100 mA ~ 100 mA ~ 10 mA ~ 10 mA
Standby current ~ mA ~ 0.1 µA~ mA ~ 10 µA ~ 10 µA

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ELECTRONICS
 2. Fundamentals of DRAM

2.1. DRAM Cell

2.2. Data storage in DRAM cell
- Memory cell capacitor
- Parasitic bit line capacitance
- Memory cell transistor
2.3. Sensing signal margin
- Charge sharing
- Sensing signal voltage
- Factors to affect sensing signal margin
- Minimum sensing signal margin
2.4. Considerations for DRAM
2.5. Key process technologies for DRAM
- FEOL(Isolation, transistor)
- MOL(memory cell process including cap.)
- BEOL(Metallization process)

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ELECTRONICS
 2.1. DRAM cell

WL
- Cell capacitance > 25 fF/cell
BL
- IDL < 1fA/cell capacitor
Cell transistor
- IOFF <1fA/cell transistor
Cell junction

Cell cap. - IJL < 10 fA/cell

- ION > few µA/cell

- ION/IOFF > 109

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ELECTRONICS
 2.2. Data storage in DRAM cell
Memory cell capacitor

Capacitance is approximated by parallel plate capacitor in spite of

its complicated 3D structures (Assuming SN & PN be metals).
ε
C =A
S d
Capacitor is charged and discharged instantly, thereby no limit of speed
for data storage (cell transistor conduction and parasitic limits).

The dielectric leakage current of capacitor strongly depends on electrodes

of capacitor, dielectric film and capacitor structure.

Only a few dielectric materials has been used as the dielectric materials
among many candidates.

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ELECTRONICS
 The candidates for the capacitor dielectric material

Dielectric Breakdown Field Max. charge capacity Currently used

constant( ε ) (MV/cm) ( Qmax = 2εEmax ) charge capacity

SiO2 3.9 ~10 55 fF/µm2

Si3N4 7~8 ~6 75 fF/µm2 7.67 fF/µm2

Al2O3 8~10 ~9 120 fF/µm2 N.A.
NbO2 ~11 ~5 95 fF/µm2 N.A.
ZrO2 ~16 ~5 170 fF/µm2 N.A.
Ta2O5 ~25 ~4.5 200 fF/µm2 10~12 fF/µm2
TiO2 ~80 ~1.5 180 fF/µm2 N.A.
BST ~250 ~0.3 155 fF/µm2 N.A.

Kinam Kim
ELECTRONICS
 3F
Layout
F

Top view

Vertical
h view

BOX OCS OCS+inner HSG

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ELECTRONICS
 Parasitic Bit Line Capacitance

Parasitic bit line capacitance (CBL) is originated from the two dimensional
array configuration where each bit line is commonly shared with many cells.

For 64Kb(=64x1024)

a) 256x256 b) 256x128x2
WL0 WL255 WL0 WL127 WL128
WL255

BL0 BL0 BL0

BL1 BL1 BL1

BL255 BL255 BL255

# of cell/ BL =256 # of cell/BL = 128

# of Sense-Amp = 256 # of Sense-Amp = 256x2=512

Kinam Kim
ELECTRONICS
 Parasitic bit line capacitance and its component

Total Parasitic bit line capacitance

PN CS

SN C BL = N * (∑ C BL , i ) where N is the number of cells/BL

CBL,BL CBL,PN Components of parasitic BL capacitance

BL
CBL,WL
CBL,SN Junction capacitance between BL and Sub = CBL,SUB
WL
STI Interlayer capacitance between BL and WL = CBL,WL
CBL,Sub
Interlayer capacitance between BL and SN = CBL,SN

Interlayer capacitance between BL and PN = CBL,PN

4F
Interlayer capacitance between BL and BL = CBL,BL

Kinam Kim
ELECTRONICS
 Cell Transistor (Array Transistor)
Cell transistor is to serve switch between data storage(cell capacitor)
and data line(bit line).

Cell transistor has the smallest dimensions (W & L = F, F is feature size).

WL 4F
unit cell

2F

3F
Active 1F

cap.area
In order to be perfect isolation for switch-off state, extremely small off-state
leakage current is only allowed, but for fast switching in on-state, high
current capacity is required. And no loss of signal across the switch must
be maintained.

Kinam Kim
ELECTRONICS
 Characteristics of memory cell transistor

logIds
Va
Ion
Vth

Vpp > Va + Vth

Ioff

0 Vpp Vgs

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ELECTRONICS
 2.3 Sensing signal margin
Charge sharing
Before switch(Transistor) on
WL
node1= vBL, node2 =vC
node1 node2
vC After switch on
vBL
BL CS node1= node2=v
CBL
vP
by charge conservation law

node2
CS (vC − vP ) + C BL vBL = (CS + C BL )v
node1
vBL vC
CS CBL
CBL CS ∴ v= (vC − vP ) + vBL
CS + CBL CS + CBL

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ELECTRONICS
 Bit line voltage level after charge sharing in case of data 1

C BL
1 CS
ν = (vcc − v P ) + v BL
1 + C BL 1 + C BL
H

CS CS

Bit line voltage level after charge sharing in case of data 0

C BL
1 CS
ν = ( −v P ) + v BL
1 + C BL 1 + C BL
L

CS CS
Typical ratio of CBL/CS is around 6~10.

Since CBL is much bigger than CS, the bit line voltages after charge sharing
are slightly changed from original level(precharge level) to either above or
below that level, depending on data 1 and data 0, respectively.

Kinam Kim
ELECTRONICS
 Sensing signal voltage

vS = 1/2(vH-vL)
v=vH when vC=Vcc (data1 storage)
v=vL when vC=0 (data0 storage)
CS C BL CS CBL
vH − vL = (VCC − vP ) + vBL − ( ( 0 − vP ) + vBL )
CS + CBL CS + CBL CS + CBL CS + CBL
CS
= VCC
CS + CBL
1 VCC
∴ vS =
2 1 + C BL
CS

- not dependent on plate node voltage(vP) and bit line precharge voltage(vBL)
- only dependent on supply voltage(Vcc) and ratio of BL cap./cell cap.(CBL/CS)

Kinam Kim
ELECTRONICS
 Voltage change of storage node and bit line before and after switch on

Before switch on After switch on

node2 node1 v
vC vBL=1/2 VCC
CS CBL CS CBL

Voltage at storage node Precharge voltage at BL Voltage after charge sharing

vC vBL v
vH(Vcc)
1 VCC
1/2Vcc vS =
2 1 + CBL
vS CS

vL(0)

Kinam Kim
ELECTRONICS
 Factors to decrease the sensing signal margin

- Supply voltage scaling

- Technology scaling

* Extremely difficult to achieve sufficient cell capacitance

* Difficult to reduce parasitic bit line capacitance
* Not scaleable mismatches of sense amplifier
(∆Vth, ∆β, ∆CBL, etc)
* Increased junction leakage current

- Signal losses due to a-particle and cosmic-ray

QS > QN + QC + QL where QS= stored charge, QL=charge loss due to leakage

QC=Critical charge due to a-particle, QN=noise charge

1 1
vS = C S VCC − (QN + QC + QL )
2(C S + C BL ) C S + C BL

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ELECTRONICS
 Components of Noise sources

Component of VN Noise expression Typical values When device

shrinks
1 Mismatch of SA 1 30~50 mV Slightly increase
vN ≈ CK / β (∆C / C + ∆β / β ) + ∆VTH
2
2 Bit line interference v N ≈ v S C DD /(C + C DD ) ~10 mV increase
3 Word line driving 2
mC DW v S ~10 mV Fast increase
vN ≈
noise (C DW + CW )(C DW + C BL )
4 Power line noise v N ≈ nδC DW /(C DW + C BL ) ~ < 10 mV increases
5 Other coupling noise ~ 10 mV increases
Total VN 70~90 mV increases

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ELECTRONICS
 Sense amplifier noise
VBL
Vth1 I1(t) ∆Vth=Vth1-Vth2
CBL1
β1 K ∆β=β1−β2
∆CBL=CBL1-CBL2
Vth2 I2(t) 1
β2 vN ≈ CK / β (∆C / C + ∆β / β ) + ∆Vth
VBL 2
CBL2

Bit line interference noise

vS
BL
CDD C BL
BL
vN
BL

BL
CBL

v N ≈ v S C DD /(C BL + C DD )

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ELECTRONICS
 Leakage current

I J = f (doping profile , defect )

Id

Vgs − Vth
I SUB = I O exp( )
S / 2.3
Gate

I d = AV 2 exp(−b / V )
Isub STI d
T
IGIDL I I GIDL ∝ f (t ox , n −, lov )
J
II
S I I = f ( S + 2dT − 2 X J , N A )

QL = ∫ ( I J + I SUB + I GIDL + I I )dt = I total Tref

QC
∴ I total <
Tref

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ELECTRONICS
 Minimum sensing signal voltage

1 1
vS = C S VCC − (QN + QC + QL )
2(C S + C BL ) C S + C BL
1 QC
vS = C S VCC − v N − v L −
2(C S + C BL ) C S + C BL
QC 10 fC
vS , min = v N + v L + = 70mV + 30mV + = 150mV
C S + C BL 200 fF

C S , min = 2(C S + C BL )v S , min / VCC = 2 x150mVx 200 fC / 2V = 30 fF / cell

∴ C BL = 200 fF − 30 fF = 170 fF

Kinam Kim
ELECTRONICS
 Considerations for DRAM cell

- Small cell size

close to 8F2
- High sensing signal margin
High cell capacitance
small parasitic capacitance bit line
- Good data retention time
Small junction leakage
Small transistor leakage currents
Small dielectric leakage currents
- High speed
Large current of cell transistor
Low parasitic resistance of WL & BL

Kinam Kim
ELECTRONICS
 2.3. Considerations for DRAM

- Good properties of memory cell

- Fast speed
- Small power consumption
- Small die size
- High reliability

Kinam Kim
ELECTRONICS
 Schematic diagram of configurations of DRAM chip
RAS VCC VSS
AC
τ RAC = τ RA + τ DEC + τ WL + τ S + τ I / O + τ DOT
RAS.B m

τ RA τ RA : add.buffer output from RAS

BL BL
τ DEC τ WL WL AA τ DEC : row add. decoding time
n
Row τ WL : word line delay
R RD
AB DEC τS τ S : sensing delay

Add. τ I / O : I/O line delay

SA
τ OUT τ OUT : data output
I/O τI /O
Col. Data
I/O
AB CD

C DEC

CAS.B

CAS

Kinam Kim
ELECTRONICS
 Key delay paths to determine chip speed
Word line delay
LWL
τ WL ∝ RWL CWL = RS ,WL CWL LWL
2
∝ LWL
2
WL
RD

BL BL
Charge sharing delay
WL RBL BL VCC −t
vS ( H , L) = ± (1 − e τ ) + 1 Vcc
SA 2(1 + C BL )
2
RDC CBL CS
CS
where
RS/D
RBC+RL τ = Rtotal C BL
RCH Rtotal = ( RBL + RDC + 2 RS / D + RCH + RBC + RL )

RS/D

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ELECTRONICS
 Sensing delay

VBL
2C BL (Vth − vS ) 2C BL
Vth1 I1(t) CBL1 τ SD ≈ = (1 − v S )
β1 K βVth vS βv S Vth
vS
I2(t)
Vth : Threshold voltage of S / A
Vth2
β2 Z
VBL
β = µ n Cox
L
CBL2

I/O line delay

vI/O vI/O
I/O Vcc −t
I/O vI / O = (1 − e τ ) + 1 Vcc
RI/O CI / O 2
2(1 + )
CI/O CI/O C BL
RBL Vcc −t
BL v I /O = − (1 − e τ ) + 1 Vcc
CI / O 2
2(1 + )
CBL C BL

where
RBL BL τ = ( RBL + RI / O )(C BL + C I / O ) ≈ ( RBL + RI / O )C I / O

CBL
Col.Select
Kinam Kim
ELECTRONICS
 Power consumption in DRAM chip

Power = switching power + DC power

Switching power = array switching power(PA) + periphery switching power(PP)
DC power = DC generator power(PD) + DC power from ratioed logics(PDL)

array switching power PA ∝ mC BL ∆VBL / t RC

periphery switching power PP ∝ CT , P ∆VP / t RC

DC generator power PD ∝ I DCVCC

DC power from ratioed logics PDC ∝ I DLVCC

Allowable maximum and minimum power will be limited by junction temperature

and battery back-up, respectively
TJ , max − Ta
Battery back up power ≤ P (= PA + PP + PD + PDL ) ≤
θ ja

Kinam Kim
ELECTRONICS
 Key factors to determine die size of DRAM

Die size of DRAM

Die(chip) size : AC AA SC N
AC = =
AE AE
Array size : AA
AA
Cell size : SC where AE : array effeciency ≡
AC

Density : N
In order for small die size, high array efficiency and small cell size
are required for the given technology.

For instance, 1Gb DRAM with 0.15 µm technology

cell size = 8x(0.15µm)2=0.18 µm2=0.18x10-8 cm2
Array size = 230x0.18x10-8cm2=1.933 cm2
If AE =60 %, 65 %, 70 %
Then, AC=3.222 cm2, 2.974cm2, 2.761cm2

Kinam Kim
ELECTRONICS
 High reliability

- High immunity against ESD (Electro-static discharge)

- High immunity against SER (Soft-error rate)
- High immunity to moisture penetration

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ELECTRONICS
 2.4 Key process technologies for DRAM

- FEOL process
- MOL process
- BEOL process

Kinam Kim
ELECTRONICS
 Vertical structure for typical COB stack cell

BEOL

ILD3
MEOL
BL BL
SN
BL cont. landing pad ILD2
cont.

ILD1
WL gate
FEOL
STI STI
P-well

P-sub

Kinam Kim
ELECTRONICS
 FEOL
: CMOS Front-end-of-line process (Isolation, well, transistor, landing pad)

Isolation

STI STI

Well

STI
P-well
N-well

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ELECTRONICS
 Transistor

WL gate
STI STI

cell landing pad

Cell landing pad

ILD1
WL gate
STI

Kinam Kim
ELECTRONICS
 protrusion
Considerations for STI Isolation
recess
- Sufficient isolation BV curvature d
- Small inverse narrow width effect
void or seam
- No-hump characteristics
- No defect generation W roundness

Key parameters for STI isolation

- Trench shape(width, depth, curvature, roundness)

- Filling material without void/seam
- Highly uniform CMP without recess nor protrusion

Kinam Kim
ELECTRONICS
Considerations for Well

- Latch-up immunity Core NMOS

Core PMOS cell array Peri-NMOS Peri-PMOS
- Well-to well isolation BV
- Noise separation Vcca Vbb Vcca Vccp

Key parameters for Well

P-well1
P-well2
- well-to-well space, well width N-well N-well
- well depth
- well doping density P-sub.

Kinam Kim
ELECTRONICS
Considerations for transistors

- High BVdss
gate
- Small S-factor engineering gate
- Small leakage currents Sl
- Low gate resistance
- High reliability(Hot carrier, oxide integrity) STI
Lg

Key parameters for transistor drain

channel structure
- Drain structure engineering
- Channel engineering
- Gate structure(gate material, Gox)
- Gate pitch and gate length(Lg)
Pitch = Lg +2Sl+ LS

Kinam Kim
ELECTRONICS
Consideration for cell pads

- No shortage between WL and landing pad

- No contact failure between landing pad and Si-sub.
- No bridge between landing pads
cell landing pad
Key parameters for cell pad

- Spacer width
- ILD1 filling without voids and seams WL
- Alignment tolerance S
- Contact hole size & A/R
- Contact cleaning

Kinam Kim
ELECTRONICS
 MEOL
: Memory cell capacitor (BL contact, BL, Storage contact, SN, PN)

ILD3
BL BL
SN
BL cont. landing pad ILD2
cont.

ILD1
WL gate

STI STI
P-well

P-sub

Kinam Kim
ELECTRONICS
 BL Contact

landing pad ILD2

ILD1
WL gate

STI STI
P-well

P-sub

Bit Line(BL)

landing pad ILD2

ILD1
WL gate

STI STI
P-well

P-sub

Kinam Kim
ELECTRONICS
 SN Contact Hole

landing pad ILD2

ILD1
WL gate

STI STI
P-well

P-sub
SN Contact Plug

landing pad ILD2

ILD1
WL gate

STI STI
P-well

P-sub

Kinam Kim
ELECTRONICS
 Capacitor

ILD3
BL BL
SN
BL cont. landing pad ILD2
cont.

ILD1
WL gate

STI STI
P-well

P-sub

Kinam Kim
ELECTRONICS
 δ

S h1 landing pad
Considerations for BL contact
WL
- Free from the NOT open
- No shortage between BL and WL STI
P-well
- Small contact resistance
- Small junction leakage P-sub

Key parameters for BL contact

h2 ILD2
- contact hole size(S<F) h3
- alignment tolerance(δ) ILD1
gate
- contact hole height
(h3>h2>h1) STI
- ohmic and barrier layers

Kinam Kim
ELECTRONICS
 t
Consideration for BL landing pad

- Low resistance WL
- Low parasitic capacitance
STI
- High thermal stability P-well

P-sub
Key parameters for BL

- material for BL
- thickness, width, of BL ILD2
- thickness of ohmic & Barrier layer
ILD1
barrier layer thickness gate

STI
Ohmic layer

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ELECTRONICS
 δ
S
h
Considerations for SN contact
landing pad
- No shortage to BL
- No shortage between SN and SN WL
- Free from not open
STI
P-well
Key parameters for SN contact
P-sub

- contact hole size (S<F)

- alignment tolerance (d) ILD
- contact hole height(h)
- ILD filling without seam and void
BL

WL

Kinam Kim
ELECTRONICS
Considerations for capacitor

- enough capacitance d
h
- small dielectric leakage current
- No shortage between SN and SN
l
Key parameters for capacitor BL
SN
BL cont. landing pad
cont.
- SN structure (dimension(h,l,w))
- dielectric material & thickness(d) WL
- PN material and thickness STI
- alignment tolerance P-well

P-sub

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ELECTRONICS
 BEOL
: Interconnection (Metal contact, Metal1, Via1, Metal2, Via2, Metal3)

ILD3
BL BL
SN
BL cont. landing pad ILD2
cont.

ILD1
WL gate

STI STI
P-well

P-sub

Kinam Kim
ELECTRONICS
 Metal contact and Metal 1

ILD3
BL BL
SN
BL cont. landing pad ILD2
cont.

ILD1
WL gate

STI STI
P-well

P-sub

Kinam Kim
ELECTRONICS
 Via1 and Metal2

ILD3
BL BL
SN
BL cont. landing pad ILD2
cont.

ILD1
WL gate

STI STI
P-well

P-sub

Kinam Kim
ELECTRONICS
 Via2 and Metal3

ILD3
BL BL
SN
BL cont. landing pad ILD2
cont.

ILD1
WL gate

STI STI
P-well

P-sub

Kinam Kim
ELECTRONICS
Considerations for metal contact and metal1

- small contact resistance W

- small contact leakage current h
- small wiring resistance h1
- high endurance for EM & SM ILD3 h3 h2
BL
Key parameters for metal contact and metal 1 ILD2

- contact hole dimension(h, s) S ILD1

gate
- global topology
STI
- ohmic and barrier layer
- metal dimension(h,w)

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ELECTRONICS
Considerations for via1 and metal2

- small via resistance

- small metal resistance
- immunity for EM & SM

Key parameters for via1 and metal2 ILD3

BL
- via dimension(h,s) ILD2
- via filling ILD1
- global and local topology gate
- metal dimension(h,w) STI

Kinam Kim
ELECTRONICS
 3. Challenges in DRAM

Technical challenges <- Extremely small cell size

Economic challenges <- Large chip size

Performance challenges <- Gap between CPU and DRAM

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ELECTRONICS
 Challenges, Issues and Solutions for future DRAMs

Challenges Issues to be solved Solutions

* Large Chip Size - Performance degradation Low resistance WL & BL metal

- Cost-effectiveness Smaller cell size(6F2,4F2)
(Low yield due to variation) Higher array efficiency

* Extremely - Resolution & Overlay Novel cell process (Full SAC)

Small Cell Size - Insufficient capacitance High dielectric capacitor
- Performance degradation Novel cell transistor
of Cell Transistor
(High IJ&IOFF, Low ION)

* Performance Gap - High band width New design

Innovative Interface
MDL

* Operation voltage - Non-scale cell Vth New device structure

New design

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ELECTRONICS
 Challenges in DRAM

Metal
M2 Interconnection
M3

(6)
Dielectrics
(1)
PN

SN M1 Capacitor

(4) BL (5) B/L

WL Gate
N- N- N- P + N+ N+

Isolation
(3)
(2)
DRAM Cell Periphery Circuit

Kinam Kim
ELECTRONICS
 Primary technical Issues when dimension shrinks

- Insufficient memory cell capacitance (3F2) 1)

- Large cell junction leakage current (~F-1) 2)

- Large variation of cell transistor Vth (~αF-1+βF-1) 3)

- Large parasitic resistance(~αF-2+βF-1+γ) 5)

- Small process window(~F)

- Global topology(~F-1) 6)

Kinam Kim
ELECTRONICS
 Issues in capacitor technology

- Difficulty to achieve sufficient cap.

- Difficult to scale down space between storage node

and storage node

- Small overlay tolerance between storage node

and storage node contact plug
Top size
layout Bottom size

3F
F

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ELECTRONICS
 Issues in memory cell transistor technology

- Large variation of Vth

- High junction leakage current

- Difficult to scale gate oxide

- Increased parasitic resistance(diffusion, contact)

WL
Gate

135nm
Storage
Active junction Storage SAC
junction PAD STI

Kinam Kim
ELECTRONICS
 Trend of Ids, ∆Vth of memory cell transistor

0.6 60

0.5
Vds = 2.1 V
40

Idsat [µ A/Cell]
∆ Vth [V]

0.4

20

0.3

0.2 0
0.25 0.18 0.15 0.13 0.25 0.18 0.15 0.13
Technology Generation [µ m] Technology Generation [µ m]

Kinam Kim
ELECTRONICS
 Storage node junction leakage trend

2.0

1.8
Normalized Cell IJ per cell

1.6
Gate
1.4
STI
1.2
IJ
1.0
- Substrate doping
0.8 - Mechanical stress from STI
0.6 - Crystal defects from silicon
etching
0.24 0.22 0.20 0.18 0.16 0.14 0.12 0.10

Technology generation (µm)

Kinam Kim
ELECTRONICS
High storage node junction leakage
1 100

Non-scaleable Vth of cell transistor

Substrate Doping NSUB(x1017cm-3)

---> Increased substrate doing Con. Cell Transistor

Gate Length of Cell Transistor(µm)

---> increased junction ε-field
---> increased e-field field assisted
tunneling with defects
---> increased junction leakage current 0.1 10

New Cell Transistor

When substrate doping >1018cm-3

---> abrupt junction leakage current

0.01 1
101 102 103 104 105
Memory Density(Mbits)

0.7 0.5 0.3 0.18 0.13 0.10 0.07

DRAM technology generation(µm)

Kinam Kim
ELECTRONICS
 Blanket implantation Local channel implantation

PR
STI STI
Storage junction
Storage junction

Substrate doping increase Substrate doping suppress

at storage junction at storage junction

Junction E-field increase Junction E-field relax

Junction leakage increase Junction leakage suppress

Kinam Kim
ELECTRONICS
 Issues in word line and bit line

- Increased resistance due to line width effect

- Difficult to gap-filling around WL and BL due to stack height

of WL and BL
active
WL
F

5F

Kinam Kim
ELECTRONICS
 Low resistance WL and BL technology
WL BL
100
256 Cell/Wordline
MS-WSix MS-WSix or W
90

80
Ω)
Wordline Resistance (kΩ

70 DCS-WSix DCS-WSix or W
60
DCS-WSi2
50
DCS-WSix+RTP W
40
DCS-WSi2
MS-WSi2
30 + RTP

20 MS-WSi2 TiSix W
+ RTP
10 CoSi2 NiSi
TiSi2 W
0
0.25 0.18 0.15 0.13 0.10
W/poly or NiSi
µm)
DRAM technology generation (µ

Kinam Kim
ELECTRONICS
 Issues in memory cell connection

- Limited to overlay and mis-alignment tolerance

- Narrow process window

- Increase parasitic resistance

top size
WL
F

Bottom size

Kinam Kim
ELECTRONICS
 300 200

Storage Contact & Bit-Line Size (nm)

Required Alignment Accuracy (nm)

250
150
Bit-Line

200

100
Storage
150 Contact

50
100

50 0
300 250 200 150 100

Minimum Feature Size (nm)

Kinam Kim
ELECTRONICS
 Memory cell connection technology

Partial SAC Full SAC Direction connection

Partial SAC

Full SAC

Kinam Kim
ELECTRONICS
 Issues in BEOL

- Limited to the DOF margin

- BEOL limit the performance

C R

Signal Delay τ = R •C

Power Consumption P ∝ C •V 2 • f

Cross-talk I ≈ C • dV
dt

IR drop ∆V ≈ I • R

Kinam Kim
ELECTRONICS
 BEOL technology

Conventional BEOL
Planarized BEOL
Con.BEOL by Full CMP Fully planarized BEOL
by Full CMP technology
2-Metal

3-Metal

3.00 ㎛ Multi-metal

Kinam Kim
ELECTRONICS
 4. Recent Studies for Future DRAM

Present Future

- Low Array Efficiency - Higher Array Efficiency

- Bigger Cell Size than 8F2 - Smaller Cell Size than 8F2

- Low Performance - High Performance

Kinam Kim
ELECTRONICS
 Novel array architecture for higher array efficiency

Conventional array Novel array

M2 (Al) M3 (Al)

M1(Al) M2(Al)
Global BL(M1) (Al)

BL(M0) (W) Local BL(M0) (W)

WL WL
STI STI

Single level BL Dual level BLs(Local & Global)

256 cells/BL 128 cells/BL + 8 LBL/GBL
Array efficiency ~ 65% Array efficiency > 75%

Kinam Kim
ELECTRONICS
 Fully processed HBL COB cell with 0.13 µm technology
(BL direction) (WL direction)
GBL

M3 (Al)

M2(Al)
Global BL(M1) (Al)
SN

SN LBL
pad
Local BL(M0) (W)
cell
pad
WL STI
STI

GBL(Al)
GBL(Al)

LBL(W)
LBL(W)

Kinam Kim
ELECTRONICS
 Figure of merits of 8F2,6F2,4F2 cell

Cell factor Configuration Capacitor Capacitor Cell transistor Cell transistor Chip size Issues Rank
area height area structure
8F2 COB Folded 3F2 1 F2 Planar 1 None(proven) 2
8F2 CUB Folded 2F2 1.34 F2 Planar 1 Cap. 3
8F2 COB with Folded 3F2 1 F2 Planar ~0.85 Extra BL 1
novel array
6F2 Open 2F2 1.34 F2 Planar 0.75~0.85 Cap. Noise, 5
Layout
6F2 (LOGF) Globally 2F2 1.34 F2 Planar 0.75~0.85 Extra BL, Cap. 4
folded, locally
open
4F2 Open F2 2 None Vertical 0.5~0.7 Vertical Tr. 6
Cap. Noise,
Layout

Kinam Kim
ELECTRONICS
Summary for Future Semiconductor Technology

- Down to 0.1 µm Technology Generation,

Current shrink technology will faces great challenges, However,
Shrink technology with modifications be the major driving force.
For the each generation technology, the proper technology migration
is very important for mass production.

- 0.1µm ~ 0.05 µm Technology generation,

CMOS scaling will play continuously, but Many innovations
are necessary in all aspects of semiconductor technology
from design to fabrication. These must be great challenges
but, at the same, great opportunities.

Kinam Kim
ELECTRONICS