Project Report ( Stage –I)

On

AUTOMATIC WASHING MACHINECONTROL SYSTEM

USING VERILOG HDL

Guided by

Prof..Dr.N.P.Futane

Submitted By

1.Maya Gore (19131025) 2. Dattatray Ambavane (12131046)

2022-2023

Department of Electronics and Telecommunication Engineering GOVT.

COLLEGE OF ENGINEERING AND RESERCH
AWASARI(KHURD), DIST- PUNE 412405 Academic Year:
2022-2023 (SEM-I)

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 GOVT. COLLEGE OF ENGG. AND RESEARCH
AWASARI (KHURD), TAL- AMBEGAON, DIST- PUNE 412405

CERTIFICATE
This is to certify that following students of B.E. (Electronics
and Telecommunication), have done bonafide work on the project
Stage-I entitled – “Automatic washing machine using Verilog
HDL”.
They are allowed to submit this work to the Savitribai Phule
Pune University towards partial fulfilment of the requirement for the
award of Bachelor of Engineering (Electronics and
Telecommunication) during the year 2022-2023.

Project Co-ordinator Head of Department

Dr. N.P.Futane Dr. Manoj S. Nagmode

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Acknowledgemen
I would like to express my thanks to my guide Teacher Dr.
N.P.Futane Sir and my Head of Department Dr.M.S.Nagmode Sir for
giving me a great opportunity to excel in my learning through this
project stage 1.
I have achieved a good amount of knowledge through this project
and the help that I got from my Course Teacher

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Abstract
❑ Demonstrate the capabilities and scope of Verilog HDL

❑ Implementing the control system of an automatic washing

machine.

❑ Accomplishes the above mentioned objective by implementing

the Control System of an automatic washing using the Finite State
Machine model

❑ The Control System generates the control signals to control the

overall operation of the washing machine.

❑ The Digital Design is simulated using Xilinx 14.1 ISE.

❑ The Verilog code for the Control System is then synthesized and
implemented on Spartan 6 FPGA development board to verify its
operation. This paper also demonstrates the reduction in
Development Cycle by the use of Hardware Description Languages
and FPGAs..

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Literature Review:

o A finite-state machine (FSM) : FSM is a mathematical model of

computation used to design both computer programs and sequential
logic circuits. There are two types: 1. Mealy machine 2. Moore
Machine o The washing machine control system : it will generates all
the control signals required for the operation of washing machine
and is designed using Verilog HDL. o The digital design : It is
implemented on Spartan 6 FPGA. Use of FPGAs facilitates the
reduction in development cycle. o Purpose : To synthesize HDL by
implementing Automatic Washing Machine Control System using
Chapter review and literature survey

Verilog HDL as an example. The proposed work not only reduced the
hardware development cycle but also greatly reduced development
costs. o SYSTEM DESIGN : Functionalities: 1. The wash machine has
the following states: idle, soak, wash, rinse, spin. 2. There are three
modes of operation i.e mode1, mode2 and mode3. 3. Different time
durations are allocated to each mode of operation. o The controller
is composed of two blocks: 1. a finite ‐ sate machine (FSM) block and
2.a timer block

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I. INTRODUCTION
A finite-state machine (FSM) or finite-state automaton (plural: automata),or
simply a state machine, is a mathematical model of
computation used to design both computer programs and sequential logic
circuits
. There are two types: Mealy machine & Moore
machine. Mealy machine is a finite state machine whose output values are
determined both by its current state and current inputs.
This is a deterministic finite state transducer: for each state and input, at most
one transition is possible. Moore machine, is a finite
state machine whose output values are determined solely by its current state. In
this paper, Mealy State Machine is used to
implement the control system of washing machine. The washing machine
control system generates all the control signals required
for the operation of washing machine and is designed using Verilog HDL. The
digital design is implemented on Spartan 6 FPGA.
Use of FPGAs facilitates the reduction in development cycle.

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System Development
1. Hardware:

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SYSTEM DESIGN

machine controller has the following functionalities:

1. The wash machine has the following The washing states: idle, soak, wash,
rinse, spin.

2. There are three modes of operation i.e mode1, mode2 and mode3.

3. Different time durations are allocated to each mode of operation.

The controller is composed of two blocks: a finite ‐ sate machine (FSM) block
and a timer block. The FSM block receives

some signals from the user, from the timer, and from other hardware parts such
as the door sensor. FSM block output control the

timer block and other hardware components of the washing machine. Table1
identifies the FSM input and output signals and their

functionality. The timer block generates the correct time periods required for
each cycle after it has been reset. The timer block is

composed of an up‐ counter and combinational logic to give the correct time
signals once certain count values have been

achieved. The timer values will be determined by the clock frequency being
used in the system.

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Table 1:

Alphabetical listing of input and output signals for the FSM (All signals are active high)

variables Inpuy\output Operations

CLK IN FORr the System Main Clock

Lid IN Machine door (lid) is open.

Coin IN art wash machine.

Cancel IN Cancels the washing process

mode1/mode2/mode3 IN Select Washing modes

IDLE_OP OUT Do not perform any process

ready_op OUT Machine is ready to start the process

soak_op OUT Soaking operation

WASH_OP OUT WASHING operation

rinse_op OUT RINSING OPERATION

COIN_RTRN
OUT ETURN THE COIN

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 WATER INTAKE
WATER INLET OUT

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SYSTEM FLOW CHART
system is described in the flow chart as shown in figure 1. The working of the washing
machine control

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THE FSM has 6 states as shown in figure 1.

State transitions take place according to the timing control signals generated by the
timer block and inputs given to a particular state. The processing in the next state
depends on outputs produced in the previous state. Different wash times are selected
by using the 3 different mode switches.

Figure 2 shows the State diagram of Washing Machine Control System which is
based on Mealy Machine. It has following states: IDLE, READY, SOAK, WASH,
RINSE, SPIN. Initially the FSM is in the idle state. Once the coin is inserted, the FSM
will go to the READY state. Once in ready state, any of the 3 modes for washing can
be selected. The selected mode decides the timing allocated to each state. If no mode
is selected, it will remain in the READY state itself. In case the process is cancelled
now, the coin is returned as the washing process has not yet started and the FSM
returns to the IDLE state. But once the washing process starts, cancellation results in
loss of the coin

State Diagram :

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Result and discussion

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Conclusion
For washing machine control system was designed in Verilog HDL and implemented on
Spartan 6 FPGA. The FSM designed has 6 states which perform different operations of a
washing machine. The digital design of washing machine control system using Verilog HDL
reduces the development cycle time.

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Future work to be done
In future, the number of states of the FSM can be increased for additional operations if required.
Actuators like DC motor, stepper motor and solenoid valves can be interfaced with the FPGA to
realize the real time operation and functioning of the washing machine control system.

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Referencies
1] Chen Xizhen, Chen Guangjian, Jia Jinling, Yu han, Zhou Tianpeng,”Design of Automatic
Washing Machine Based on Verilog HDL” International Conference on Electronics and
Optoelectronics, 29-31 July 2011, pp 38-40.

[2] P. Usha, C H .Karuna, “An Efficient Implementation of Automatic Washing Machine

Control System using Verilog”, IJSET, volume 2, issue 7, Sep-Oct 2014, pp 1575-1578.

[3] Thomas & Moorby, the Hardware Verilog Description Language [M], Beijing tsinghua
university press, 2001. 23‐36 industry press, 2003, 23(11):43‐45.

[5] YuanJunQuan, SunMinQi, CaoRui. Verilog HDL digital system design and its application
[M], concrete: Xian University of electronic science and technology press, 2002.

. [4] YangJimin YangJiBing, digital system design and Verilog HDL [M], Beijing: electronic

[6] Wangguan, Verilog HDL and digital circuit design [M], beijing mechanical industry press,
2005.9. [7] XiaYu wen, Verilog digital system design guide[M], beijing: aerospace university
press, 2003. 2‐10.

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