INTRODUCTION

VLSI (Very Large-Scale Integration) design is a critical process in the creation of integrated circuits
(ICs), involving millions or even billions of transistors on a single chip. The design process is broadly
divided into two key phases: front-end and back-end, each playing a distinct yet complementary role in
transforming high-level functional specifications into a physical chip.
At the start of my internship, I learned about the front-end designing of VLSI, i.e., the HDL (Hardware
Description Language) coding. The HDL uses two primary languages for hardware description: VHDL
and Verilog. Both are used to model electronic systems, particularly in the design of digital circuits. The
software used for front-end designing & coding is Xilinx Vivado . This software is primarily for
designing and implementing digital circuits , specifically targeting Xilinx FPGAs and SoCs . Vivado
includes tools for RTL design , simulation , and synthesis .
VHDL is a high-level language . It is basically a hardware description language used to model and
describe the behavior and structure of electronic systems, particularly digital circuits.
VHDL code typically follows this structure
Library declarations : collection of data is called library . In VHDL we are having a standard library
called IEEE , 1164 library functions are available. Entity declaration (describes the input/output ports
of the module) : it consists of entity name or file name . In entity name it represents how many numbers
of input and how many number of outputs ports are used. Architecture body (describes the internal
functionality) : It represents the type of statements . It represents the relation between input and output
. It consists of sequential statements and concurrent statements .
There are three models of writing a VHDL and Verilog code :
1. Data flow model : It is a gate level model where the relation between input and output is given
by keyword , no conditions or component statements & declarations .
2. Behavioural model : It is a functional level model where the relation between input and output
is given by conditional statements . It consists of concurrent statements .
3. Structural model : It is a gate level model . Two port declarations are done one for entity and
other for components . It is an example of sequential statements . It is a combination of main
program and sub-program .
As there were drawbacks in the VHDL programming language hence the Verilog HDL ( the advanced
HDL programming language ) was developed which was faster and easier to implement than VHDL
and it was more suitable for complex circuits . The Verilog HDL programming structure consists of only
one part , i.e. ‘module’ and ends with ‘end module ‘.Modules: In Verilog, designs are divided into
modules. Each module can represent a specific component (like an AND gate, flip-flop, or entire
systems). A module can have input and output ports defined. In Verilog we use key symbols instead of
keywords for gates . The Verilog HDL also has 3 types of models that is the dataflow , behavioural and
structural based on the model the structure of the program changes and it is different from the VHDL
models structure .
In the next phase of VLSI that is the back-end designing it focused on the physical implementation of
the circuits , This stage includes placing and routing the components of the chip , ensuring that the
design meets timing , power , and area constraints . The process involves translating the logical design
into a physical layout .Some important steps include floor planning , placement , clock tree synthesis ,
routing , desing rule checking , power and timing analysis These design steps make sure that the chip
can be successfully manufactured and will work as intended . The cadence design tool that I have used
for desining and simulating was Tanner EDA .
Project Title : Automatic Washing Machine control system using
Verilog HDL
Description : Various real life scenarios can be represented by Finite State Machines like control
system of an automatic washing machine . Assigning the main stages of the process like Close door, fill
water, add detergent, cycle, drain and spin various states that can be implemented as a State Machine.
Writing a test bench to observe the working of the machine. Using Xilinx ISE 14.7 to implement the
control system .

Purpose : To design a digital control system that automated the operation of a washing machine .
This project proposes to demonstrate the capabilities and scope of Verilog HDL by implementing the
control system of an automatic washing machine. This project accomplishes the above mentioned
objective by implementing the Control System of an automatic washing using the Finite State Machine
model. The Control System generates the control signals to control the overall operation of the washing
machine. The Digital Design is simulated using Xilinx 14.7 ISE.
The controller is composed of a finite ‐ sate machine (FSM) block and a counter. The FSM block
receives some signals from the user, from the timer, and from other hardware parts such as the door
sensor. FSM block output control the counter and other hardware components of the washing machine.
The counter generates the correct time periods required for each cycle after it has been reset. The timer
block is composed of an up‐counter and combinational logic to give the correct time signals once certain
count values have been achieved. The timer values will be determined by the clock frequency being
used in the system.

Working : The working of the washing machine control system is described in the flow chart as
shown in figure . System flow chart of Washing Machine Controller The FSM has 7 states as shown in
figure. State transitions take place according to the timing control signals generated by the counter and
inputs given to a particular state. The processing in the next state depends on outputs produced in the
previous state .State transitions take place according to the timing control signals generated by the
counter and inputs given to a particular state. The processing in the next state depends on outputs
produced in the previous state. This automatic washing machine is generally modelled as a Moore
machine . so it works on only present input . Below is the state diagram .
PROGRAM:
`timescale 10ns / 1ps
/////////////////////////////////
/////////////////////////////////
/////////////////////////////////
module automatic_washing_machine(clk, reset, door_close, start, filled, detergent_added,
cycle_timeout, drained, spin_timeout, door_lock, motor_on, fill_value_on, drain_value_on, done,
soap_wash, water_wash);
input clk, reset, door_close, start, filled, detergent_added, cycle_timeout, drained, spin_timeout;
output reg door_lock, motor_on, fill_value_on, drain_value_on, done, soap_wash, water_wash;
//defining the states
parameter check_door = 3'b000;
parameter fill_water = 3'b001;
parameter add_detergent = 3'b010;
parameter cycle = 3'b011;
parameter drain_water = 3'b100;
parameter spin = 3'b101;
reg[2:0] current_state, next_state;
always@(current_state or start or door_close or filled or detergent_added or drained or cycle_timeout
or spin_timeout)
begin
case(current_state)
check_door:
if(start==1 && door_close==1)
begin
next_state = fill_water;
motor_on = 0;
fill_value_on = 0;
drain_value_on = 0;
door_lock = 1;
soap_wash = 0;
water_wash = 0;
done = 0;
end
else
begin
next_state = current_state;
motor_on = 0;
fill_value_on = 0;
drain_value_on = 0;
door_lock = 0;
soap_wash = 0;
water_wash = 0;
done = 0;
end
fill_water:
if (filled==1)
begin
if(soap_wash == 0)
begin
next_state = add_detergent;
motor_on = 0;
fill_value_on = 0;
drain_value_on = 0;
door_lock = 1;
soap_wash = 1;
water_wash = 0;
done = 0;
end
else
begin
next_state = cycle;
motor_on = 0;
fill_value_on = 0;
drain_value_on = 0;
 door_lock = 1;
soap_wash = 1;
water_wash = 1;
done = 0;
end
end
else
begin
next_state = current_state;
motor_on = 0;
fill_value_on = 1;
drain_value_on = 0;
door_lock = 1;
done = 0;
end
add_detergent:
if(detergent_added==1)
begin
next_state = cycle;
motor_on = 0;
fill_value_on = 0;
drain_value_on = 0;
door_lock = 1;
soap_wash = 1;
done = 0;
end
else
begin
next_state = current_state;
motor_on = 0;
fill_value_on = 0;
drain_value_on = 0;
 door_lock = 1;
soap_wash = 1;
water_wash = 0;
done = 0;
end
cycle:
if(cycle_timeout == 1)
begin
next_state = drain_water;
motor_on = 0;
fill_value_on = 0;
drain_value_on = 0;
door_lock = 1;
//soap_wash = 1;
done = 0;
end
else
begin
next_state = current_state;
motor_on = 1;
fill_value_on = 0;
drain_value_on = 0;
door_lock = 1;
//soap_wash = 1;
done = 0;
end
drain_water:
if(drained==1)
begin
if(water_wash==0)
begin
next_state = fill_water;
 motor_on = 0;
fill_value_on = 0;
drain_value_on = 0;
door_lock = 1;
soap_wash = 1;
//water_wash = 1;
done = 0;
end
else
begin
next_state = spin;
motor_on = 0;
fill_value_on = 0;
drain_value_on = 0;
door_lock = 1;
soap_wash = 1;
water_wash = 1;
done = 0;
end
end
else
begin
next_state = current_state;
motor_on = 0;
fill_value_on = 0;
drain_value_on = 1;
door_lock = 1;
soap_wash = 1;
//water_wash = 1;
done = 0;
end
spin:
if(spin_timeout==1)
begin
next_state = door_close;
motor_on = 0;
fill_value_on = 0;
drain_value_on = 0;
door_lock = 1;
soap_wash = 1;
water_wash = 1;
done = 1;
end
else
begin
next_state = current_state;
motor_on = 0;
fill_value_on = 0;
drain_value_on = 1;
door_lock = 1;
soap_wash = 1;
water_wash = 1;
done = 0;
end
default:
next_state = check_door;

endcase
end
always@(posedge clk or negedge reset)
begin
if(reset)
begin
current_state<=3'b000;
 end
else
begin
current_state<=next_state;
end
end

endmodule

module new_test();
reg clk, reset, door_close, start, filled, detergent_added, cycle_timeout, drained, spin_timeout;
wire door_lock, motor_on, fill_value_on, drain_value_on, done, soap_wash, water_wash;

automatic_washing_machine machine1(clk, reset, door_close, start, filled, detergent_added,

cycle_timeout, drained, spin_timeout, door_lock, motor_on, fill_value_on, drain_value_on, done,
soap_wash, water_wash );
initial
begin
clk = 0;
reset = 1;
start = 0;
door_close = 0;
filled = 0;
drained = 0;
detergent_added = 0;
cycle_timeout = 0;
spin_timeout = 0;

#5 reset=0;
#5 start=1;door_close=1;
#10 filled=1;
#10 detergent_added=1;
 //filled=0;
#10 cycle_timeout=1;
//detergent_added=0;
#10 drained=1;
//cycle_timeout=0;
#10 spin_timeout=1;
//drained=0;

/*

#0 reset = 0;
#2 start = 1;
#4 door_close = 1;
#3 filled = 1;
#3 detergent_added = 1;
#2 cycle_timeout = 1;
#2 drained = 1;
#3 spin_timeout = 1;
*/
end

always
begin
#5 clk = ~clk;
end
initial
begin
$monitor("Time=%d, Clock=%b, Reset=%b, start=%b, door_close=%b, filled=%b,
detergent_added=%b, cycle_timeout=%b, drained=%b, spin_timeout=%b, door_lock=%b,
motor_on=%b, fill_valve_on=%b, drain_valve_on=%b, soap_wash=%b, water_wash=%b,
done=%b",$time, clk, reset, start, door_close, filled, detergent_added, cycle_timeout, drained,
spin_timeout, door_lock, motor_on, fill_value_on, drain_value_on, soap_wash, water_wash, done);
end
endmodule
OUTPUT: