CS 3352-DP&CO UNIT I

UNIT I COMBINATIONAL LOGIC

Combinational Circuits – Karnaugh Map - Analysis and Design Procedures – Binary Adder – Subtractor –
Decimal Adder - Magnitude Comparator – Decoder – Encoder – Multiplexers - Demultiplexers
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1. Combinational Logic
The digital system consists of two types of circuits, namely
(i) Combinational circuits
(ii) Sequential circuits
Combinational Circuits
1. A combinational circuit consists of logic gates whose outputs at any time
are determined from only the present combination of inputs.
2. For n input variables, there are 2n possible combinations
of the binary inputs.
3. For each possible combination, there is one and only one
possible output combination.
4. A combinational logic circuit can be described by m Boolean functions and each output can be expressed in
terms of n input variables.

1. Analysis Procedure
1. The analysis of a combinational circuit requires that we determine the function that the circuit implements.
2. The analysis can be performed manually by finding the Boolean functions or truth table or by using a
computer simulation program.
3. The first step in the analysis is to make sure that the given circuit is combinational and not sequential.
4. The diagram of a combinational circuit has logic gates with no feedback paths or memory elements.
5. To obtain the output Boolean functions from a logic diagram,
i) Label all gate outputs that are a function of input variables with arbitrary symbols. Determine the
Boolean functions for each gate output.
ii) Label the gates that are a function of input variables and previously labeled gateswith other arbitrary
symbols. Find the Boolean functions for these gates.
iii) Repeat the process outlined in step 2 until the outputs of the circuit are obtained.
iv) By repeated substitution of previously defined functions, obtain the outputBoolean functions in terms
of input variables.
For analysis, let us consider the logic diagram:

The circuit has three binary inputs— A, B, and C and two binary outputs— F1 and F2.
The Boolean functions for these two outputs are
F1 = T3 + T2
F2 =AB +AC+BC
T1=A+B+C
T2=ABC
T3= F2 ‗T1
To obtain F1 as a function of A,B,C, we form a series of substitutions as follows
F1 = T3 + T2 = F2 ‗T1 + T2
= (AB +AC+BC)‘ (A+B+C) + ABC
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=(A‘+B‘)(A‘+C‘)(B‘+C‘)(A+B+C)+ABC
=(A‘+B‘C‘)(AB‘+AC‘+BC‘+B‘C) +ABC
=A‘BC‘+A‘B‘C

The derivation of the truth table for a circuit is a straightforward process once the output Boolean
functions are known.
1. Determine the number of input variables in the circuit. For n inputs, form the 2n possible input
combinations and list the binary numbers from 0 to (2n - 1) in a table.
2. Label the outputs of selected gates with arbitrary symbols.
3. Obtain the truth table for the outputs of those gates which are a function of the input variables only.
4. Proceed to obtain the truth table for the outputs of those gates which are a function of previously defined
values until the columns for all outputs are determined
Truth Table for the Logic Diagram of Fig

2. Design Procedure
The procedure involves the following steps:
1. From the specifications of the circuit, determine the required number of inputs and outputs and assign a
symbol to each.
2. Derive the truth table that defines the required relationship between inputs and outputs.
3. Obtain the simplified Boolean functions for each output as a function of the input variables.
4. Draw the logic diagram from the simplified expression.

Binary adder –Subtractor

Simple addition consists of four possible elementary operations:
0+0 = sum 0, carry 0
0+1=sum 1, carry 0
1+0=sum 1 ,carry 0
1+1=sum 0 , carry 1.
First three operations produce a sum of one digit.
When both augend and addend bits are equal to 1, the binary sum consists of two digits. The higher significant bit
of this result is called a carry.

2.1. Half Adder

1. A combinational circuit that performs the addition of two bits is called a half adder.
2. It has two binary inputs (augends, addend) and two binary outputs (sum & Carry).
3. Assign symbols x and y to the two inputs and S and C to the outputs. 4.Truth Table
Inputs Outputs
x y S C
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
Block Diagram

5. The simplified sum-of-products expressions obtained from the truth table are
S = x‘y + xy‘
C = xy
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6. Logic Diagram of the half adder

2.2. Full adder

1. A full adder is a combinational circuit that performs the arithmetic sum of three bits (two significant bits
and a previous carry).
2. It consists of three inputs and two outputs.
3. Two of the input variables, denoted by x and y, represent the two significant bits to be added.
The third input, z, represents the carry from the previous lower significant position.

Block Diagram

4. As there are three input variables, eight different input combinations are possible.
5. The truth table of the full adder is listed in Table

Truth Table k-map for S k-map for C

Inputs Outputs
x y z S C
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

6. The simplified Boolean expressions of the outputs are

S = x′y’z + x’yz ’+xy’z’+ xyz and
C = xy+yz+xz.

7. The logic diagram for the above functions is shown in Figure

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It can also be implemented with two half adders and one OR gate.

In fig The S output from the second half adder is the exclusive-OR of z and the output of the first half adder,
giving S = z (x y)
= z‘(xy‘ + x‘y) + z (xy‘ + x‘y)‘
= z‘(xy‘ + x‘y) + z (xy + x‘y‘)
= xy‘z‘ + x‘yz‘ + xyz + x‘y‘z
The carry output is
C = z (xy‘ + x‘y) + xy = xy‘z + x‘yz + xy

2.3. Design of Half-subtractor

1. A half-subtractor is a combinational circuit that subtracts two bits and produces their difference.
2. It also has an output to specify if a 1 has been borrowed (Borrow).
3. Let the input variables minuend and subtrahend be designated as X and Y respectively, and output
functions be designated as D for difference and B for borrow.
4. The truth table of the functions is as follows.
Truth Table
5. By considering the minterms of the truth table, the Boolean expressions of
Inputs Outputs
the outputs D and B functions can be written as
x y D B
D = x′y + xy′ and
0 0 0 0
B = x′y.
0 1 1 1
1 0 1 0
1 1 0 0

6. Logic diagram of half subtrator

2.4. Full-Subtractor
1. A full-subtractor has three inputs and two outputs.
2. x,y and z are the inputs to be subtracted in which z represents borrow from the next stage.
D and B are the outputs.
3. Truth table for a full- subtractor

Inputs Outputs
x y z D S
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
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1 1 0 0 0
1 1 1 1 1

4. Karnaugh maps are prepared to derive simplified Boolean expressions of D and B

yz yz
x 00 01 11 10 x 00 01 11 10

0
1 1 1 1 1
0
1 1 1
1 1

K maps for D & B

5. The simplified Boolean expressions of the outputs are

D=x’y’z+x’yz’+xy’z’+xyz & B=x’y+x’z+yz
= z (x y)
6. Simplified expressions for D & B are implemented using basic gates.

It can also be implemented with two half subtractors and one OR gate.
The boolean expression for difference and borrow can be written as
D = x'y'z + x'yz' + xy'z' + xyz
= (x'y' + xy)z + (x'y + xy')z'
= (x y)'z+ (x y)z'
=x y z
B = x'.y + x'.z+ y.z

Implementation of full subtractor using half subtrator

2.5. Binary adder (binary parallel adder/Ripple carry adder)

1. A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers.
2. It can be constructed with full adders connected in cascade, with the output carry from each full adder
connected to the input carry of the next full adder in the chain.
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3. An n bit adder requires n full adder.
4. The carries are connected in a chain through the full adders. The input carry to the adder is C0, and it
ripples through the full adders to the output carry C4.
5. All the carries must be generated for the correct sum bits to appear at the outputs. Therefore, the sum and
carry outputs of any stage cannot be produced until the input carry occurs. This delay is known as carry
propagation delay.

Carry Propagation
1. In parallel adder all the bits of the augend and addend are available for computation at the same time.
2. The signal must propagate through the gates before the correct output sum is available in the output
terminals. The total propagation time is equal to the propagation delay of a typical gate, times the number
of gate levels in the circuit.
3. The longest propagation delay time in an adder is the time it takes the carry to propagate through the full
adders. Since each bit of the sum output depends on the value of the input carry.
4. There are several techniques for the reduction of carry propagation delay time. However, the most widely
used method employs the principle of look ahead carry generation

Full adder with P and G shown

Pi = Ai Bi
Gi = AiBi
The output sum and carry can respectively be expressed as
S i = P i Ci
Ci+1 = Gi + PiCi
Gi is called a carry generate, and it produces a carry of 1 when both Ai and Bi are 1, regardless of the input carry
Ci.
Pi is called a carry propagate-it determines whether a carry in stage i will propagate into stage i + 1
C0 = input carry
C1 =G0+P0C0
C2 = G1 + P1C1 = G1 + P1(G0 + P0C0) = G1 + P1G0 + P1P0C0
C3 = G2 + P2C2 = G2 + P2G1 + P2P1G0 +P2P1P0C0
This circuit can add in less time because C3 does not have to wait for C2 and C1 to propagate.
C3 is propagated at the same time as C1 & C2.
The three Boolean functions for C1,C2 & C3 are implemented in the carry lookahead generator as shown in figure.

Four bit adder with carry look ahead

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2.6.4 bit adder – subtractor

When the mode input (M) is at a low logic, i.e. '0', the circuit act as an adder and when the mode input is
at a high logic, i.e. '1', the circuit act as a subtractor.
The exclusive-OR gate connected in series receives input M and one of the inputs B.
When M is at a low logic, we have B Ex-or 0 = B.
The full-adders receive the value of B, the input carry is 0, and the circuit performs A plus B.
When M is at a high logic, we have B Ex-or 1 = B' and C0 = 1.
The B inputs are complemented, and a 1 is added through the input carry. The circuit performs the operation A
plus the 2's complement of B.
An overflow condition can be detected by observing the carry into the sign bit position and the carry out of the
sign bit position. If these two carries are not equal, an overflow has occurred
Let the carry out of the full adder adding the least significant bit be called c0. Then, the carry out of the
full adder adding the next least significant bit is c1. Thus, the carry out of the full adder adding the most
significant bits is c(k - 1). This assumes that we are adding two k bit numbers.
We can write the formula as: V = c(k-1) XOR c(k-2)
This is effectively XORing the carry-in and the carry-out of the leftmost full adder.
The XOR of the carry-in and carry-out differ if there's either a 1 being carried in, and a 0 being carried out, or if
there's a 0 being carried in, and a 1 being carried out.
Case 1: 0 carried in, and 1 carried out If a 0 is carried, then the only way that 1 can be carried out is if x(k-1) = 1
and y(k-1) = 1. That way, the sum is 0, and the carry out is 1. This is the case when you add two negative
numbers, but the result is non-negative.
Case 1: 1 carried in, and 0 carried out The only way 0 can be carried out if there's a 1 carried in is if x(k-1) = 0
and y(k-1) = 0. In that case, 0 is carried out, and the sum is 1. This is the case when you add two non-negative
numbers and get a negative result.

2.7. Decimal Adder

A decimal adder requires a minimum of nine inputs and five outputs.
There is wide variety of possible decimal adder circuits, depending upon the code used to represent the decimal
digits.
BCD adder
1. A BCD adder is a circuit that adds two BCD digits with an input carry from the previous stage and
produces a sum digit also a BCD.
2. Since each input digit does not exceed 9, the output sum cannot be greater than 9+9+1 =19.
3. Suppose we apply two BCD digits to a four-bit binary adder.
The adder will form the sum in binary and produce a result that ranges from 0 through 19.
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These binary numbers are listed in Table and are labeled by symbols K, Z8, Z4, Z2, and Z1.
K is the carry.
The output sum of two decimal digits must be represented in BCD and should appear in the form listed in
the columns under ―BCD Sum.‖
4. From the contents of the table, when the
Binary-sum is equal to or less than 1001, the
corresponding BCD number is identical. No
conversion is needed.
5. When the binary sum is greater than 1001, we
obtain an invalid BCD representation. The addition
of binary 6 (0110) to the binary sum converts it to
the correct BCD representation and also produces
an output carry as required.
6. The logic circuit that detects the necessary
Correction can be derived from the entries in
the table. It is obvious that a correction is
needed when the binary sum has an output
carry K = 1.
The other six combinations from 1010 through
1111 that need a correction have a 1 in position
Z8.
8. To distinguish them from binary 1000 and
1001, which also have a 1 in position Z8,
we specify further that either Z4 or Z2 must
have a‘1‘.
The condition for a correction and an output carry can
be expressed by the Boolean function
C = K + Z8Z4 + Z8Z2
When C = 1, it is necessary to add 0110 to the binary
sum and provide an output carry for the next stage.

9. To implement BCD adder we require

4 bit binary adder for initial addition - The two decimal digits, together with the input carry, are first added
in the top four-bit adder to produce the binary sum
Logic circuit to detect sum greater than 9
One more four bit adder to add (0010)2 to the sum. if the output carry is equal is 1.

2.8. Serial Adder:

1. In the serial adder, the addition operation is done by
bit-by-bit.
2. The serial adder requires simple circuit than a parallel
adder.
The operation of the serial adder is as follows:
i) Two shift registers A and B are used to store the
numbers to be added serially.
ii) A single full adder is used, to add one pair of bits at a
time, along with the carry.
iii) The D-flip flop is used to store the carry output of the
full adder, so that it can be added to the next significant
position of the numbers in the registers.
iv) The contents of the shift registers shift from left to
right and their outputs starting from A0 and B0 are fed into a single full adder along with the output of the
D-flip flop upon application of each clock pulse.
v) The sum output of the full adder is fed to MSB bit (S3) of the sum register.
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vi) For each succeeding clock pulse, the contents of the both shift registers are shifted once to the right and
new carry bit are transferred to sum register and D-flip flop respectively.
vii) This process continues until all the pairs of bits are added.

2.9. Serial Subtractor:

1. A serial subtractor can be obtained by converting the full adder by feeding the output B‘ into the full adder
instead of B.
2. Intially setting the D flip flop to 1 instead of 0.
3. Difference register instead of sum register.
The operation of the serial subtractor is as follows:
i) 2‘s complement subtraction method is used in the
serial subtractor.
ii) The subtrahend is stored in the ‗B‘ register and the
minuend stored in ‗A‘ register.
iii) The subtrahend is converted into 1‘s complement
number by adding a NOT gate with B register and get
2‘s complement number by adding 1 through Cin.
iv) The 2‘s complement of subtrahend is added to the
minuend by the full adder and the result is stored in
the difference register.
Comparison Between Serial And Parallel Adder:
Serial adder Parallel adder
1) Slower 1) Faster
2) It uses shift registers 2) It uses registers with parallel load capacity
3) It requires one full adder circuit. 3) No. of full adder circuit is equal to no. of
bits in binary adder.
4) It is sequential circuit. 4)It is a combinational circuit
5) Time required for addition depends on 5)Time required does not depend on the
number of bits.
number of bits

3. Magnitude Comparator
A magnitude comparator is a combinational circuit that compares two numbers, A and B, and determines their
relative magnitudes.
The outcome of the comparison is specified by three binary variables that indicate whether A>B ,A=B ,A<B.
Consider two numbers A & B with four digits each.
A=A3A2A1A0
B=B3B2B1B0
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The two numbers are equal if all pairs of significant digit are equal i.e., if A3=B3 and A2=B2 and A1=B1 and
A0=B0
The equality relation of each pair of bits can be expressed logically with an equivalence function
xi =AiBi+Ai‘Bi‘ i=0,1,2,3

where xi=1 only if the pair of bits in position i are equal.

The binary variable (A=B) is 1 if the input numbers A & B are equal. For the equality condition to exist, all xi
variables must be equal to 1.This indicates an AND operation of all variables
(A=B) = x3 x2 x1 x0
To determine whether A is greater or less than B, we inspect the relative magnitudes of pairs of significant digits,
starting from the most significant position.
If the two digits of a pair are equal, we compare the next lower significant pair of digits.
The comparison continues until a pair of unequal digits is reached.
If the corresponding digit of A is 1 and that of B is 0, we conclude that A > B.
If the corresponding digit of A is 0 and that of B is 1, we have A < B.
The sequential comparison can be expressed logically by the two Boolean functions
(A > B) = A3B3‘ + x3 A 2B2‘ + x3x2A1B1‘ + x3x2x1A0B0‘
(A < B) = A3’B3 + x3A2‘B2 + x3x2A1’B1 + x3x2x1A0B0’
Draw the logic diagram.

4. Multiplexer (data selector)

1. A multiplexer is a combinational circuit that selects binary information from one of many input lines and
directs it to a single output line.
2. The selection of a particular input line is controlled by a set of selection lines.
3. Normally, there are 2n input lines and n selection lines whose bit combinations determine which input is to be
selected.
Four-to-one line Multiplexer:
1. Each of the four inputs, I0 through I3, is applied to one input
of an AND gate.
2. Selection lines S1 and S0 are decoded to select a particular
AND gate.
3. The outputs of the AND gates are applied to a single
OR gate that provides the one-line output.

Operation of the circuit:

Consider the case when S1S0 = 10.
The AND gate associated with input I2 has two of its inputs equal to 1
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and the third input connected to I2.
The other three AND gates have at least one input equal to 0, which makes their outputs equal to 0.
The output of the OR gate is now equal to the value of I2, providing a path from the selected input to the output.

Procedure to Implement Boolean function using multiplexer:

1. Any Boolean function of n variables can be implemented with a multiplexer with n - 1 selection inputs
and 2n-1 data inputs.
2. Then last n - 1 variables in the table are applied to the selection inputs of the multiplexer.
3. For each combination of the selection variables, we evaluate the output as a function of the First variable.
This function can be 0, 1, the variable, or the complement of the variable.
These values are then applied to the data inputs in the proper order.

Example 4.1. Implement the given function using Multiplexer F (A, B, C) = Σ (0, 2, 6, 7)
Step 1: Select the multiplexer. Here Boolean expression has 3 variables, thus we require 22=4:1 MUX.
Variable B& C –Selection lines & A- input to the MUX.
Step 2: Derive inputs for MUX using implementation table

Implementation table
Implementation table is the list of the inputs of the MUX and under them list of all the minterms in two rows.
Encircle the minterms which is included in the given function
If the two minterms in a column are not circled, apply 0 to the corresponding multiplexer input.
If the two minterms are circled, apply 1 to the corresponding multiplexer input.
If the bottom minterm is circled and top is not circled, apply true form of the variable to the corresponding
multiplexer input.
If the top minterm is circled and bottom is not circled, apply complement of the variable to the corresponding
multiplexer input.
Here in I0 column top minterm alone is circled , so apply C‘ to I0
in I1 column top minterms alone is circled, so apply C‘ to I1
in I2 column both minterms are not circled, so apply 0 to I2
in I3 column both minterms are circled, so apply C to I3
Alternate method
Step 1: select the multiplexer same as above said.
Step 2: Find the truth table for the given Boolean expression

Inputs output
A B C F
0 0 0 1
F= C‘
0 0 1 0
0 1 0 1
F= C‘
0 1 1 0
1 0 0 0 F= 0
1 0 1 0
1 1 0 1 F= 1
1 1 1 1

Step 3: choose variables A & B as selection lines .

From the truth table when AB=00 then F=C‘,
AB=01 then F=C‘
AB=10 then F=0 &
AB=11 then F=1
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Example 4.2. Implement a full-adder circuit with Multiplexer

Inputs output
From the truth table when xy=00 then S=z, & C=0
x y z S C
xy=01 then S=z‘ C=z
0 0 0 0 0
xy=10 then S=z‘ C= z
0 0 1 1 0
0 1 0 1 0 xy=11 then S=z C= 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

Example 4.3. implement the following Boolean function with an 8 to 1 line multiplexer
F(A,B,C,D) = Σ (2,4,6,9,10,11,15)
Given Boolean expression is a function of 4 variable(A,B,C,D) , 3 variable(A,B,C) can be used as selection lines
i.e 3 selection lines . evaluate the output as a function of D.

5.Demultiplexer
DEMULTIPLEXERS: (abbreviated as demux)
The demultiplexer performs the exact opposite function of Multiplexer.
A Demultiplexer is a circuit that receives information on a single line and transmits this information on one
of 2 n possible output lines.
The selection of specific output line is controlled by the values of n selection lines.

Selection output
inputs
S1 S0 Y3 Y2 Y1 Y0
0 0 0 0 0 1
0 1 0 0 1 0
1 0 0 1 0 0
1 1 1 0 0 0

Block diagram Truth table

Y3=S1S0 I
Y2=S1S0‘I
Y1=S1‘S0 I
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Y0 =S1‘S0‘I
Logic diagram

6. Decoders:
A decoder is a combinational circuit that converts binary information from n input lines to a maximum of 2n
unique output lines.
If the n -bit coded information has unused combinations, the decoder may have fewer than 2n outputs.

6.1. 2 to 4 line decoder

1. Two inputs are decoded into 4 outputs
2. Each output represents one of the minterms of the two input variables.

Y3  I1 I0 Y2  I1 I0

Y1  I1 I0 Y0  I1 I0

Block Diagram

Truth table

Y3

Y2

Y1

Y0

I1
I0
Logic Diagram
6.2. 3to-8 line decoder:
1. The three inputs are decoded into eight outputs,
2. Each output represents one of the minterms of the three input variables.
3. A particular application of this decoder is Binary-to-octal conversion.
4. The input variables represent a binary number, and the outputs represent the eight digits of a number
in the octal number system.
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5. For each possible input combination, there are

seven outputs that are equal to 0 and only one
that is equal to 1.
6. The output whose value is equal to 1 represents the
minterm equivalent of the binary number currently
available in the input lines.

Combinational logic implementation

Any Boolean expression expressed in SOP, can be implemented using a decoder and an external OR gate.
Since decoder provides the 2n minterms of n input variable.

Example . Implement full adder circuit with a decoder.

Obtain the truth table of full adder (Page no 17).
From the truth table of the full adder, we obtain the functions for the combinational circuit in sum-of-minterms
form: S(x, y, z) =Σ (1, 2, 4, 7)
C(x, y, z) = Σ (3, 5, 6, 7)
Since there are three inputs and a total of eight minterms, we need a three-to-eight-line Decoder.

The OR gate for output S forms the logical sum of minterms 1,2, 4, and 7.
The OR gates for output C forms the logical sum of minterms 3, 5, 6, and 7.

Example .Construct 4-to-16 line decoder using two 3-to-8 line decoder
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1. Decoders with enable inputs can be connected together to form a larger decoder circuit.
2. Two 3-to-8-line decoders with enable inputs connected to form a 4-to-16-line decoder.
3. When w =0, the top decoder is enabled and the other is disabled.
4. The bottom decoder outputs are all 0‘s, and the top eight outputs generate minterms 0000 to 0111.
5. When w = 1, bottom decoder is enabled.
6. The bottom decoder outputs generate minterms 1000 to 1111, while the outputs of the top decoder are all
0‘s.

Example :Implementation of 4 to 16 Decoder using 2 to 4 Decoders

6.3. BCD TO SEVEN SEGMENT DISPLAY DECODER:

 A seven segment display is normally used for displaying any one of the decimal digits from 0 to 9.
 A BCD to seven segment decoder accepts decimal digits in BCD and generates the corresponding seven
segment code.

Truth Table:
Decimal Inputs Outputs
Digits A B C D a b c d e f g
0 0 0 0 0 1 1 1 1 1 1 0
1 0 0 0 1 0 1 1 0 0 0 0
2 0 0 1 0 1 1 0 1 1 0 1
3 0 0 1 1 1 1 1 1 0 0 1
4 0 1 0 0 0 1 1 0 0 1 1
5 0 1 0 1 1 0 1 1 0 1 1
6 0 1 1 0 1 0 1 1 1 1 1
7 0 1 1 1 1 1 1 0 0 0 0
8 1 0 0 0 1 1 1 1 1 1 1
9 1 0 0 1 1 1 1 1 0 1 1
10 1 0 1 0 x x x x x x x
11 1 0 1 1 x x x x x x x
12 1 1 0 0 x x x x x x x
13 1 1 0 1 x x x x x x x
14 1 1 1 0 x x x x x x x
15 1 1 1 1 x x x x x x x
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K-Map Simplification:

Logic Diagram:
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7. Encoder
An encoder is a digital circuit that performs the inverse operation of a decoder.
An encoder has 2n (or fewer) input lines and n output lines.
The output lines generate the binary code corresponding to the input value.

Types:
 4 to 2 line Encoder
 8 to 3 line Encoder[ Octal to Binary]
 16 to 4 line Encoder[ Hexadecimal to Binary]
 Decimal to BCD Encoder
 Priority Encoder

7.1. Octal to binary encoder:

It has eight inputs (one for each of the octal digits) and three outputs that generate the corresponding
binary number. It is assumed that only one input has a value of 1 at any given time.

The encoder can be implemented with OR gates whose inputs are determined directly from the truth table.
z = D1 + D3 + D5 + D7
y = D2 + D3 + D6 + D7
x = D4 + D5 + D6 + D7

Logic diagram of octal to binary encoder

7.2. 16to 4 ENCODER

It has sixteen inputs (one for each of the hexadecimal digits) and four outputs that generate the corresponding
binary number. It is assumed that only one input has a value of 1 at any given time.
 CS 3352-DP&CO UNIT I

Truth table

Logic Diagram

7.3. Decimal TO BCD Encoder:

Truth Table
Inputs OUTPUTS

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 W X Y Z Logic Diagram:
1 0 0 0 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 0 0 0 1 0 0
0 0 0 0 0 1 0 0 0 0 0 1 0 1
0 0 0 0 0 0 1 0 0 0 0 1 1 0
0 0 0 0 0 0 0 1 0 0 0 1 1 1
0 0 0 0 0 0 0 0 1 0 1 0 0 0
0 0 0 0 0 0 0 0 0 1 1 0 0 1

W=D8+D9
X=D4+D5+D6+D7
Y=D2+D3+D6+D7
Z=D1+D3+D5+D7+D9
 CS 3352-DP&CO UNIT I
Disadvantage of Encoder:
1. If two inputs are active simultaneously, the output produces an undefined combination.
if D3 and D6 are 1 simultaneously, the output of the encoder will be 111.The output 111 does not
represent either binary 3 or binary 6.
To resolve this ambiguity, encoder circuits must establish an input priority to ensure that only one input is
encoded.
2. When all the inputs are 0, all outputs are 0, but this output is the same as when D0 is equal to 1.
The discrepancy can be resolved by providing one more output to indicate whether at least one input is equal to 1.

7.4. Priority Encoder

A priority encoder is an encoder circuit that includes the priority function.
If two or more inputs are equal to 1 at the same time, the input having the highest priority will take precedence.
The truth table of a four-input priority encoder is given below.

V is a valid bit indicator that is set to 1 when one or more inputs are equal to 1.
If all inputs are 0, there is no valid input and V is equal to 0.
The other two outputs are not inspected when V equals 0 and are specified as don‘t-care conditions.
Instead of listing all 16 minterms of four variables, the truth table uses an X to represent either 1 or 0.
For example, X100 represents the two minterms 0100 and 1100.
Simplified expression of outputs obtained from K-Map simplification
D2D3
D2D3
00 01 11 10 00 01 11 10

D0D1 X 1 1 1
D0D1 X 1 1
00 00

1 1 1 01
1 1 1
01

1 1 1 11
1 1 1
11

1 1 1 10
1 1
10

K-Map for x K-Map for y

Simplified Boolean expressions are x=D3 +D2 and

y =D1D2‘+D3 and
V=D0+D1+D2+D3

8. Parity generation and checking

The parity bit is used at the transmitting side for the purpose of detecting errors during the transmission of binary
information.
A parity bit is an extra bit included with a binary message to make the number of 1‘s either odd or even.
A error is detected at the receiving end if the checked parity does not correspond with the one transmitted.
Parity generator is the circuit that generates the parity bit in the transmitter.
 CS 3352-DP&CO UNIT I
Parity checker is the circuit that checks the parity in the receiver is called a parity checker.

8.1. Parity generator Truth table

1. x,y,z constitute the message and are the inputs to the circuit. Inputs output
2. Parity bit P is the output of the circuit. A B C Pe Po
3. For even parity, P must be generated to make the total number 0 0 0 0 1
of 1‘s (including P) even. 0 0 1 1 0
4. From the truth table even parity Pe is equal to 1 for those minterms,
0 1 0 1 0
whose numerical values have an odd number of 1‘s.hence Pe can be
0 1 1 0 1
expressed as a three variable exclusive-OR function.
1 0 0 1 0
Pe = A B C
1 0 1 0 1
5. For odd parity, P must be generated to make the total number
of 1‘s (including P) odd. 1 1 0 0 1
6. It is the complement of the even parity 1 1 1 1 0
Po = (x y z)’

A A
Pe
B
c B Po
c
3- bit even parity generator
3- bit odd parity generator
BC
A 00 01 11 10

0
1 1

1
1 1

Kmap for Pe

Pe = A′B’C+ A’BC ’+AB’C’+ ABC

8.2. Parity checker

1. Message together with parity bit are applied to parity-checker at the destination.
2. If the information transmitted with even parity, the four bits received must have an even number of 1‘s.
3. If the received information have an odd number of 1‘s , then the error occur.
4. Output of the parity checker is 1 if error occurs.

Truth table
Inputs output 5. Form the truth table C consists of the eight minterms with binary
A B C P C numerical values having odd number of 1‘s.
0 0 0 0 0 C=A B C P
0 0 0 1 1
0 0 1 0 1
0 0 1 1 0 A
0 1 0 0 1 B
0 1 0 1 0
C
0 1 1 0 0
0 1 1 1 1 C
1 0 0 0 1 P
1 0 0 1 0
1 0 1 0 0
1 0 1 1 1
1 1 0 0 0
1 1 0 1 1
1 1 1 0 1
1 1 1 1 0
 CS 3352-DP&CO UNIT I

Code converters
CS 3352-DP&CO UNIT I
 CS 3352-DP&CO UNIT I

Unit I
1. Define Combinational circuit.
A combinational circuit consists of logical gates whose outputs at any time are determined from
the present combination of inputs. A combinational circuit performs an operation that can be
specified logically by a set of Boolean functions. It consists of input variables, gates and output
variables.

2. What is meant by carry propagation delay?

 In parallel adders, sum and carry outputs of any stage cannot be produced until the input carry
occurs.
 This time delay in the addition process is called carry propagation delay.
 This delay increases with increase in the number of bits to be added in an adder circuit.

2. What is magnitude comparator? (Nov/Dec ‘19)

A magnitude digital Comparator is a combinational circuit that compares two digital or binary numbers
in order to find out whether one binary number is equal, less than or greater than the other binary
number. We logically design a circuit for which we will have two inputs one for A and other for B
and have three output terminals, one for A > B condition, one for A = B condition and one for A < B

3. Define full adder and half adder.

Half adder :A combinational circuit that performs the addition of two bits is called a half adder.It has two
binary inputs (augends, addend) and two binary outputs (sum & Carry)
A full adder is a combinational circuit that performs the arithmetic sum of three bits (two significant bits
and a previous carry).It consists of three inputs and two outputs.

4. Draw the logic circuit for the expression F=A’B+AB’C’

5. How does the look-ahead-carry speed up the addition process?

The Look-ahead-carry adder speeds up the addition process by eliminating the ripple carry delay. It
examines all the input bits simultaneously and also generates the carry-in-bits for all the stages
simultaneously.

6. what is decoder?
Decoder is a multiple input multiple output logic circuit which converts coded input into coded output. In
a binary decoder n inputs produces 2n outputs.

7. what is multiplexer ? show the block diagram of 4×1 multiplexer.

A multiplexer is a combinational circuit that selects binary information from one of many input lines and
directs it to a single output line.
The selection of a particular input line is controlled by a set of selection lines.
Normally, there are 2n input lines and n selection lines whose bit combinations determine which input is
to be selected.
 CS 3352-DP&CO UNIT I

8. draw 8:1 multiplexer using two 4:1 multiplexer

9. Construct full adder using half adder and OR gate.

10. Write about the design procedure of combinational circuit.

The design procedure of the combinational circuit involves the following steps:
 The problem definition.
 Determining the number of available input variables and required output variables.
 Assigning the letter symbols to input and output variables.
 Deriving the truth table, indicating the relationships between input and output variables
 Obtaining the simplified Boolean expression for each output.
 Obtaining the logic diagram.
 CS 3352-DP&CO UNIT I
11. Draw the 4 bit Binary to Gray code converter

12. What is a priority encoder? (Apr/May ‘17)

A priority encoder is an encoder circuit that includes the priority function. The
operation of the priority encoder is such that if two or more inputs are activated
at the same time, the output binary code will be generated to the highest-
numbered input.

13. Write the truth table of 2 to 4 line decoder and draw its logic diagram

Y3  I1 I0 Y2  I1 I0

Y1  I1 I0 Y0  I1 I0

Y3
Logic diagram

Y2

Y1

Y0

I1
I0
14. Mention the uses of decoder
Uses of decoder are
Code converter
Implementation of combinational circuits
Address decoding

15. Write the Verilog module for 2 to 1 line Mux.

module exm4_6(A,B,S,O);
input A,B,S;
output O;
assign O=S ? A:B;
endmodule
 CS 3352-DP&CO UNIT I
16. State the different modeling techniques used in HDL. (Apr/May ’18)
There are different abstraction levels in Verilog HDL. These ―Different
abstraction levels‖ are also known as ―different modeling techniques‖. These are
1. Switch level modeling
2. Gate level modeling
3. Dataflow level modeling
4. Behavioural level modeling
5. Structural level modeling

17. Give some of the major applications of multiplexers.

a. Data selection b. Data routing c. Operation sequencing d.Parallel to serial conversion e. Waveform
generation f. Logic-function generation

18. Write the stimulus for 2 to 1 line Mux.

module exm4_6(A,B,S,O);
input A,B,S;
output O;
assign O=S ? A:B;
endmodule

19. Design the combinational circuit with 3 inputs and 1 output. The output is 1when the binary value of
the input is less than 3. The output is 0 otherwise. (May/June ‘16)

Truth table

yz
x 00 01 11 10
1 1 1

F=x‘y‘+x‘z‘
1

20. State the differences between combinational logic and sequential logic.