CS 3352 –DP&CO Unit II

/II IT
UNIT II SYNCHRONOUS SEQUENTIAL LOGIC
Introduction to Sequential Circuits – Flip-Flops – operation and excitation tables, Triggering of FF,
Analysis and design of clocked sequential circuits – Design – Moore/Mealy models, state minimization,
state assignment, circuit implementation - Registers – Counters.

Sequential Circuit- Introduction

1. It consist of combinational circuit to which storage elements are connected to form a
feedback path.
2. Binary information stored in the storage element define the state of the sequential circuit at
that time.
3. Output of the sequential circuit are a function of not only of the input but also of the present
state of the storage element.
4. External input determine the condition for changing the state in the storage element.
5. Next stage of the storage element is also a function of external inputs and present state.

Sequential circuit

Shynchronous Ashynchronous
Sequential circuits Sequential circuits

Synchronous sequential circuits Asynchronous sequential circuits

1. Signals can affect the memory elements Change in input signals can affect the memory
only at discrete instants of time. element
2 Memory elements are clocked flip-flops Memory elements are un clocked flip-flops or
time delay instant of time.
3 The maximum operating speed of clock Because of absence of clock, asynchronous
depends on time delays involved circuits can operate faster than synchronous
circuits
4 Easier to design More difficult to design

Difference between sequential circuits and combinational circuits

Combinational circuits Sequential circuits

1. Output depends on present input Output depends not only on present input but also
on past output
2 No feedback involved It has feedback
3 It doesn‟t have clock signal It may or may not have clock signal , but most
sequential circuit have clock signal
4 Faster than sequential circuits Low speed
5 Memory unit is not required Memory unit is required
6 Easy to design Design is not easy

1
 CS 3352 – DP& CO Unit II
7 Examples: Half Adder, Full Adder, Half
Examples:Serial Adder, Flip-Flops, Counters
Subtract or, Full Subtract or, Parallel
form the sequential circuit.
Adder

1. Latches
It is a memory cell, which is capable of storing one bit of information.
changes its output immediately based on the applied input.
It is used to store either 1 or 0 at any specified time.
It consists of two inputs namely “SET” and RESET and two outputs, which are complement
to each other.

S-R Latch:
The simplest type of latch is the Set-Reset (SR) latch. It can be constructed either by two
NAND gates or two NOR gates.
NOR gate: any one of the input is 1, then the output is zero.

Operation:
Case 1: S = 1; R = 0
In this case, S input of the NOR gate2 is at logic 1,
hence its output 𝑄̅= 0.
Both inputs to NOR gate1 are now at logic 0.
Therefore, the output Q = 1.

Case 2: S = 0; R = 1
R input of the NOR gate1 is at logic 1, hence its output Q = 0.
Both inputs to NOR gate2 are now at logic 0.
Therefore, the output 𝑄̅= 1.
Case 3: S = 0; R = 0
There are two assumptions:
i) Initially Q = 1 and 𝑄̅= 0.
With 𝑄̅= 0, both the inputs to NOR gate1 are at logic 0.
So its output Q is at logic 1.
With Q = 1, one of input of NOR gate2 is at logic 1, hence its output 𝑄̅= 0.
The output does not change.

ii) Initially Q = 0 and 𝑄̅= 1

With 𝑄̅= 1, one of input of NOR gate1 is at logic 1, hence its output 𝑄 = 0.
With 𝑄= 0, both the inputs to NOR gate2 are at logic 0.
So its output 𝑄̅ is at logic 1.The output does not change.

Case 4: S = 1, R = 1.
One of the input of each NOR gate is one, so both the outputs are 0.
This condition is not valid, because it violates the invertible output property.
For Normal operation, this Condition must be avoided.

2
 CS 3352 – DP& CO Unit II

Characteristic table State diagram

Inputs outputs
S R Qn+1
0 0 Qn No change
0 1 0 Reset
1 0 1 Set
1 1 ? Forbidden

State table Excitation table

Present S R Next state O𝑛 O𝑛+1 Excitation Inputs
State Q Qn+1 S R
0 0 0 0 0 0 0 X
0 0 1 0 0 1 1 0
0 1 0 1 1 0 0 1
0 1 1 F 1 1 X 0
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 F

Characteristic equation:
It can be obtained from the K-Map. It is the logic equation that describes the operation of
Latch.

Qn+1=S+QnR‟

2. Flip-Flops:
The latch with the additional control input is called the Flip-Flop.
The additional control input is either the clock or enable input.
It checks the inputs but changes the output only at times defined by the clock signal or any
other control signal.
There are four basic types, namely S-R, J-K, D and T flip-flops.
Flip flops are edge triggered. All the flip flops are categorized into positive edge triggered
and negative edge triggered.

2.1. Triggering of Flip-flop

i. Level triggering
ii. Edge triggering

A clock pulse starts from an initial value of 0, goes momentarily to 1, and after a short
interval, returns to the initial value.
Level Triggering of Flip-flops
A flip-flop gets enabled when a clock pulse goes HIGH and remains enabled throughout the
duration of the clock pulse remaining HIGH.

3
 CS 3352 – DP& CO Unit II
Positive level triggered flip-flop
Flip-flop changes its state when the clock pulse is positive.

Negative level triggered flip-flop

NOT gate is introduced in the clock input terminal of the fl ip-flop.
The flip-flop changes its state when the clock pulse is negative.

The main drawback of level triggering is that, as long as the clock pulse is active, the flip-
flop changes its state more than once or many times for the change in inputs.
If the frequency of the input change is higher than the input clock frequency, the output of the
Flip-flop undergoes multiple changes as long as the clock remains active.

Edge-triggering of Flip-flops
A clock pulse goes from 0 to 1 and then returns from 1 to 0.
The output state is allowed to change according to the input only at the positive or negative
edge of the clock pulse at the enable input.
a) Positive Edge Triggering: Here, the output responds to the change in the input only
at the positive edge of the clock pulse

b) Negative Edge Triggering: Here, the output responds to the change in the input only
at the negative edge of the clock pulse

figure shows the two transitions and they are defined as the positive edge (0 to 1 transition)
and the negative edge (1 to 0 transition).
The term edge-triggered means that the flip-flop changes its state only at either the positive or
negative edge of the clock pulse.

2.2. S-R Flip-Flop:

The S-R flip-flop obtained by adding gates to the inputs of the SR Latch.

4
 CS 3352 – DP& CO Unit II

In this circuit (2) when Clk=0, output of NAND gates 1 & 2 becomes one and the changes in S ,R
input will not change the output Q.
When the Clk input goes to 1, information from the S or R input is allowed to affect the latch.
The output (Q) will change accordingly as long as the clock input is HIGH.
In this manner, one can store either a 1 by applying S=1, R=0.
Or a 0 by applying S=0, R=1.
Characteristics table

Truth table / function table for Truth table / function table for
positive edge triggered flip flop Negative edge triggered flip flop Presen Data Next Action
state Inputs State
Inputs outputs Inputs outputs O S R O𝑛
Clk S R Qn+1 Qn+1’ Qn+1 Qn+1’ 0 0 0 0 No Chang
Clk S R
0 X X Qn Qn‟ 0 X X Qn Qn‟„ 1 0 0 1 No Chang
↑ 0 0 Qn Qn „ ↓ 0 0 Qn Qn 0 0 1 0 Reset
↑ 0 1 0 1 ↓ 0 1 0 1 1 0 1 0 Reset
↑ 1 0 1 0 ↓ 1 0 1 0 0 1 0 1 Set
↑ 1 1 0 0 ↓ 1 1 0 0 1 1 0 1 Set
0 1 1 ? Forbidden
1 1 1 ? Forbidden

Input output waveform for positive edge triggered D flip flop

2.3.D Flip-Flop:
1. The D flip-flop has only one input (D) and two outputs Q and 𝑄̅.
2. It can be constructed from an S-R flip-flop by inserting an inverter between S and R and assigning
the symbol D to the S input.

Operation:
1. When the CLK input is LOW, D input has no effect on the output.
2. When Clock goes HIGH,
i) CLK = 1; D = 1 NAND gate -1 output goes to„0‟
NAND gate -2 output goes „1‟
One of input of NAND gate3 is at logic 0, Therefore, Output (Q) = 1.

5
 CS 3352 – DP& CO Unit II

Both inputs to NAND gate 4 is at logic 1, hence its output 𝑄̅= 1

ii) CLK = 1; D = 0 NAND gate -1 output goes „1‟
NAND gate -2 output goes „0‟
One of input of NAND gate4 is at logic 0, hence its Output𝑄̅= 1.
Both inputs to NAND gate 3 is at logic 1.
Therefore, Output (Q) = 0.
3. Hence, the next state of the flip-flop follows the value of the input D when CLK=1.
4. As transfer of data from the input to the output is delayed, it is known as delay (D) flip-flop.
5. The D-type flip-flop is either used as delay device or as a latch to store 1 bit of information.

State Diagram
Truth table/Function table D=1
CLK Input (D) Output (Qn+1)
0 X No Change
↑ 0 0 Reset 0 1 D=1
𝐷=0
↑ 1 1 Set
𝐷=0
Characteristics table
Excitation table
Present State Delay Next 𝑄𝑛 O𝑛+1 Excitation
(O𝑛) input (D) state Input (D)
O𝑛+1 0 0 0
0 0 0 0 1 1
0 1 1 1 0 0
1 0 0 1 1 1
1 1 1

Characteristics equation

Input output waveform for positive edge triggered D flip flop

Charateristics equation Qn+1=D

2.4. J-K Flip-Flop:

1. This simple JK flip Flop is the most widely used of all the flip-flop designs and is
considered to be a universal flip-flop circuit
2. A J-K flip-flop has the characteristics similar to the S-R flip-flop.
3. Inputs J and K behave like inputs S and R to set and reset the flip-flop respectively.
4. When J=K=1, the flip-flop output toggles, i.e If Q=0, it switches to Q=1 and vice versa.
5. A J-K flip-flop can be obtained from the clocked S-R flip-flop by including two AND
gates as shown in the figure.
6. The data input J and the output 𝑄̅are applied to the first AND gate,
Its product (J𝑄̅) is applied to the S input of S-R flip-flop.
6
 CS 3352 – DP& CO Unit II

7. The data input K and the output Q are applied to the second AND gate,
Its product (KQ) is applied to the S input of S-R flip-flop.

J
Q
CLK
𝑄̅
K
Symbol
Logic Diagram

Truth Table
Clk Inputs Output Comment
J K O𝑛+1
X 0 0 𝑄𝑛 No Change
↑ 0 1 0 Reset
↑ 1 0 1 Set
↑ 1 1 ̅𝑄𝑛̅ Toggle

Characteristics table
Characteristics equation
Present Next
Inputs
State state
J K
𝑄𝑛 O𝑛+1
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 1 Characteristic equation Q n+1 = J̅Q̅n+ Qn K
̅
1 0 1 0
1 1 0 1
1 1 1 0
State diagram
Excitation Table

𝑄𝑛 Qn+1 Excitation Inputs

J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0

Input output waveform for positive

edge triggered JK flip flop

7
 CS 3352 – DP& CO Unit II

Race around condition

In JK flip-flop when J=K=1, the output toggles.
Consider that initially Q=1 and J= K = 1 and a pulse as shown in Figure
is applied at the clock input.
After a time interval ∆t equal to the propagation delay through two NAND gates in series, the
outputs will change to Q = 0. So now we have J = K = 1 and Q = 0.
After another time interval of ∆t the output will change back to Q = 1.
Hence, we conclude that for the time duration of tP of the clock pulse, the output will oscillate
between 0 and 1.
Hence, at the end of the clock pulse, the value of the output is not certain.
This situation is referred to as a race-around condition.

Methods to eliminate race around condition

 Increasing the delay of flip-flop
But it is not a good solution as increasing the delay will decrease the speed of the
system.
 Use of edge-triggered flip-flop
 Use of master-slave JK flip-flop

2.5.Master slave Flip flop

1. A master –slave flip-flop is constructed from two separate flip-flops.

2. One circuit serves as a master and the other as a slave.
3. Gates 1 through 4 form the master flip-flop, and gates 5 through 8 form the slave flip-
flop.
4. Clocked JK flip-flop is a master flip-flop & clocked RS flip-flop is a slave flip-flop.

8
 CS 3352 – DP& CO Unit II

Working
When CP=0
1. Outputs of gates 1 & 2 at the level 1. This prevents the J & K inputs from affecting the
master flip-flop. Master flip-flop is disabled.
2. Clock input of the slave is 1.The flip-flop is enabled output Q is equal to Y, while Q‟ is
equal to Y‟.

When CP=1
1. The information at the external J, K inputs is transmitted to the master flip-flop.
2. The slave flip-flop is isolated as long as the clock is at 1 level.
3. Assume that clock pulse inputs to all flip-flops are synchronized (occur at the same
time).
4. At the beginning of each clock pulse, some of the master elements change state, but all
flip-flop outputs remain at their previous values.
5. After clock pulse returns to 0, some of the outputs change state, but none of these new
states have an effect on any of the master elements until the next clock pulse.
6. Thus, the states of flip-flops in the system can be changed simultaneously during the
same clock pulse, even though outputs of flip-flops are connected to inputs of flip-flops.
7. The binary content of one flip-flop can be transferred to a second flip-flop and the
content of the second transferred to the first, and both transfers can occur during the
same clock pulse.

2.6. T Flip-Flop:
1. Toggle or trigger (T) flip-flop has single input (T) and two outputs Q and 𝑄̅
2. T-type flip-flop is obtained from a J-K flip-flop by connecting its J and K inputs together.
T J
Q T Q
Clk
𝑄̅ Clk 𝑄̅
K

Logic Symbol Logic symbol

3. When the input T=0 (i.e., J=K=0), the output remains unchanged.
4. When the input T=1(i.e., J=K=1), the output toggles
Characteristic table Excitation Table
Function table
Present Input Next Qn Qn+1 Excitation
Input Next state State T state
T Qn+1 Input (T)
Qn Qn+1
0 Qn No 0 0 0
0 0 0 0 1 1
change
0 1 1 1 0 1
1 Qn‟ 1 0 1
complement 1 1 0
1 1 0
.

9
 CS 3352 – DP& CO Unit II

Characteristic equation is obtained from K-Map

State Diagram

T= 1

0 1 T=0
T=0

T=1
Characteristic equation ̅n+ T
Qn+1 = T Q ̅Q n

Excitation table for different Flip-Flops

Characteristic Table or Transition Table:

The characteristic table is useful for analysis and for defining the operation of the flip-
flop. It specifies the next state (Qn+1) when the inputs and present states are known.

Characteristic Equation:
1. It is an algebraic expression for the binary information of the characteristic table.
2. This equation derived from K-Map.
3. This equation specifies the value of the next state as a function of the present state and
input.

Application Table or Excitation Table:

1. The table is useful for design process.
2. It is used to find the flip-flop input conditions that will cause the required transition,
when the present state (Qn) and the next state (Qn+1) are known.

2.7.Interconversion of Flip-Flops
Convert a SR Flip-Flop into JK Flip-Flop.
Step 1: Make a excitation table which consist of excitation table of the original Flip-Flop and
characteristic table of the resultant Flip-Flop.

10
 CS 3352 – DP& CO Unit II

Input Present State Next State Flip-Flop inputs

J K Qn Qn+1 S R
0 0 0 0 0 X
0 1 0 0 0 X
1 0 0 1 1 0
1 1 0 1 1 0
0 0 1 1 X 0
0 1 1 0 0 1
1 0 1 1 X 0
1 1 1 0 0 1

Step 2: K-Map simplification.

From the table find Boolean expression for S & R input using K-Map simplification.

Step 3: Draw the logic diagram

𝑆 = 𝐽̅𝑄̅𝑛 , 𝑅 = 𝐾𝑄𝑛

Exercise 2.1 convert JK flip-flop into T flip-flop.

3. Design of Synchronous Sequential circuits

In synchronous sequential circuits, clocked flip-flops are used as memory elements

Thus the change in states of flip-flops and change in state of entire circuit occurs at the
transition of clock signal.
The state of the output of the flip-flop gives the state of the sequential circuit.
Present state: The status of all state variables, at some time t, before the next clock
edge, represents condition called present state.
Next state: The status of all state variables, at some time t+1, represents a condition
called next state.
The synchronous sequential circuits are represented by two models:

11
 CS 3352 – DP& CO Unit II

1. Mealy model
2. Moore model

Moore Model:

When the output of the sequential circuit depends only on the present state of the flip-flop,
the sequential circuit is referred to as Moore model
Example: Let us have a sequential circuit as shown in fig below, which consists of two JK
flip-flops and three AND gates.

The circuit has one input X and one output Y. From the fig, we can understand that the input
X is not used to determine the output Y. The output is derived using only the present states of
the flip-flops.

Mealy Model:
When the output of the sequential circuit depends both on the present state of the flip-flop
and on the inputs, then the sequential circuit is referred to as Mealy model.
Example: Let us have a sequential circuit as shown in fig below, which consists of two JK
flip-flops and three AND gates.

12
 CS 3352 – DP& CO Unit II

The circuit has one input X and one output Y. From the fig, we can understand that, the
output of the circuit is derived using both the input X and the present states of the flip-flops.

3.1. Comparision between mealy and moore model

Mealy model Moore Model

1. Output is a function of both the present Output is a function of only the present state.
state and the input
2 Input changes may affect the output of Input changes do not affect the output of the
the circuit. circuit

3 Generally, it has fewer states than Moore Generally, it has more states than Mealy Machine
Machine
Outputs may change if the inputs change In Moore machines, more logic is required to
4 during the clock cycle. decode the outputs resulting in more circuit
delays. They generally react one clock cycle later.

5 Requires less hardware to design More hardware is required to design

The two models of a sequential circuit are commonly referred to as a finite state machine
(FSM).

3.2. Design Procedure

1. The word description of the circuit behaviour is stated. This may be accompanied by a
state diagram, a timing diagram.
2. From the given information about the circuit, obtain the state table.
3. The number of states may be reduced by state reduction methods.
4. Assign binary values to each state if the state table obtained in step 2or 3 contains letter
symbols.
5. Determine the number of Flip-Flops needed and assign a letter symbol to each.
6. Choose the type of Flip-Flop to be used.
7. From the state table, derive the circuit excitation and output tables.
8. Using the map or any other simplification method, derive the circuit output functions and
the Flip-Flop input functions.
9. Draw the logic diagram.

The type of Flip-Flop to be used may be included in the design specifications or may

13
 CS 3352 – DP& CO Unit II
depend what is available to the designer. Many digital systems are constructed with
JK Flip-Flops because they are the most versatile available. The selection of inputs
is given as follows.
JK - general applications
D- Application requiring transfer of data
T- application involving complementation
State Equation:
The behaviour of a clocked sequential circuit can be described algebraically by means of state
equations.
A state equation (also called a transition equation) specifies the next state as a function of the
present state and inputs.

State Table:
The time sequence of inputs, outputs, and flip-flop states can be enumerated in a state table
(sometimes called a transition table).
The table consists of four sections labelled present state, input, next state, and output.

mealy –state table

Moore –state table

Transition table
A state table with binary assignment is called transition table.
Assignment of values to state variables is called state assignment.
This gives the next states of flip-flops as a function of present state and inputs.

mealy –Transition table

14
 CS 3352 – DP& CO Unit II

Moore –Transition table

State Diagram:

The information available in a state table can be represented graphically in the form of a state
diagram.
In this type of diagram, a state is represented by a circle, and the transitions between states
are indicated by directed lines connecting the circles
The binary number inside each circle identifies the state of the flip-flops.
The directed lines are labelled with two binary numbers separated by a slash.
The input value during the present state is labelled first, and the number after the slash gives
the output during the present state with the given input.

Moore –state diagram

mealy –state diagram

State Reduction:
The state reduction technique avoids the introduction of redundant states.
The reduction in redundant states reduces the number of required flip-flops and logic gates.
Two states are said to be equivalent if, every possible set of inputs generate exactly same
output and same next state.
One of them can be removed without altering the input-output relationship.

Example 3.1: Reduce the number of states in the following state table. Apr/May 2010 (12 Marks)
Present Next state Output
state x=0 x=1 x=0 x=1
a f b 0 0
b d c 0 0
c f e 0 0
d g a 1 0
e d c 0 0
f f b 1 1
g g h 0 1
h g a 1 0
15
 CS 3352 – DP& CO Unit II

Solution:
Step 1: From the given state table states d & h and b & e are equivalent states.
d=h & b=e
Remove the rows with present state h & e. replace state h by d and state e by b each time it
occurs in the columns headed “Next State”.
Reducing the state table
Table 2
Present Next state Output
state x=0 x=1 x=0 x=1 Present Next state Output
a f b 0 0 state x=0 x=1 x=0 x=1
b d c 0 0 a f b 0 0
c f e b 0 0 b d c a 0 0
c f b 0 0
d g a 1 0
e d c 0 0 d g a 1 0
f f b 1 1 f f b 1 1
g g h d 0 1 g g d 0 1
h g a 1 0

Step 2: From table 2 a &c is equivalent states.

Remove the rows with present state c. replace state „c‟ by „a‟, each time it occurs in the
columns headed “Next State”.

Reduced state table

Present Next state Output
state x=0 x=1 x=0 x=1
a f b 0 0
b d a 0 0
d g a 1 0
f f b 1 1
g g d 0 1

Example 3.2: Construct reduced state diagram for the following state diagram.
May/June 2013 (16 Marks)

16
 CS 3352 – DP& CO Unit II

Solution:
Step 1: Derive the state table.
Present Next state Output
state x=0 x=1 x=0 x=1
a a b 0 0
b c d 0 0
c a d 0 0
d e f 0 1
e a f 0 1
f g f 0 1
g a f 0 1
Step 2: Apply state reduction algorithm
From the state table states e & g are equivalent states ( e=g).
Remove the rows with present state g. replace state „g‟ by „e‟, each time it occurs in the
columns headed “Next State”.
Present Next state Output
state x=0 x=1 x=0 x=1
a a b 0 0
b c d 0 0
c a d 0 0
d e f 0 1
e a f 0 1
f g e f 0 1
g a f 0 1

From Table 2 states d & f are equivalent states (d=f). Remove the rows with present state f.
replace state f by d, each time it occurs in the columns headed “Next State”.

Present Next state Output

state x=0 x=1 x=0 x=1
a a b 0 0
b c d 0 0
c a d 0 0
d e f d 0 1
e a f d 0 1
f e f 0 1
Reduced state table Number of states is reduced from 7 to 5.
Present Next state Output
state x=0 x=1 x=0 x=1
a a b 0 0
b c d 0 0
c a d 0 0
d e d 0 1
e a d 0 1
Reduced State Diagram

17
 CS 3352 –DP&CO Unit II

Example 3.3. Design a synchronous sequential circuit using JK for the given state diagram
Apr/May 2010 (16 Marks)

Solution:
Step 1: Obtain the state table.
Present State Next State
A B x=0 x=1
AB AB
0 0 00 01
0 1 10 01
1 0 10 11
1 1 11 00
Step 2: Derive the excitation table:
The type of Flip-Flop to be used is JK.
To accommodate 4 states we need 2 Flip-Flops (A & B)
Excitation table of JK flipflop
Present state Input Next state Flip Flop inputs
A B x A B JA KA JB KB 𝑄𝑛 Qn+1 Excitation
Inputs
0 0 0 0 0 0 X 0 X
J K
0 0 1 0 1 0 X 1 X
0 0 0 X
0 1 0 1 0 1 X X 1
0 1 1 X
0 1 1 0 1 0 X X 0
1 0 X 1
1 0 0 1 0 X 0 0 X
1 1 X 0
1 0 1 1 1 X 0 1 X
1 1 0 1 1 X 0 X 0
1 1 1 0 0 X 1 X 1
Step 3: Find the Flip-Flop input functions using K-Map simplification

K-map for JA K-map for KA

K-map for JB

𝐽𝐴 = 𝐵𝑥̅̅
K-map for KB

18
 CS 3352 –DP&CO Unit II

Step 4: Draw the Logic Diagram

clk
x
JA A
J Q
x‟

KA A‟
K Q‟

B
JB
J Q

KB B‟
K Q‟

Example 3.4. Design a clocked sequential machine using JK Flip-Flops for the state
diagram shown in the figure. Use state reduction if possible. Make proper state
assignment.

Step 1: state table

Next state Output

Present
state X= 0 X= 1 X= 0 X= 1
a a b 0 0
b c b 0 0
c a b 0 1
d a b 0 0

Step 2: state reduction

a and d are equivalent states. a and d generate exactly same next state and same output for
every possible set of inputs. Therefore state d can be removed and replaced by a.

19
 CS 3352 –DP&CO Unit II
Next state Output
Present state
X= 0 X= 1 X= 0 X= 1
a a b 0 0
b c b 0 0
c a b 0 1

Step 3: transition table

Now each state is assigned with binary values. Since there are three states, number of
Flip-Flops required is two. a=00 ,b=01, c=10.
Present state Next state Output
X= 0 X= 1 X= 0 X= 1
00 00 01 0 0
01 10 01 0 0
10 00 01 0 1
Step 4: excitation table

Present state Input Next state Flip Flop inputs output

𝑄𝑛 Qn+1 Excitation
A B x A B JA KA JB KB Inputs
0 0 0 0 0 0 X 0 X 0 J K
0 0 0 X
0 0 1 0 1 0 X 1 X 0
0 1 1 X
0 1 0 1 0 1 X X 1 0 1 0 X 1
1 1 X 0
0 1 1 0 1 0 X X 0 0
1 0 0 0 0 X 1 0 X 0
1 0 1 0 1 X 1 1 X 1
1 1 0 X X X X X X X
1 1 1 X X X X X X X

STEP 5 : K-map simplification

K-map for JA
K-map for KA K-map for JB

20
 CS 3352 –DP&CO Unit II

K-map for KB
K-map for output

Step 6: Logic diagram

Example 3.5. Draw the state diagram. Derive the state equation and draw the clocked
sequential circuit for the following state table.

Present Next State Output

State x=0 x=1 x=0 x=1
AB Y Y
00 00 01 0 0
01 11 01 0 0
10 10 00 0 0
11 10 11 0 0

Solution:
State diagram 0/0
This circuit has four states
1/0 0 1/0

0/0
1/0 1
0

0/0
0/0 1

1/0

21
 CS 3352 –DP&CO Unit II

State equation:
State equation can be obtained from excitation table.
Present state Input Output Next state Flip Flop inputs
A B x Y A B JA KA JB KB
0 0 0 0 0 0 0 X 0 X
0 0 1 0 0 1 0 X 1 X
0 1 0 0 1 1 1 X X 0
0 1 1 0 0 1 0 X X 0
1 0 0 0 1 0 X 0 0 X
1 0 1 0 0 0 X 1 0 X
1 1 0 0 1 0 X 0 X 1
1 1 1 0 1 1 X 0 X 0

K-map for JA K-map for KA

Bx Bx
A 00 01 11 10 A 00 01 11 10
1 X X X X
0 0
X X X X 1
1 1
JA =Bx‟ KA =B‟x

K-map for JB K-map for KB

Bx Bx
A 00 01 11 10
A 00 01 11 10
1 X X X X
0 0
X X X X 1
1 1
JB =A‟x KB=Ax‟

̅ + QK
For JK flip-flop Q(t + 1) = JQ ̅
A(t + 1) = JA A′ + A ̅K̅A
= Bx′ A′ + A ̅B̅′x
= Bx′A′ + A(B + x′)
B(t + 1) = JB B′ + B̅K̅B
̅ + B ̅A̅x′̅
= A′ x B
= A′xB′ + B (A′ + x)

State equations: A(t + 1) = Bx′A′ + A(B + x′)

B(t + 1) = A′x B′ + B (A′ + x)

22
 CS 3352 –DP&CO Unit II

Logic Diagram:
Clk
x
A
J Q

A‟
K Q‟

B
J Q

B‟
K Q‟

Example 3.6 Design a clocked sequential machine using T flip-flops for the following
state diagram. Use state reduction if possible. Also use straight binary state assignment.
(May-11, Marks 8)

Solution:
Step 1: Derive state table
Present Next State Output
State x=0 x=1 x=0 x=1
Y Y
a a b 0 0
b d c 0 0
c a b 1 0
d b a 1 1

Step 2: State assignment:

Assign binary Value for each state .
a=00 ,b=01 ,c=10,d=11.
two flip flops are needed

23
 CS 3352 –DP&CO Unit II

Present Next State Output

State x=0 x=1 x=0 x=1
Y Y
00 00 01 0 0
01 11 10 0 0
10 00 01 1 0
11 01 00 1 1

Step 3: Excitation Table

To find the flip flop inputs TA and TB
Present state Input Next state Flip Flop inputs output
A B x A B TA TB
0 0 0 0 0 0 0 0
0 0 1 0 1 0 1 0
0 1 0 1 1 1 0 0
0 1 1 1 0 1 1 0
1 0 0 0 0 1 0 1
1 0 1 0 1 1 1 0
1 1 0 0 1 1 0 1
1 1 1 0 0 1 1 1

Step 4: K-Map simplification:

K map for y
K map for TA K map for TB
Bx Bx Bx
A 00 01 11 10 A 00 01 11 10 A 00 01 11 10
1 1 1 1
0 0 0
1 1 1 1 1 1 1 1 1
1
1 1
TA =A+B TB =x Output y=AB+Ax‟

Step 5: Logic Diagram:

TA Q
A

Y
Q‟

x TB Q B

Q‟

24
 CS 3352 –DP&CO Unit II

Example 3.7. Design a sequential circuit 'with two D flip-flops A and B and an input x.
When x = 0 the state of the circuit remains the same. When x = 1 the circuit goes
through the state transitions from 00 to 01 to 11 to 10 back to 00 and repeats.

Solution:
Given – two D flip flops are used
Possible states are 00,01,10,11
X=0  circuit remain in same state
X=1  transition be like 00 01 , 0111, 11 10 , 10 00

Step 1: State table

Present Input Next State
State x A B
A B
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 1
1 0 0 1 0
1 0 1 0 0
1 1 0 1 1
1 1 1 1 0

Step 2 : Excitation table

Present state Input Next state Flip Flop inpu
A B x A B DA DB
0 0 0 0 0 0 0
0 0 1 0 1 0 1
0 1 0 0 1 0 1
0 1 1 1 1 1 1
1 0 0 1 0 1 0
1 0 1 0 0 0 0
1 1 0 1 1 1 1
1 1 1 1 0 1 0

Step 3: K-Map simplification:

K map for DA K map for DB

DB =Bx‟+A‟x

DA =Bx+Ax‟

25
 CS 3352 –DP&CO Unit II

Step 4: Logic Diagram:

Example 3.8 Design the synchronous sequential circuit for Moore state diagram as
shown in fig:

Solution:
4 states : a,b,c,d

Step 1 :State table

Present state Next state Output
a b 1
b c 1
c d 0
d a 0

Step 2: transition table

assign binary values to states : a=00 ,b=01 , c= 10 , d=11
Present state Next state Output
AB AB Y
00 01 1
01 10 1
10 11 0
11 00 0

26
 CS 3352 - DP&CO Unit II

Step 3 : excitation table

To find the flip flop inputs
Present state Next state Flip flop inputs Output
A B A B TA TB Y
0 0 0 1 0 1 1
0 1 1 0 1 1 1
1 0 1 1 0 1 0
1 1 0 0 1 1 0

Step 4: K map simplification

K map for TB K map for Y
K map for TA

step 5: Logic Diagram

TA Q A

Q‟ Y

TA Q B

Q‟

4. Analysis of synchronous sequential circuits

The analysis of sequential circuit involves the obtaining a state table or a state diagram for the
time sequence of inputs, outputs and internal states.
Consider the sequential circuit to be analyzed.
The steps used to analyze any given circuit are:

27
 CS 3352 - DP&CO Unit II

Procedure
1. Determine the flip-flop input equations and output equations from the given
sequential circuits.
2. Find the state equation.
3. Draw the state table.
4. Draw state diagram.

Example 4.1. A sequential circuit with 2 D FFs A and B and input X and output Y is
specified by the following next state and output equations.
A (t+1) = AX+BX
B (t+1) =A’X
Y= (A+B) X’
(i) Draw the logic diagram of the circuit
(ii) Derive the state table
(iii) Derive the state diagram

Solution :
For D Flip-Flop Q(t+1)=D
Hence DA=AX+BX
DB = A‟X
Y= (A+B) X‟

i. Logic Diagram

i. State table

Present Input Flip-Flop Inputs Next state Output

state
DA=Ax+Bx
A B x DB=A’x A(t+1) B(t+1) Y= Ax’+Bx’
0 0 0 0 0 0 0 0
0 0 1 0 1 0 1 0

28
 CS 3352 - DP&CO Unit II
0 1 0 0 0 0 0 1
0 1 1 1 1 1 1 0
1 0 0 0 0 0 0 1
1 0 1 1 0 1 0 0
1 1 0 0 0 0 0 1
1 1 1 1 0 1 0 0

Next Output
Present state state
x= 0 x= 1 x= 0 x= 1
A B A B A B Y Y
0 0 0 0 0 1 0 0
0 1 0 0 1 1 1 0
1 0 0 0 1 0 1 0
1 1 0 0 1 0 1 0

ii.State diagram

Example.4.2. A sequential circuit has two JK flip-flop A& B. The flip-flop input
functions are
JA=B JB=x’
KA=Bx’ KB=A x Dec 2013 (16 Marks)
i) Draw the logic diagram of the circuit
ii) Tabulate the state table
iii) Draw the state diagram

Solution:
i) Logic diagram

29
 CS 3352 - DP&CO Unit II

ii) State table

Present Input Flip Flop inputs Next state
state
AB x JA= B KA =Bx’ JB =x’ KB =A x A B
00 0 0 0 1 0 0 1
00 1 0 0 0 1 0 0
01 0 1 1 1 0 1 1
01 1 1 0 0 1 1 0
10 0 0 0 1 1 1 1
10 1 0 0 0 0 1 0
11 0 1 1 1 1 0 0
11 1 1 0 0 0 1 1

Present
state Next state
x=0 x=1
AB A B A B
0 0 0 1 0 0
0 1 1 1 1 0
1 0 1 1 1 0
1 1 0 0 1 1
iii) State Diagram

30
 CS 3352 - DP&CO Unit II

problem 4.3. Analyze the synchronous Mealy machine and obtain its state diagram.

Solution :The given synchronous Mealy machine consists of two D Flip-Flops, one inputs
and one output.
Step 1: Derive expression for flip flop inputs and output
DA= Y1‟ Y2 X‟
DB= x+ Y1‟ Y2
Z= Y1Y2X

Step 2: derive state table

Present state Input Flip-Flop Inputs Next state Output

Y1 Y2 X DA= Y1’Y2X’ DB= X+ Y1’Y2 Y1 Y2 Z= Y1Y2X

0 0 0 0 0 0 0 0
0 0 1 0 1 0 1 0
0 1 0 1 1 1 1 0
0 1 1 0 1 0 1 0
1 0 0 0 0 0 0 0
1 0 1 0 1 0 1 0
1 1 0 0 0 0 0 0
1 1 1 0 1 0 1 1

31
 CS 3352 - DP&CO Unit II

Next state Output

Present state
X= 0 X= 1 X= 0 X= 1
Y1 Y2 Y1 Y2 Y1 Y2 Z Z

0 0 0 0 0 1 0 0
0 1 1 1 0 1 0 0
1 0 0 0 0 1 0 0
1 1 0 0 0 1 0 1

Step 3 :State Diagram

Problem 4.4. logic diagram of the sequential circuit is given below. derive state table
and draw state diagram

solution :
Given : sequential circuit consist of two JK flip flop. It has one input and one output

32
 CS 3352 - DP&CO Unit II

Step 1: find flip flop input function and output expression

JA=x Y2
KA= Y2 „
JB=x
KB= x‟
Z=Y1.Y2‟

Step 2 : state table

Present state Input Flip-Flop Inputs Next state Output

Y1 Y2 X JA=x Y2 KA= Y2 „ JB=x KB= x‟ Y1 Y2 Z=Y1.Y2‟

0 0 0 0 1 0 1 0 0 0
0 0 1 0 1 1 0 0 1 0
0 1 0 0 0 0 1 0 0 0
0 1 1 1 0 1 0 1 1 0
1 0 0 0 1 0 1 0 0 1
1 0 1 0 1 1 0 0 1 1
1 1 0 0 0 0 1 1 0 0
1 1 1 1 0 1 0 1 1 0

Next Output
Present state state
X= 0 X= 1
Z
Y1 Y2 Y1 Y2 Y1 Y2
0 0 0 0 0 1 0
0 1 0 0 1 1 0
1 0 0 0 0 1 1
1 1 1 0 1 1 0

Step 3: state diagram

33
 CS 3352 - DP&CO Unit II

Problem 4.5. A sequential circuit has two T Flip-Flop A and B. The Flip-Flop input
functions are: TA= Bx , TB= x , y= AB

(a) Draw the logic diagram of the circuit,

(b) Tabulate the state table,
(c) Draw the state diagram.

Solution :
Here output does not depend on external input , hence circuit is a Moore model circuit.
a) Logic diagram

b) State table

Present state Input Flip-Flop Next state Output

Inputs
A B x TA= Bx TB= x A B y= AB

0 0 0 0 0 0 0 0
0 0 1 0 1 0 1 0
0 1 0 0 0 0 1 0

0 1 1 1 1 1 0 0
1 0 0 0 0 1 0 0
1 0 1 0 1 1 1 0
1 1 0 0 0 1 1 1

1 1 1 1 1 0 0 1

34
 CS 3352 - DP&CO Unit II

Next state Output

Present state
x= 0 x= 1 y
A B A B A B
0 0 0 0 0 1 0
0 1 0 1 1 0 0
1 0 1 0 1 1 0
1 1 1 1 0 0 1

c) State Diagram

Example 4.6. Derive the state table and state diagram of the sequential circuit shown in
figure.
F2
D Q

F2‟
Q‟

z
x

F1
D Q

F1‟
Q‟

Solution:
Step 1: Find the flip-flop input and the output equations from the sequential circuit.
D1=x‟+F1F2‟
D2=xF1F2‟
Z=xF2

35
 CS 3352 - DP&CO Unit II

Step 2: Derive the state equation

It can be obtained from the characteristic equation of D flip-flop.
For D flip-flop Q(t+1)= D
F1 (t+1) =D1
=x‟+F1F2‟
F2 (t+1) =D2
= xF1F2‟
Step 3: Plot the transition table
Present Input Flip Flop input Next state Output
state
F1 F2 x D1 D2 F1 F2 Z
0 0 0 1 0 1 0 0
0 0 1 0 0 0 0 0
0 1 0 1 0 1 0 0
0 1 1 0 0 0 0 1
1 0 0 1 0 1 0 0
1 0 1 1 1 1 1 0
1 1 0 1 0 1 0 0
1 1 1 0 0 0 0 1

Present Output
state Next state
F1 F2 x=0 x=1 Z
F1 F2 F1 F2 x=0 x=1
0 0 1 0 0 0 0 0
0 1 1 0 0 0 0 1
1 0 1 0 1 1 0 0
1 1 1 0 0 0 0 1

Step 4: Derive state table

Present Output
state Next state
F1 F2 x=0 x=1 Z
F1 F2 F1 F2 x=0 x=1
a c a 0 0
b c a 0 1
c c d 0 0
d c a 0 1

Step 6: state diagram

36
 CS 3352 - DP&CO Unit II

5. Counters:
1. A register that goes through a prescribed sequence of states upon the application of input
pulses is called a counter
2. The sequence of states may follow the binary number sequence or any other sequence of
states. A counter that follows the binary number sequence is called a binary counter. An n ‐
bit binary counter consists of n flip‐flops and can count in binary from 0 through 2n - 1.
3. Counters can be classified as :
Asynchronous and synchronous counters
Single and multi-mode counters
Modulus counters.
4. Asynchronous (ripple) counters
i) Each flip-flop is triggered by the output from the previous flip-flop.
ii) It can be constructed using minimum hardware.
iii) Speed of operation is slow; it is also called as serial counter.
5. Synchronous counters:
i) Clock pulses simultaneously applied to all the flip-flops.
ii) Speed of operation is high.
iii) It is also called as parallel counter.
6. Single Mode counters:
i) It counts either in UP mode or in the DOWN mode.
7. Multi-mode counters
i) It operates in both UP and DOWN mode.
8. Modulus Counters:
i) Modulus counters are defined based on the number of states they are capable
of counting.
9. Applications:
i) Pulse counting ii) Frequency division
ii) iii) Time measurement iv) control and timing operations.

Comparison between Synchronous and Asynchronous Counters

Asynchronous Counters Synchronous counters

In this type of counter, the output of the first In this type, there is no connection between
flip flop drives the clock for the next flip- output of first flip flop and clock input of
flop. the next flip-flop.
All the flip-flops are not clocked All the flip flops are clocked
simultaneously simultaneously
Logic circuits is very simple Design involves complex logic circuits
The delay times of all Flip- Flops are added. There is minimum propagation delay.
Therefore there is considerable
propagation delay.
Cheaper than synchronous counters. Costlier than ripple counters.

37
 CS 3352 - DP&CO Unit II

Example 5.1.sing JK flip-flops, design a synchronous counter which counts in the

sequence 000,001,010,011,100,101,110,111,000. Dec 2013 (16 Marks)
Solution:
Step 1: Draw the state diagram

Step 2: derive state table

Present state Next state

000 001
001 010
010 011
011 100
100 101
101 110
110 111
111 000
Step 3: Excitation table
There are eight states. No of flip-flops are „n‟( 2n≥N) . N= No of states.
We need 3 JK flip-flops. Three flip-flops are designated as A, B & C.
Excitation table for JK FF
Present state Next state Flip Flop inputs
A B C A B C JA KA JB KB JC KC 𝑄𝑛 Qn+1 Excitation
0 0 0 0 0 1 0 X 0 X 1 X Inputs
0 0 1 0 1 0 0 X 1 X X 1 J K
0 1 0 0 1 1 0 X X 0 1 X 0 0 0 X
0 1 1 1 0 0 1 X X 1 X 1 0 1 1 X
1 0 0 1 0 1 X 0 0 X 1 X 1 0 X 1
1 0 1 1 1 0 X 0 1 X X 1 1 1 X 0
1 1 0 1 1 1 X 0 X 0 1 X
1 1 1 0 0 0 X 1 X 1 X 1
Step 4: K-Map simplification
For JA For KA For JB
B B B
A 00 01 11 10 A 00 01 11 10 A 00 01 11 10
1 X X X X 1 X X
0 0 0
X X X X 1 1 1 X X
1 1
JA=BC KA=BC JB=C

38
 CS 3352 - DP&CO Unit II
For KB For JC for KC
B B B
A 00 01 11 10 A 00 01 11 10 A 00 01 11 10
X X 1 1 X X 1 X 1 1 X
0 0 0
X X 1 1 X X 1 X 1 1 X
1 1 1
KB=C JC=1 KC=1

Step 5: logic diagram

LSB MSB
Logic 1

C B J Q A
J Q J Q

K Q‟
K Q‟ K Q‟

clk

Example 5.2.Design a BCD counter using T flip-flop

Step 1: state diagam April/May 2010 (16 Marks)

1001 0000

1000 0001

0111 0010

0110 0011

0101
0100

Step 2: derive state table

Present state Next state
0000 0001
0001 0010
0010 0011
0011 0100
0100 0101
0101 0110
0110 0111
0111 1000
1000 1001
1001 0000

39
 CS 3352 - DP&CO Unit II

Step 3: Excitation table

There are ten states. We need 4 T flip-flops.
Three flip-flops are A, B, C, D.
Present state Next state Flip Flop inputs
A B C D A B C D TA TB TC TD
0 0 0 0 0 0 0 1 0 0 0 1
0 0 0 1 0 0 1 0 0 0 1 1 Excitation table for T
0 0 1 0 0 0 1 1 0 0 0 1 FF
0 0 1 1 0 1 0 0 0 1 1 1 Qn Qn+1 Excitation
0 1 0 0 0 1 0 1 0 0 0 1 Input (T)
0 1 0 1 0 1 1 0 0 0 1 1 0 0 0
0 1 1 0 0 1 1 1 0 0 0 1 0 1 1
0 1 1 1 1 0 0 0 1 1 1 1 1 0 1
1 0 0 0 1 0 0 1 0 0 0 1 1 1 0
1 0 0 1 0 0 0 0 1 0 0 1

Step 4: K-Map simplification

Here we are using only ten input combinations. All other combinations are considered as
don‟t – care combinations.
For TA For TB For TC For TD
CD CD CD CD
AB 00 01 11 10 AB 00 01 11 10 AB 00 01 11 10 AB 00 01 11 10
1 1 1 1 1 1 1
00 00 00 00
1 1 1 1 1 1 1 1
01 01 01 01
X X X X X X X X X X X X X X X X
11 11 11 11
1 X X X X X X 1 1 X X
10 10 10 10
TA=BCD+AD
TB =CD TC =A‟D TD =1

Step 4:Logic diagram

Logic 1
LSB
MSB
D A‟D A
T Q C T Q B T Q
T Q

D C B A

Q‟ Q‟ Q‟ Q‟

clk

40
 CS 3352 - DP&CO Unit II

Example 5.3.Design a counter with the sequence 0,1,3,7,6,4,0

Nov/Dec 2010 (16 Marks)
Solution:
Step 1: state diagram Step 2: derive State table
Present state Next state Present state Next state
00
000 001 000 001
00 001 011
10 001 011
011 111 010 XXX
111 110 011 111
110 100 100 000
11 01
100 000 101 XXX
110 100
11
111 110

Step 3: Excitation table

There are six states. We need 3 JK flip-flops.
Three flip-flops are A, B, C.
Present state Next state Flip Flop inputs
A B C A B C JA KA JB KB JC KC Excitation table for JK
FF
0 0 0 0 0 1 0 X 0 X 1 X
0 0 1 0 1 1 0 X 1 X X 0 𝑄𝑛 Qn+1 Excitation
0 1 0 X X X X X X X X X Inputs
0 1 1 1 1 1 1 X X 0 X 0 J K
1 0 0 0 0 0 X 1 0 X 0 X 0 0 0 X
1 0 1 X X X X X X X X X 0 1 1 X
1 1 0 1 0 0 X 0 X 1 0 X 1 0 X 1
1 1 1 1 1 0 X 0 X 0 X 1 1 1 X 0

Step 4: K-Map simplification

For JA For KA For JB

BC BC BC
A 00 01 11 10 A 00 01 11 10 A 00 01 11 10
1 X X X X X 1 X X
0 0 0
X X X X 1 X X X X
1 1 1
JA=B KA=B‟ JB=C

For KB For JC For KC

BC BC B
A 00 01 11 10 A 00 01 11 10 A 00 01 11 10
X X X 1 X X X X X
0 0 0
X X 1 X X X X 1 X
1 1 1
KB=C‟ JC=A‟ KC=A

41
 CS 3352 - DP&CO Unit II

Step 5: Draw the logic diagram

C LSB B A
J Q J Q J Q MSB

C B A
C‟ B‟ A‟
K Q‟ K Q‟ K Q‟

clk

Exercise 5.1.. The following sequence is to be realized by a counter consisting of 3 JK

FF’s.
A1 0 0 0 0 1 1 0
Nov/Dec 2010 (16 Marks)
A2 0 1 1 0 0 1 0
A3 0 1 0 1 1 0 0
Design the counter.

Example 5.4.Design a BCD counter using T flip-flops, where flip-flop inputs are
TQ1,TQ2,TQ4, andTQ8. April/May 2011 (16 Marks)
Refer the example 4.2.

Example 5.5. Design a counter using JK flip-flop for realizing the following sequence.
Q2 Q1 Q0 Nov/Dec 2011 (16 Marks)
0 0 0
0 0 1
0 1 1
1 1 1
1 1 0
1 0 0
0 0 0
Refer the example 4.3.

5.1. Modulus or MOD-Number of the Counter

The Modulus (or MOD-number) of a counter is the total number of unique states it passes
through in each of the complete cycles.
For example, a MOD-6 counter goes through the state from 0t o 5 and a MOD-4 counter goes
through the states 0 to 3.
Modulus = 2n
where n = Number of flip-flops.
The maximum binary number that can be counted by the counter is 2n –1.
Hence, a 3-flip-flop counter can count a maximum of (111)2 = 23 – 1 = 710.

42
 CS 3352 - DP&CO Unit II

Example 5.6. Design of a MOD -3 counter

A MOD-3 counter is a counter which has only three distinct states.
To design a counter with three states, the number of flip-flops required can be found using
the equation 2n≥ N, where n is the number of flip-flops required and N is the number of states
present in the counter.
For N = 3, from the above equation, n = 2, i.e., two flip-flops are required.
Step 1: Draw state diagram Step 2:Derive state table
Present Next state
00 state
00 01
01
01 10
01
10 00

Step 3: Excitation table Step 4: K-Map simplification

Filp-flop to be used is T flip-flop. For TA For TB
Present Next Flip-flop B B
State state Inputs A 0 1 A 0 1
A B A B TA TB 1 1 1
0 0 0 1 0 1 0 0
0 1 10 1 1 1 X X
1 0 00 1 0 1 1
TA=A+B TB=A‟

Step 5: draw the logic diagram

Example 5.7. Design of MOD-10 (Decade) counter.

Refer example 4.2

5.2. Lockout condition

In the counters with modulus less than 2n, it may happen that the counter by chance finds
itself in any one of the unused states.
For example, in the MOD-10 counter, logic states, A3A2A1A0 = 1010, 1011, 1100, 1101,
1110, and 1111 are not used.
Now, if by chance the counter enters into any one of these unused states, its next state will
not be known.
It may be possible that the counter might go from one unused state to another and never
arrive at a used state, then this counter is said to be in lockout condition.

43
 CS 3352 – DP&CO Unit II
/II IT
The counter that goes in lockout condition is called self starting counter.

5.3.1-Bit Synchronous Binary Counter

In this counter the clock signal is connected in parallel to clock inputs of both the Flip-Flops
(FF0 and FF1). The output of FF0 is connected to J1 and K1 inputs of the second Flip-Flop
(FF1).

Assume that the counter is initially in the binary 0 state: i.e., both Flip-Flops are RESET.
When the positive edge of the first clock pulse is applied, FF0 will toggle because J0=
k0= 1, whereas FF1 output will remain 0 because J1= k1= 0. After the first clock pulse Q0=1
and Q1=0.
When the leading edge of CLK2 occurs, FF0 will toggle and Q0 will go LOW. Since
FF1 has a HIGH (Q0 = 1) on its J1 and K1 inputs at the triggering edge of this clock pulse,
the Flip-Flop toggles and Q1 goes HIGH. Thus, after CLK2,Q0 = 0 and Q1 = 1.
When the leading edge of CLK3 occurs, FF0 again toggles to the SET state (Q0 = 1),
and FF1 remains SET (Q1 = 1) because its J1 and K1 inputs are both LOW (Q0 = 0).After
this triggering edge, Q0 = 1 and Q1 = 1.

Finally, at the leading edge of CLK4, Q0 and Q1 go LOW because they both have a
toggle condition on their J1 and K1 inputs. The counter has now recycled to its original state,
Q0 = Q1 = 0.

Timing diagram

5.3.2. 3-Bit Synchronous Binary Counter

A 3 bit synchronous binary counter is constructed with three JK Flip-Flops and an

AND gate. The output of FF0 (Q0) changes on each clock pulse as the counter progresses
from its original state to its final state and then back to its original state. To produce this
operation, FF0 must be held in the toggle mode by constant HIGH, on its J0 and K0 inputs

44
 CS 3352 –DP&CO Unit II

The output of FF1 (Q1) goes to the opposite state following each time Q0= 1.
This change occurs at CLK2, CLK4, CLK6, and CLK8. The CLK8 pulse causes the counter
to recycle. To produce this operation, Q0 is connected to the J1 and K1 inputs of FF1.
When Q0= 1 and a clock pulse occurs, FF1 is in the toggle mode and therefore changes
state.

When Q0= 0, FF1 is in the no-change mode and remains in its present state.The output of
FF2 (Q2) changes state both times; it is preceded by the unique condition in which both
Q0 and Q1 are HIGH. This condition is detected by the AND gate and applied to the J2
and K2 inputs of FF3. Whenever both outputs Q0= Q1= 1,the output of the AND gate
makes the J2= K2= 1 and FF2 toggles on the following clock pulse. Otherwise, the J2
and K2 inputs of FF2 are held LOW by the AND gate output, FF2 does not change state.

CLOCK Q2 Q1 Q0
Pulse
Initially 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1
8 (recycles) 0 0 0

Timing diagram
5.3.3. Bit Synchronous Binary Counter

45
 CS 3352 –DP&CO Unit II

This particular counter is implemented with negative edge-triggered Flip- Flops. The
reasoning behind the J and K input control for the first three Flip- Flops is the same as
previously discussed for the 3-bit counter. For the fourth stage, the Flip- Flop has to change
the state when Q0= Q1= Q2= 1. This condition is decoded by AND gate G3.

Therefore, when Q0= Q1= Q2= 1, Flip-Flop FF3 toggles and for all other times itis in a no-
change condition. Points where the AND gate outputs are HIGH are indicated by the shaded
areas.

Timing diagram

5.3.4. 4-Bit Synchronous Decade Counter: (BCD Counter):

BCD decade counter has a sequence from 0000 to 1001 (9). After 1001
state it must recycle back to 0000 state. This counter requires four Flip-Flops and
AND/OR logic as shown below.

46
 CS 3352 –DP&CO Unit II

CLOCK Q3 Q2 Q1 Q0
Pulse
Initially 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10(recycles) 0 0 0 0

First, notice that FF0 (Q0) toggles on each clock pulse, so the logic equation for its J0 and
K0 inputs are J0= K0= 1
This equation is implemented by connecting J0 and K0 to a constant HIGH level.
Next, notice from table, that FF1 (Q1) changes on the next clock pulse each time Q0 = 1 and
Q3 = 0, so the logic equation for the J1 and K1 inputs is J1= K1= Q0Q3‟
This equation is implemented by ANDing Q0 and Q3 and connecting the gate output to J1 and
K1 inputs of FFl.
Flip-Flop 2 (Q2) changes on the next clock pulse each time both Q0 = Q1 = 1.
This requires an input logic equation as follows:
J2= K2= Q0Q1
This equation is implemented by ANDing Q0 and Q1 and connecting the gate output to the J2
and K2 inputs of FF3
Finally, FF3 (Q3) changes to the opposite state on the next clock pulse each time Q0 = 1, Q1 =
1, and Q2 = 1 (state 7), or when Q0 = 1 and Q1 = 1 (state 9).
The equation for this is as follows: J3= K3= Q0Q1Q2+ Q0Q3
This function is implemented with the AND/OR logic connected to the J3 and K3 inputs of

Timing

FF3.

47
 CS 3352 –DP&CO Unit II

5.4. RING COUNTER:

1. The Ring counter is the simplest form of Shift-register counter.

2. The construction is same as SISO register except that the output of this shift registers
back to its input.
3. So, the output from the last flip-flop, QD becomes the input of the first flip-flop (DA).

States
QA QB Q C QD
1000
0100
0010
0001
1000

Operation:
The Q output of each stage is connected to the D input of the next stage and the output
of last stage is fed back to the input of first stage.
1. By setting the flip-flop A output (QA) = 1, the output of the counter is „1000‟.
2. On the arrival of second clock pulse, the output of „QA‟ is shifted to „QB‟ and the output
of „QD‟ is shifted to „QA‟. Therefore, the output is „0100‟.
3. This sequence of shifting is shown in the figure given below.
4. Since the ring counter shown above has four distinct states, it is also known as a "modulo-
4" or "mod-4" counter .
5. A "mod-n" ring counter will require "n" number of flip-flops connected together to
circulate a single data bit providing "n" different output states.

5.5.JOHNSON COUNTER

1. The Johnson Ring Counter or "Twisted Ring Counters", is another shift register
counter with feedback exactly the same as the Ring Counter, except the inverted
output Q of the last flip-flop is connected back to the input D of the first flip-flop.
2. The main advantage of this type of counter is that it only needs half the number of
flip-flops compared to the ring counter.
3. Therefore, a "n-stage" Johnson counter will circulate a single data bit of „2n‟ different
states.
4. Hence, it is also considered as a "mod-2n counter".
5. This inversion of Q before it is fed back to input D Causes the counter to "count" in a
different way.
6. The counting pattern of Johnson counter is "1000", "1100", "1110", "1111", "0111",
"0011", "0001", "0000" and this is demonstrated in the following table below.

48
 CS 3352 –DP&CO Unit II

6. SHIFT REGISTER:
1. Aregister is simply a group of flip-flops that can be used to store a binary number.
2. There must be one flip flop for each bit in the binary number. For eg., if a register is
used to store an 8-bit binary number, then eight flip-flops are needed.
3. The Shift Register is another type of sequential logic circuit that is used for the
storage or transfer of data in the form of binary numbers and then "shifts" the data
out once every clock cycle, hence the name "shift register".
4. It basically consists of several single bit "D-Type Data Latches", one for each bit (0 or
1) connected together in a serial or daisy-chain arrangement so that the output from
one data latch becomes the input of the next latch and so on.
5. The bits in a binary number (data) can be removed from one place to another
6. in either of two ways. The first method involves shifting the data one bit at a time in a
serial fashion, beginning with either the most significant bit (MSB) or the least
significant bit (LSB). This technique is referred to as serial shifting. The
second
7. method involves shifting all the data bits simultaneously and is referred to as parallel
shifting.

Different types of Modes:

i) Serial-in to Parallel-out (SIPO) - the register is loaded with serial data, one bit at a
time, with the stored data being available in parallel form.

ii) Serial-in to Serial-out (SISO) - the data is shifted serially "IN" and "OUT" of the
register, one bit at a time in either a left or right direction under clock control.

49
 CS 3352 –DP&CO Unit II

iii) Parallel-in to Serial-out (PISO) - the parallel data is loaded into the register
simultaneously and is shifted out of the register serially one bit at a time under clock
control.

iv) Parallel-in to Parallel-out (PIPO) - the parallel data is loaded simultaneously into the
register, and transferred together to their respective outputs by the same clock pulse.

6.1. Serial-In Serial-Out Shift Register:

The serial in/serial out shift register accepts data serially, i.e., one bit at a
time on a single line. It produces the stored information on its output also in serial

form.

The entry of the four bits 1010 into the register is illustrated below, beginning with the right-
most bit. The register is initially clear. The 0 is put onto the data input line, making D=0 for
FF0. When the first clock pulse is applied, FF0 is reset, thus storing the 0.
Next the second bit, which is a 1, is applied to the data input, making D=1 for FF0 and D=0
for FF1 because the D input of FF1 is connected to the Q0 output.
When the second clock pulse occurs, the 1 on the data input is shifted into FF0, causing FF0
to set; and the 0 that was in FF0 is shifted into FFl.
The third bit, a 0, is now put onto the data-input line, and a clock pulse is applied. The 0 is
entered into FF0, the 1 stored in FF0 is shifted into FFl, and the 0 stored in FF1 is shifted into
FF2.

50
 CS 3352 –DP&CO Unit II
The last bit, a 1, is now applied to the data input, and a clock pulse is applied.This time the 1
is entered into FF0, the 0 stored in FF0 is shifted into FFl, the 1 stored in FF1 is shifted into
FF2, and the 0 stored in FF2 is shifted into FF3.
This completes the serial entry of the four bits into the shift register, where they can be
stored for any length of time as long as the Flip-Flops have dc power.

bits(1010) beingentered seriallyintotheregister

To get the data out of the register, the bits must be shifted out serially and taken off the Q3
output. After CLK4, the right-most bit, 0, appears on the Q3 output.When clock pulse CLK5
is applied, the second bit appears on the Q3 output clock pulse CLK6 shifts the third bit to the
output , and CLK7 shifts the fourth bit to the output. While the original four bits are being
shifted out, more bits can be shifted in. All zeros are shown being shifted out, more bits can
be shifted in

51
 CS 3352 –DP&CO Unit II

..

6.2. Serial-In parallel-Out Shift Register:

In this shift register, data bits are entered into the register in the same as serial-in serial-out
shift register. But the output is taken in parallel. Once the data are stored, each bit appears on
its respective output line and all bits are available simultaneously instead of on a bit-by-bit.

52
 CS 3352 –DP&CO Unit II
Four bits (1111) being serially entered into the register

6.3. Parallel-In Serial-Out Shift Register:

In this type, the bits are entered in parallel i.e., simultaneously into their respective stages on
parallel lines.
A 4-bit parallel-in serial-out shift register is illustrated below. There are four data input lines,
X0, X1, X2 and X3 for entering data in parallel into the register.
SHIFT/ LOAD input is the control input, which allows four bits of data to load in parallel

53
 CS 3352 –DP&CO Unit II
into the register.
When SHIFT/LOAD is LOW, gates G1, G2, G3 and G4 are enabled, allowing each data bit
to be applied to the D input of its respective Flip-Flop. When a clock pulse is applied, the
Flip-Flops with D = 1 will set and those with D = 0 will reset, thereby storing all four bits
simultaneously.

When SHIFT/LOAD is HIGH, gates G1, G2, G3 and G4 are disabled and gates G5, G6 and
G7 are enabled, allowing the data bits to shift right from one stage to the next. The OR gates
allow either the normal shifting operation or the parallel data- entry operation, depending on
which AND gates are enabled by the level on the SHIFT/LOAD input.

6.4. Parallel-In Parallel-Out Shift Register

In this type, there is simultaneous entry of all data bits and the bits appear on parallel outputs
simultaneously

54
 CS 3352 –DP&CO Unit II

6.5. UNIVERSAL SHIFT REGISTERS

If the register has shift and parallel load capabilities, then it is called a shift register with
parallel load or universal shift register. Shift register can be used for converting serial data to
parallel data, and vice-versa. If a parallel load capability is added to a shift register, the data
entered in parallel can be taken out in serial fashion by shifting the data stored in the register.
The functions of universal shift register are:

A clear control to clear the register to 0.

A clock input to synchronize the operations.

A shift-right control to enable the shift right operation and the serial input and output
lines associated with the shift right.

A shift-left control to enable the shift left operation and the serial input and output lines
associated with the shift left.

A parallel-load control to enable a parallel transfer and the n input lines associated with
the parallel transfer.
„n‟ parallel output lines.

A control line that leaves the information in the register unchanged even though the clock
pulses re continuously applied.

It consists of four D-Flip-Flops and four 4 input multiplexers (MUX). S0 and S1 are the two
selection inputs connected to all the four multiplexers. These two selection inputs are used to
select one of the four inputs of each multiplexer.
The input 0 in each MUX is selected when S1S0= 00 and input 1 is selected when S1S0= 01.
Similarly inputs 2 and 3 are selected when S1S0= 10 and S1S0= 11 respectively. The inputs
S1 and S0 control the mode of the operation of the register.

55
 CS 3352 –DP&CO Unit II
4-Bit Universal Shift Register

When S1S0= 00, the present value of the register is applied to the D-inputs of the Flip-Flops.
This is done by connecting the output of each Flip-Flop to the 0 input of the respective
multiplexer. The next clock pulse transfers into each Flip-Flop, the binary value is held
previously, and hence no change of state occurs.
When S1S0= 01, terminal 1 of the multiplexer inputs has a path to the D inputs of the Flip-
Flops. This causes a shift-right operation with the lefter serial input transferred into Flip-Flop
FF3.
When S1S0= 10, a shift-left operation results with the right serial input going into Flip-Flop
FF1.
Finally when S1S0= 11, the binary information on the parallel input lines (I1, I2,I3 and I4)
are transferred into the register simultaneously during the next clock pulse.
The function table of bi-directional shift register with parallel inputs and parallel outputs is
shown below.
Mode Control
Operation
S1 S
0
0 0 No change
0 1 Shift-right
1 0 Shift-left
1 1 Parallel load

6.6. BI-DIRECTION SHIFT REGISTERS:

A bidirectional shift register is one in which the data can be shifted either left or right. It can
be implemented by using gating logic that enables the transfer of a data bit from one stage to
the next stage to the right or to the left depending on the level of a control line.
A 4-bit bidirectional shift register is shown below. A HIGH on the RIGHT/LEFT control
input allows data bits inside the register to be shifted to the right, and a LOW enables data
bits inside the register to be shifted to the left.
When the RIGHT/LEFT control input is HIGH, gates G1, G2, G3 and G4 are enabled, and
the state of the Q output of each Flip-Flop is passed through to the D input of the following
Flip-Flop. When a clock pulse occurs, the data bits are shifted one place to the right.

When the RIGHT/LEFT control input is LOW, gates G5, G6, G7 and G8 are enabled, and the
Q output of each Flip-Flop is passed through to the D input of the preceding Flip-Flop. When
a clock pulse occurs, the data bits are then shifted one place to the left
.

56
 CS 3352 –DP&CO Unit II

4-bit bi-directional shift register

7. Design of asynchronous counters

1. In this counter, all the flip-flops are not under the control of single clock.
2. Here the clock pulse is applied to the first (LSB) flip-flop, and the successive flip-flop
is triggered by the output of the previous flip-flops.
3. Therefore, this counter has cumulative timing.
4. As the triggers move through the flip-flops like a ripple, it is called a ripple counter

April/May 2011 (16 Marks)

Example 5.8.BCD Ripple Counter (Decade Ripple counter)
A decimal counter follows a sequence of 10 states and returns to 0 after the count of 9.
The sequence of states in a decimal counter is dictated by the binary code used to represent a
decimal digit.
If BCD is used, the sequence of states is as shown in the state diagram.

A decimal counter is similar to a binary counter, except that the state after 1001 (the code for
decimal digit 9) is 0000 (the code for decimal digit 0).
The logic diagram of a BCD ripple counter using JK flip‐flops is shown in Figure.
The four outputs are designated by the letter symbol Q, with a numeric subscript equal to the
binary weight of the corresponding bit in the BCD code.
The output of Q1 is applied to the Clock inputs of both Q2 and Q8 and the output of Q2 is
applied to the Clock input of Q4.
The J and K inputs are connected either to a permanent 1 signal

57
 CS 3352 –DP&CO Unit II
or to outputs of other flip‐flops.
A ripple counter is an asynchronous sequential circuit.
Signals that affect the flip‐flop transition depend on the way
they change from 1 to 0.
Operation of the counter
When the C input goes from 1 to 0,
The flip‐flop is set if J = 1,
is cleared if K = 1,
is complemented if J = K = 1,
and is left unchanged if J = K = 0.
Q1 changes state after each clock pulse.
Q2 complements every time Q1 goes from 1 to 0, as long as
Q8 = 0.When Q8 becomes 1, Q2 remains at 0.
Q4 complements every time Q2 goes from 1 to 0.
Q8 remains at 0 as long as Q2 or Q4 is 0.
When both Q2 and Q4 become 1, Q8 complements when Q1
goes from 1 to 0. Q8 is cleared on the next transition of Q1.

7.1. Asynchronous Up counter:

3 bit asynchronous binary counter using positive edge triggered JK flip flop
When flip flops are positively edge triggered, the Q‟ output of the previous stage is connected
to the clock input of the next stage.

JK of all the three FFs are connected to high input ie logic 1.initially output of all the flip
flops are at logic low (ie reset condition).

Output waveform

Q0 – LSB Q2 –MSB . so the sequence obtained is

000,001,010,011,100,101,110,111,000,….

58
 CS 3352 –DP&CO Unit II

Hint :
1. if the FF is negative edge triggered means connect Q output of first FF into clock
input of next FF.
2. Instead of JK FF we can use T FF with T input connected to logic 1.

7.2. Asynchronous down counter

When flip-flops are positive edge triggered, the Q‟ output of the previous stage is connected
to the clock input of the next stage.
Fig shows the 3-bit asynchronous down counter with positive edge triggered FF.

7.3.4- Bit asynchronous down counter with negative edge triggered FF.

59
 CS 3352 –DP&CO Unit II

7.4.Asynchronous UP-DOWN counter:

1. The UP-DOWN counter is a combination of the up-counter and the down-counter.
2. As the up-down counter has the capability of counting upwards as well as downwards,
it is also called multi-mode counter.
3. In an UP-counter, each flip-flop is triggered by the normal output of the preceding
flip-flop.
4. In a DOWN-counter, each flip-flop is triggered by the inverted output of the
preceding flip-flop.
5. In both the counters, the first (LSB) flip-flop is triggered by the clock pulse.
6. When the Count-up line is held at 1 while the count-down line is at 0, the lower AND
gates (2,4,6) will be disabled and their outputs are zero. So it will have no effect on
the outputs of OR gates.
7. Also, the Upper AND gates (1,3,5) will be enabled, i.e., it will allow QD to pass
through the OR gate and into the clock input of the C flip-flop.

The

counting sequence of up/down counter in the two modes of counting is given in table
COUNT – UP Mode COUNT – DOWN Mode

States QA QB QC QD States QA QB QC QD

0 0 0 0 0 15 1 1 1 1

1 0 0 0 1 14 1 1 1 0

2 0 0 1 0 13 1 1 0 1

3 0 0 1 1 12 1 1 0 0

4 0 1 0 0 11 1 0 1 1

5 0 1 0 1 10 1 0 1 0

6 0 1 1 0 9 1 0 0 1

7 0 1 1 1 8 1 0 0 0

8 1 0 0 0 7 0 1 1 1

60
 CS 3352 –DP&CO Unit II
9 1 0 0 1 6 0 1 1 0

10 1 0 1 0 5 0 1 0 1

11 1 0 1 1 4 0 1 0 0

12 1 1 0 0 3 0 0 1 1

13 1 1 0 1 2 0 0 1 0

14 1 1 1 0 1 0 0 0 1

15 1 1 1 1 0 0 0 0 0

0 0 0 0 0 15 1 1 1 1

61