Southeast University (SEU)

Department of Computer Science & Engineering (CSE)

LAB REPORT

Course Title: Digital Logic Design Lab

Course Code: CSE 264.1

Submitted By :

Name:Lamisa Sobnom Faria ID: 2019000000097

Submitted To:
Mahnuma Rahman Rinty
Lecturer,Department of CSE,
Southeast University
 Table of Contents:

Experiment no:01 2
Experiment no:02 17
Experiment no:03 33
Experiment no:04 46
Experiment no:05 53
Experiment no:06 63
 Experiment no:01

Name of the experiment: An experiment to simulate the seven types of logic

gates

1. AND gate.
2. OR gate.
3. NOT gate.
4. NAND gate.
5. NOR gate.
6. X-OR gate.
7. X-NOR gate.

Objective:To know how different types of logic gates can be implemented and
also to know how they work.

(01)

AND gate:

The AND gate is a basic digital logic gate that implements logical
conjunction (∧) from mathematical logic. The Logic diagram of AND gate is given
below:
Logic diagram:

Figure:AND Gate

Theory:

An AND gate is a digital logic gate with two or more inputs and one output
that performs logical conjunction. The output of an AND gate is true only when all
of the inputs are true. If one or more of an AND gate's inputs are false, then the
output of the AND gate is false.if the inputs applied to it are all 1, then the output
will be 1. An AND gate is an electrical circuit that combines two signals so that the
output is on if both signals are present.A HIGH output (1) results only if all the
inputs to the AND gate are HIGH (1). If not all inputs to the AND gate are HIGH,
LOW output results. The AND gate with inputs A and B and output C implements
the logical expression C= A.B
Truth table:

Input Output

A B C=A.B

0 0 0

0 1 0

1 0 0

1 1 1

Result:
From the logic diagram we see,

When A=0 and B=0 then the output will be also 0

When A=0 and B=1 then the output will be 0

When A=1 and B=0 then the output will be 0

When A=1 and B=1 then the output will be 1

Discussion:
We have successfully run the simulation of the AND gate. In this gate we
have added two inputs and got the required output.
 (02)

OR gate:

The OR gate is a digital logic gate that implements logical disjunction (∨)
from mathematical logic .The Logic diagram of OR gate is given below:

Logic diagram:

Figure:OR gate

Theory:

The function of an OR gate is to find the maximum between the

inputs which are binary in nature. It is one of the basic gates used in
Boolean algebra and electronic circuits like transistor-transistor logic, and
complementary metal-oxide semiconductors make use of it.Its output is
"true" if both inputs are "false." Otherwise, the output is "false." If all the
inputs are low, then and only then the output will be low.it behaves
according to the truth table.The OR gate with inputs A and B and output C
implements the logical expression C= A+B.
Truth table:

Input Output

A B C=A+B

0 0 0

0 1 1

1 0 1

1 1 1

Result:
From the logic diagram we see,

When A=0 and B=0 then the output will be also 0

When A=0 and B=1 then the output will be 1

When A=1 and B=0 then the output will be 1

When A=1 and B=1 then the output will be 1

Discussion:
We have successfully run the simulation of the OR gate. In this gate we have
added two inputs and got the required output.
 (03)

NOT gate: In digital logic, an inverter or NOT gate is a logic gate which
implements logical negation.The Logic diagram of NOT gate is given below:

Logic diagram:

Figure:NOT Gate

Theory:

A NOT gate uses just one input to generate one output. A NOT gate inverts
the input - the output is 1 (TRUE) if the input is 0 (FALSE), and the output is 0
(FALSE) if the input is 1 (TRUE).The logical expression of NOT gate is,if the input is
A then the output will be A’.So, the expression is, A=A’.
Truth table:

Input Output

A A=A’

0 1

1 0

Result:
From the logic diagram we see,

When A=0 and B=0 then the output will be 1

When A=1 then the output will be 0

Discussion:
We have successfully run the simulation of the NOT gate. In this gate we
have added one input and got the required output.

(04)
NAND gate:

NAND gate is considered as an "universal" gate in Boolean algebra as it is

capable of producing all other logic gates.The Logic diagram of NAND gate is given
below:
Logic diagram:

Figure: NAND Gate

Theory:

A NAND gate is a logic gate which produces an output which is false only if
all its inputs are true; thus its output is complementary to that of an AND gate. A
LOW output results only if all the inputs to the gate are HIGH; if any input is LOW,
a HIGH output results.A NAND Gate is a logical gate which is the opposite of an
AND logic gate. It is a combination of AND and NOT gates and is a commonly used
logic gate.The NAND gate with inputs A and B and output C implements the logical
expression C= (A.B)’.

Truth table:

Input Output

A B C=(A.B)’

0 0 1
 0 1 1

1 0 1

1 1 0

Result:
From the logic diagram we see,

When A=0 and B=0 then the output will be 1

When A=0 and B=1 then the output will be 1

When A=1 and B=0 then the output will be 1

When A=1 and B=1 then the output will be 0

Discussion:
We have successfully run the simulation of the NAND gate. In this gate we
have added two inputs and got the required output.
 (05)

NOR gate:

NOR gate is an universal gate.It can create any logical Boolean expression.
The Logic diagram of NOR gate is given below:

Logic diagram:

Figure: NOR gate

Theory:

A NOR gate is a digital logic gate that gives an output of 0 when any of its
inputs are 1, otherwise 1. NOR gates can be made to produce a variety of logic
gates, including OR and AND gates. The output of the NOR gate is a logic 0 as long
as the input voltage is below the threshold.NOR gate is used to construct the basic
gates similar to AND gate. By combining NOT gate and OR gate, NOR gate can be
constructed. The NOR gate is a digital logic gate that implements logical NOR - it
behaves according to the truth table. The NOR gate with inputs A and B and
output C implements the logical expression C= (A+B)’.
Truth table:

Input Output

A B C=(A+B)’

0 0 1

0 1 0

1 0 0

1 1 0

Result:
From the logic diagram we see,

When A=0 and B=0 then the output will be 1

When A=0 and B=1 then the output will be 0

When A=1 and B=0 then the output will be 0

When A=1 and B=1 then the output will be 0

Discussion:
We have successfully run the simulation of the NOR gate. In this gate we
have added two inputs and got the required output.
 (06)

X-OR gate:

An XOR gate implements an exclusive or from mathematical logic.The Logic

diagram of XOR gate is given below:

Logic diagram:

Figure:X-OR gate

Theory:

XOR gate is a digital logic gate that gives a true output when the number of
true inputs is odd. If both inputs are false (0/LOW) or both are true, a false output
results. XOR represents the inequality function, i.e., the output is true if the inputs
are not alike otherwise the output is false. A way to remember XOR is "must have
one or the other but not both".The X-OR gate with inputs A and B and output C
implements the logical expression,C= A ⊕ B.
Truth table:

Input Output

A B C= A ⊕ B

0 0 0

0 1 1

1 0 1

1 1 0

Result:
From the logic diagram we see,

When A=0 and B=0 then the output will be 0

When A=0 and B=1 then the output will be 1

When A=1 and B=0 then the output will be 1

When A=1 and B=1 then the output will be 0

Discussion:
We have successfully run the simulation of the X-OR gate. In this gate we
have added two inputs and got the required output.
 (07)
X-NOR gate:

The X-NOR gate is a digital logic gate whose function is the logical
complement of the Exclusive OR gate.The Logic diagram of X-NOR gate is given
below:

Logic diagram:

Figure: X-NOR Gate

Theory:

An X-NOR gate is a digital logic gate with two or more inputs and one
output that performs logical equality. The output of an XNOR gate is true when all
of its inputs are true or when all of its inputs are false. If some of its inputs are
true and others are false, then the output of the X-NOR gate is false.An XNOR gate
is also called exclusive NOR gate or XNOR gate. In a two-input XNOR gate, the
output is high (logic 1 or true) when two inputs are the same.The X-NOR gate with
inputs A and B and output C implements the logical expression C= A ⊙ B.
Truth table:

Input Output

A B C= A ⊙ B

0 0 1

0 1 0

1 0 0

1 1 1

Result:
From the logic diagram we see,

When A=0 and B=0 then the output will be 1

When A=0 and B=1 then the output will be 0

When A=1 and B=0 then the output will be 0

When A=1 and B=1 then the output will be 1

Discussion:
We have successfully run the simulation of the X-NOR gate. In this gate we
have added two inputs and got the required output.
 Experiment no:02

Name of the experiment:

An experiment to simulate the two logic circuit of

1. SR flip-flop,
2. JK flip-flop,
3. D flip-flop and
4. T flip-flop

Objective:

To know how different types of logic circuits can be implemented and also
to know how they work.

(01)

SR Flip-Flop :

A flip-flop circuit can remain in a binary state indefinitely until directed by

an input signal to switch states or clock.

S-R flip-flop stands for SET-RESET flip-flops.

The SET-RESET flip-flop consists of two NOR gates and also two NAND gates.

These flip-flops are also called S-R Latch.

Circuit diagram:

Theory:

SR flip-flop is the simplest possible memory element. It can be constructed

from two NAND gates or two NOR gates. Let us understand the operation of the
SR flip-flop using NAND gates as shown below using the truth table for ‘A NOR B’
gate. The inputs S And R are referred to as the set and Reset inputs, respectively.
The outputs Q and Q' are complements of each other and are referred to as the
normal and complement outputs, respectively. The circuit shown below is a basic
NAND latch. Because the NAND inputs must normally be logic 1 to avoid affecting
the latching action, the inputs are considered to be inverted in this circuit (or
active low).
Truth Table :

S R Q Q’

0 0 x x

0 1 0 1

1 0 1 0

1 1 x x

When we use the inputs as S = 0, R = 1, irrespective of the value of Q’, the

next state output of NAND gate A is logic HIGH, i.e Q = 1, which will SET the flip
flop. So the two inputs of NAND gate B are R’ = 1 and Q = 1. The output thus
produced is Q’ = 0.

For the inputs S = 1, R = 0, irrespective of the values of Q, the next state output of
NAND gate B is logic HIGH, i.e, Q’ = 1. The two inputs for NAND gate A are S = 1
and Q’ = 1, producing an output Q = 0, which will RESET the flip flop.

Result :
Discussion:

We have successfully run the simulation of the SR Flip-Flop . In this decoder

we have added 2 inputs and we have got the required outputs
 (02)

JK Flip-Flop :

The JK flip flop is one of the most used flip flops in digital circuits. The JK flip flop is
a universal flip flop having two inputs 'J' and 'K'. In SR flip flop, the 'S' and 'R' are
the shortened abbreviated letters for Set and Reset, but J and K are not. The J and
K are themselves autonomous letters which are chosen to distinguish the flip flop
design from other types.

Circuit diagram:

Theory:

The JK flip flop is basically a gated SR flip-flop with the addition of a clock
input circuitry that prevents the illegal or invalid output condition that can occur
when both inputs S and R are equal to logic level “1”. Due to this additional
clocked input, a JK flip-flop has four possible input combinations, “logic 1”, “logic
0”, “no change” and “toggle”. The symbol for a JK flip flop is similar to that of an
Bistable Latch as seen in the previous tutorial except for the addition of a clock
input.
Truth Table :

Clock J K Q Q’

↑ 0 0 Undefine

↑ 0 1 0 1

↑ 1 0 1 0

↑ 1 1 Toggle (1)

Here J = S and K = R. The two-input AND gates of the RS flip-flop is replaced

by the two 3 inputs NAND gates with the third input of each gate connected to the
outputs at Q and Ǭ. This cross-coupling of the RS Flip-Flop is used to produce
toggle action. As the two inputs are interlocked.

If the circuit is in the “SET” condition, the J input is inhibited by the status 0 of Q
through the lower NAND gate. Similarly, the input K is inhibited by 0 status of Q
through the upper NAND gate in the “RESET” condition. When both J and K are at
logic “1”, the JK Flip Flop toggle.
Result:
Discussion:

We have successfully run the simulation of the JK Flip-Flop . In this decoder we

have added 3 inputs and we have got the required outputs
 (03)

D Flip-Flop:

A D (or Delay) Flip Flop (Figure 1) is a digital electronic circuit used to delay
the change of state of its output signal (Q) until the next rising edge of a clock
timing input signal occurs.

Circuit diagram:

Theory:

The D flip flop is the most important flip flop from other clocked types. It
ensures that at the same time, both the inputs, i.e., S and R, are never equal to 1.
The Delay flip-flop is designed using a gated SR flip-flop with an inverter
connected between the inputs allowing for a single input D(Data).

This single data input, which is labeled as "D" used in place of the "Set"
input and for the complementary "Reset" input, the inverter is used. Thus, the
level-sensitive D-type or D flip flop is constructed from a level-sensitive SR flip
flop. So, here S=D and R= ~D(complement of D)
Truth Table :

Clock D Q Q’

↓ 0 Q Q’

↓ 1 Q Q’

↑ 0 0 1

↑ 1 1 0

When EN=0, irrespective of D-input, the R = S = 0 and the state is held. When EN=
1, the S input of the RS flip-flop equals the D input and R is the inverse of D.
Hence, output Q follows D, when EN= 1. When EN returns to 0, the most recent
input D is ‘remembered'.

Result:
Discussion:

We have successfully run the simulation of the D Flip-Flop . In this

decoder we have added 2 inputs and we have got the required outputs
 (04)

T Flip Flop :

The T flip-flop is a single input version of the JK flip-flop. The T flip-flop is obtained
from the JK type if both inputs are tied together.

Circuit diagram:

Theory:

In T flip flop, "T" defines the term "Toggle". In SR Flip Flop, we provide only a
single input called "Toggle" or "Trigger" input to avoid an intermediate state
occurrence. Now, this flip-flop works as a Toggle switch. The next output state is
changed with the complement of the present state output. This process is known
as "Toggling"'.

We can construct the "T Flip Flop" by making changes in the "JK Flip Flop". The "T
Flip Flop" has only one input, which is constructed by connecting the input of the
JK flip flop. This single input is called T. In simple words, we can construct the "T
Flip Flop" by converting a "JK Flip Flop". Sometimes the "T Flip Flop" is referred to
as a single input "JK Flip Flop".

The toggle, or T, flip-flop is a bistable device, where the output of the T flip-flop
"toggles" with each clock pulse. Till CP=0, the output is in hold state (three input
AND gate principle). When CP=1, for T=0, previous output is memorized by the
circuit. When T=1 along with the clock pulse, the output toggles from the previous
value as given in the characteristic table below.

Truth Table :

Clock T Q Q’

↓ 0 0 0

↓ 1 0 1

↑ 0 1 0

↑ 1 1 0

○ If J = K = 1, the flip-flop switches at each rising edge of Clk between the

results.

○ If J = K = 0, the result is stored.

Result:

Discussion:

We have successfully run the simulation of the T Flip-Flop . In this decoder we

have added 2 inputs and we have got the required outputs.
 Experiment no:03
Name of the experiment:

An experiment to simulate the logic circuit of

1. Full adder using two half adder

2. 4-bit Parallel adder
3. Full subtractor

Objective:

To know how to implement;

1. Full adder using two half adder

2. 4-bit Parallel adder

3. Full subtractor in practical life and also to know how they work.

(01)

Full adder using two half adders:

Two Half Adders and an OR gate is required to implement a Full Adder.The

circuit diagram of Full adder using two half adder is given below:
Circuit diagram:

Figure:Full adder using two half adder

Theory:

A full adder is a digital circuit that performs addition. Full adders are
implemented with logic gates in hardware. A full adder adds three one-bit binary
numbers, two operands and a carry bit. The adder outputs two numbers, a sum
and a carry bit. The term is contrasted with a half adder, which adds two binary
digits. A full adder circuit has three binary digit inputs (two input bits and one
carry input bit) and two binary digit outputs, Sum bit and carry output bit.Full
Adders are used in ALU- Arithmetic Logic Unit. In order to generate memory
addresses inside a computer and to make the Program Counter point to the next
instruction, the ALU makes use of Full Adders. Full-Adders are a part of the
Graphics Processing Unit for graphics related applications. Full Adder is the adder
which adds three inputs and produces two outputs. The first two inputs are A and
B and the third input is an input carry as C-IN. The output carry is designated as
C-OUT and the normal output is designated as S which is SUM.A full adder logic is
designed in such a manner that can take eight inputs together to create a
byte-wide adder and cascade the carry bit from one adder to the another. The
expression will be, S=A⊕B⊕C ; Cout=A.B+(A⊕B).Cin

Truth table:

Input Output

A B Cin S Cout

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1
From the truth table we see,

When A=0 and B=0 & Cin=0 then we get S= 0 & Cout=0

When A=0 and B=0 & Cin=1 then we get S= 1 & Cout=0

When A=0 and B=1 & Cin=0 then we get S= 1 & Cout=0

When A=0 and B=1 & Cin=1 then we get S= 0 & Cout=1

When A=1 and B=0 & Cin=0 then we get S= 1 & Cout=0

When A=1 and B=0 & Cin=1 then we get S= 0 & Cout=1

When A=1 and B=1 & Cin=0 then we get S= 0 & Cout=1

When A=1 and B=1 & Cin=1 then we get S= 1 & Cout=1
Result:

Figure:Full adder using two half adder

Discussion:

We have successfully run the simulation of the Full adder using two half adders.
In this full adder we have added 3 inputs and we have got the required outputs.

(02)

4-Bit Parallel Adder:

A parallel adder is an arithmetic combinational logic circuit that is used to add
more than one bit of data simultaneously. The circuit diagram of 4-Bit Parallel Adder
is given below:

Circuit diagram:

Figure:4-Bit Parallel Adder

Theory:

A Parallel Adder is a digital circuit capable of finding the arithmetic sum of

two binary numbers that is greater than one bit in length by operating on
corresponding pairs of bits in parallel.The Parallel binary adder is a combinational
circuit consists of various full adders in parallel structure so that when more than
1-bit numbers are to be added, then there can be full adder for every column for
the addition. This can be done by cascading four full adder circuits as shown in the
diagram. The least significant bits A 0, B 0, and C 0 are added to the product sum
output S 0 and carry output C 1. Carry output C 1 is then added to the next
significant bits A 1 and B 1 producing sum output S 1 and carry output C 2. C 2 is
then added to A 2 and B 2 and so on. Thus finally producing the four-bit sum
output S 3S 2S 1S 0 and final carry output Cout.

Truth table:

Input Output

Cin A3 A2 A1 A0 B3 B2 B1 B0 S3 S2 S1 S0 Cout
0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 1 0 0 0 1 0 0 1 0 0
0 0 0 1 0 0 0 1 0 0 1 0 0 0
0 0 0 1 1 0 0 1 1 0 1 1 0 0
0 0 1 0 0 0 0 0 0 1 0 0 0 0
0 0 1 0 1 0 0 0 1 1 0 1 0 0
0 0 1 1 0 0 0 1 0 1 1 0 0 0
0 0 1 1 1 0 0 1 1 1 1 1 0 0
0 1 0 0 0 1 1 0 0 0 0 0 0 1
0 1 0 0 1 1 1 0 1 0 0 1 0 1
0 1 0 1 0 1 1 1 0 0 1 0 0 1
0 1 0 1 1 1 1 1 1 0 1 1 0 1
0 1 1 0 0 1 1 0 0 1 0 0 0 1
0 1 1 0 1 1 1 0 1 1 0 1 0 1
0 1 1 1 0 1 1 1 0 1 1 0 0 1
0 1 1 1 1 1 1 1 1 1 1 1 0 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1

From the diagram we see, to get the output it follows according to the truth table.
Result:
Discussion:
We have successfully run the simulation of the parallel adder. In this

parallel adder after given the input we have got the required output.
 (03)

Full Subtractor:
A full subtractor is a combinational circuit that performs subtraction of
two bits.The circuit diagram of Full subtractor is given below:

Circuit diagram:

Figure:Full Subtractor

Theory:

A full subtractor is a combinational circuit that performs subtraction

involving three bits, namely A (minuend), B (subtrahend), and Bin (borrow-in) . It
accepts three inputs: A (minuend), B (subtrahend) and a Bin (borrow bit) and it
produces two outputs: D (difference) and Bout (borrow out).A full subtractor is a
combinational circuit that performs subtraction of two bits, one is minuend and
other is subtrahend, taking into account borrow of the previous adjacent lower
minuend bit. This circuit has three inputs and two outputs. The three inputs A, B
and Bin, denote the minuend, subtrahend, and previous borrow, respectively. The
two outputs, D and Bout represent the difference and output borrow,
respectively.The expression will be, D = A ⊕ B ⊕ Bin ,Bout = A' Bin + A' B + B Bin

Truth table:

Input Output

A B Bin D Bout

0 0 0 0 0

0 0 1 1 1

0 1 0 1 1

0 1 1 0 1

1 0 0 1 0

1 0 1 0 0

1 1 0 0 0

1 1 1 1 1

From the truth table we see,

When A=0 and B=0 & Bin=0 then we get D= 0 & Bout=0

When A=0 and B=0 & Bin=1 then we get D= 1 & Bout=1

When A=0 and B=1 & Bin=0 then we get D=1 & Bout=1

When A=0 and B=1 & Bin=1 then we get D= 0 & Bout=1

When A=1 and B=0 & Bin=0 then we get D= 1 & Bout=0

When A=1 and B=0 & Bin=1 then we get D= 0 & Bout=0

When A=1 and B=1 & Bin=0 then we get D= 0 & Bout=0
When A=1 and B=1 & Bin=1 then we get D= 1 & Bout=1

Result:

Discussion:

We have successfully run the simulation of the Full Subtractor. In this full
subtractor we have added 3 inputs and we have got the required outputs.
 Experiment no:04

Name of the experiment:

An experiment to simulate the logic circuit of

1. 2 to 4 Decoder
2. 4 to 2 Encoder

Objective:

To know how to implement;

1.2 to 4 Decoder
2.4 to 2 Encoder in practical life and also to know how they work.

(01)
2 to 4 Decoder:
2 to 4 Decoder has two inputs A & B and four outputs D0, D1, D2 & D3. The
circuit diagram of 2 to 4 Decoder is given below:
Circuit diagram:
 Figure:2 to 4 Decoder

Theory: The 2 to 4 decoder depicted above consists of an array of four AND gates.
The 2 binary inputs labeled A and B are decoded into one of 4 outputs, hence the
description of 2-to-4 binary decoder. Each output represents one of the minterms
of the 2 input variables. The binary inputs A and B determine which output line
from D0 to D3 is “HIGH” at logic level “1” while the remaining outputs are held
“LOW” at logic “0” so only one output can be active (HIGH) at any one time.
Therefore, whichever output line is “HIGH” identifies the binary code present at
the input, in other words, it “decodes” the binary input.Some binary decoders
have an additional input pin labeled “Enable” that controls the outputs from the
device. This extra input allows the outputs of the decoder to be turned “ON” or
“OFF” as required. The output is only generated when the Enable input has value
1; otherwise, all outputs are 0. Only a small change in the implementation is
required: the Enable input is fed into the AND gates which produce the outputs.

If Enable is 0, all AND gates are supplied with one of the inputs as 0 and hence no
output is produced. When Enable is 1, the AND gates get one of the inputs as 1,
and now the output depends upon the remaining inputs. Hence the output of the
decoder is dependent on whether the Enable is high or low.The output values will
be:
D0 =A’B’

D1=A’B

D2=AB’

D3=AB

Truth table:

Input Output

A B D3 D2 D1 D0

0 0 0 0 0 1

0 1 0 0 1 0

1 0 0 1 0 0

1 1 1 0 0 0

Result:
Discussion:

We have successfully run the simulation of the 2 to 4 Decoder. In this

decoder we have added 2 inputs and we have got the required outputs.
 (02)
4 to 2 Encoder:
4 to 2 encoder consists of 4 input lines and 2 output lines. When any of the
input lines becomes 1, we get corresponding binary at the output lines.The circuit
diagram of 4 to 2 Encoder is given below:

Circuit diagram:

Figure:4 to 2 Encoder

Theory:
 An Encoder is a combinational circuit that performs the reverse operation of
Decoder.an encoder is a sensing device that provides feedback. An encoder is a
combinational circuit that converts binary information in the form of 2N input
lines into N output lines, which represent N bit code for the input. For simple
encoders, it is assumed that only one input line is active at a time. The 4 to 2
Encoder consists of four inputs E3, E2, E1 & E0 and two outputs A & B. At any
time, only one of these 4 inputs can be '1' in order to get the respective binary
code at the output.

Truth table:

INPUT OUTPUT

E3 E2 E1 E0 A B

0 0 0 1 0 0

0 0 1 0 0 1
 0 1 0 0 1 0

1 0 0 0 1 1

From the truth table, we can find logic expressions for A and B as following,

A=E3+E2

B=E3+E1

Result:

Discussion:

We have successfully run the simulation of the4 to 2 encoder. In this

encoder we have added 4 inputs and we have got the required outputs.
 Experiment no:05
Name of the experiment:

An experiment to simulate the logic circuit of

1. 4:1 MUX using 2:1 MUX

2. 1:4 DEMUX

Objective:

To know how to implement;

1. 4:1 MUX using 2:1 MUX

2. 1:4 DEMUX in practical life and also to know how they work.

(1)

4:1 MUX using 2:1 MUX:

A multiplexer is a device that takes multiple analog signals and forwards

the selected input into a single line. These devices are used to increase the
amount of data that can be transmitted over a network.The circuit diagram of 4:1
MUX using 2:1 MUX is given below:
Circuit diagram:

Figure:4:1 Mux

Theory:

In electronics, a multiplexer, also known as a data selector, is a device that

selects between several analog or digital input signals and forwards the selected
input to a single output line. The selection is directed by a separate set of digital
inputs known as select lines.A multiplexer is a device that can transmit several
digital signals on one line by selecting certain switches.in a 2×1 multiplexer, there
is one select switch and two data lines. You can select a data line by setting a
switch to 0 or 1.When S1 is set to HIGH it will select i1 and i3 now if s0 is LOW

output will have i1 otherwise i3 and similar for i0 and i2.

Truth table:

S0 S1 Y

0 0 i0

0 1 i1

1 0 i2

1 1 i3

Theory:

In electronics, a multiplexer, also known as a data selector, is a device that

selects between several analog or digital input signals and forwards the selected
input to a single output line. The selection is directed by a separate set of digital
inputs known as select lines.A multiplexer is a device that can transmit several
digital signals on one line by selecting certain switches.in a 2×1 multiplexer, there
is one select switch and two data lines. You can select a data line by setting a
switch to 0 or 1.When S1 is set to HIGH it will select i1 and i3 now if s0 is LOW
output will have i1 otherwise i3 and similar for i0 and i2.
Result:
Discussion:

We have successfully run the simulation of the 4:1 MUX using 2:1 MUX. In
this mux we have added inputs and we have got the required outputs.
 (02)
1:4 DEMUX: Demux (Demultiplexer)used in communication systems to carry
multiple data signals (i.e. audio, video etc) using a single line for transmission. In
this easier process, Demultiplexer receives the output data of Multiplexer (as a
receiver) and converts them back to the original form then.The circuit diagram of
1:4 DEMUX is given below:
Circuit diagram:

Figure:1:4 Demux

Theory:

Demultiplexer performs the reverse operation of the multiplexer i.e. it takes

a single output and can guide that single output through many outputs. The
output to which the input signal is to be passed is decided by the control logic.
The control logic can be manipulated by changing the value of the control signal.
The demultiplexer can be digital as well as analogue depending on the type of
input and output.The 1:4 Demultiplexer consists of 1 input signal, 2 control signals
and 4 output signals. The number of the output signal is always decided by the
number of the control signal and vice versa.There are 2 NOT gates through which
control signals are passed, and 4 AND gates, which decides or control the output.
The combination of the input signal along with control signals will decide the
output through which the input signal will pass through.When X=0, then the
control input’s(S0,S1) output is also 0.Again,when X=1,then it depends on control
input & output is also depends on the control input.

Truth table:

Input Output

X S0 S1 D3 D2 D1 D0

0 0 0 0 0 0 0

0 0 1 0 0 0 0

0 1 0 0 0 0 0

0 1 1 0 0 0 0

1 0 0 0 0 0 1

1 0 1 0 0 1 0

1 1 0 0 1 0 0

1 1 1 1 0 0 0
Result:
Discussion:

We have successfully run the simulation of the 1:4 Demux. In this demux we
have added inputs and we have got the required outputs.
 Experiment no:06

Name of the experiment:

An experiment to simulate the two logic circuit of

1. Synchronous Up Counter and

2. Asynchronous Up Counter

Objective:

To know how different types of logic circuits can be implemented and also
to know how they work.

Synchronous Up Counter :

The synchronous counter is a type of counter in which the clock signal is

simultaneously provided to each flip-flop present in the counter circuit. More
specifically, we can say that each flip-flop is triggered in synchronism with the
clock input.the synchronous up counter capable of counting up through any given
count sequence at any point within their count sequence which is limited by the
input bit length.
Circuit diagram:

Theory:

The basic idea here is to keep the J and K inputs of each flip flop high, such
that the flip flop will toggle with any negative clock transition at its clock input. We
then use AND gates to gate every second clock to flip flop B, every fourth clock to
flip flop C, and so on. This logic configuration is later referred to as “steering logic”
Since the clock pulses are gated or steered to each individual flip flop. The clock is
applied directly to flip flop A. Since the JK flip flop used responds to a negative
transition at the clock input and toggles when both the J and K input are high. Flip
flop A will change state with each negative clock transition. Whenever A is high.
AND gate X is enabled and a clock pulse is passed through the gate to the clock
input of flip flop B. Thus B changes state with every other negative clock transition
at points b, d, f and h on the timeline. Since AND gate y is enabled and will
transmit the clock to flip flop C only. When both A and B are high. Flip flop C
changes state with every fourth negative clock transition at points d and h on the
timeline. Examination of the waveform and the truth table reveals that this
counter progresses upward in a natural binary sequence from count 000 up tcount
111, advancing One count with each negative clock transition. This is a mode 8
parallel or synchronous, binary counter operating in the count up mode.

Truth Table:

State A B C D

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 1 1 1 1

8 1 0 0 0

9 1 0 0 1

10 1 0 1 0

11 1 0 1 1

12 1 1 0 0

13 1 1 0 1

14 1 1 1 0

15 1 1 1 1
Result:

Discussion:

We have successfully run the simulation of the Synchronous Up Counter

using jk flip flop. In this decoder we have added 1 inputs and we have got the
required outputs
 (02)
Asynchronous Up Counter :

Asynchronous counters are those counters which do not operate on

simultaneous clocking. In an asynchronous counter, only the first flip-flop is
externally clocked using a clock pulse while the clock input for the successive
flip-flops will be the output from a previous flip-flop. the asynchronous up counter
the output is taken at the non-inverting output ports of the flip-flops.

Circuit diagram:

Theory:

The 3-bit Asynchronous binary up counter contains three T flip-flops and

the T-input of all the flip-flops are connected to ‘1’. All these flip-flops are negative
edge triggered but the outputs change asynchronously. The clock signal is directly
applied to the first T flip-flop. So, the output of first T flip-flop toggles for every
negative edge of the clock signal. The output of the first T flip-flop is applied as a
clock signal for the second T flip-flop. So, the output of the second T flip-flop
toggles for every negative edge of output of the first T flip-flop. Similarly, the
output of the third T flip-flop toggles for every negative edge of output of second
T flip-flop, since the output of second T flip-flop acts as the clock signal for third T
flip-flop.

Truth Table:

State A B C D

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 1 1 1 1

8 1 0 0 0

9 1 0 0 1

10 1 0 1 0

11 1 0 1 1

12 1 1 0 0

13 1 1 0 1

14 1 1 1 0

15 1 1 1 1
Since A acts as the clock for B, each time the waveform at A goes low, flip flop B
will toggle. Thus at point b on the timeline, B goes high ;it then goes low at the
point d and toggles back high again at point f. Notice that the wave from at the
output of flip flops one –half the frequency of A and one –fourth the clock
frequency . Since B acts as the clock for C, Each time the waveform at B goes low,
flip flop C will toggle. Thus C goes high at point d on the timeline and goes back
low again at point h. Since C acts as the clock for D, Each time the waveform at C
goes low, flip flop D will toggle. The frequency of the waveform at D is one half
that at C, But it is only one either the clock frequency

Result:
Discussion:

We have successfully run the simulation of the Asynchronous Up Counter

using a flip flop. In this decoder we have added 1 input and we have got the
required outputs.

__________________________The End__________________________