PRACTICAL FILE

Computer Organization And Architecture

Submitted For
Bachelor Of Technology In
Computer Science And Engineering

Institute of Technology Gopeshwar

(Department of Computer Science and
Engineering)

Submitted By:
Submitted To: Name : Sapna Bangari
Mrs. Monika Bartwal Year/Sem: 2nd / 4th
Assistant Professor Roll Number:
(C.S.E Department) 201340101040
 INDEX

Ex. Experiment
Number
1 Bread Board Implementation of Flip-Flops.

2 Bread Board Implementation of Counters and Shift

register.

3 Determination of delay time AND , NAND , OR ,

NOR X-OR gates.

4 Experiment with clocked flip-flop.

5 Design of counters.

6 Implementation of arithmetic algorithms.

7 Bread Board Implementation of binary adder-

subtractor .

8 To design and set up the following adder/

subtractor circuit using an IC 7483.

9 Demultiplexer/Decoder operation using IC-M138.

 Experiment NO.1

Aim :- Bread Board Implementation of Flip-Flops.

APPARATUS REQUIRED : - IC -7400, IC- 7404, and logic trainer board,
connecting wires.
Theory :-

SR Flip-Flop :-. It has two inputs, one is called “SET” which will
set the device (output = 1) and is labelled S and another is known
as “RESET” which will reset the device (output = 0) labelled as R.
The RS stands for SET/RESET.

JK Flip-Flop :-A JK flip-flop is used in clocked sequential logic

circuits to store one bit of data. It is almost identical in function to an
SR flip flop. The only difference is eliminating the undefined state
where both S and R are 1.

D Flip-Flop: -A D flip-flop is a sequential element that follows the

input pin d at the clock's given edge. D flip-flop is a fundamental
component in digital logic circuits.

T Flip-Flop:- The T flip-flop is also called toggle flip-flop. It is a

change of the JK flip-flop. The T flip flop is received by relating
both inputs of a JK flip-flop.

RESULT: Truth table of SR ,JK ,T and D flip flop are verified.

PRECAUTION: -
1.All connection should be tight.
2.After all connection of the circuit, the main supply should be ON.
S-R Flip-Flop

J-K Flip- Flop

T Flip-Flop
D Flip-Flop
 Experiment No.2

• Aim:- Bread Board Implementation of Counters and Shift register.

• Apparatus Used :- General purpose trainer board.
• IC7491 – Serial in parallel out.
• IC74164- Serial in parallel out.
• IC74165 – Parallel in serial out.
• IC74194- Parallel in parallel out.
• Patch Code.

Theory:-
A Register is a fast memory used to accept, store, and
transfer data and instructions that are being used immediately by
the CPU. A Register can also be considered as a group of flip-flops
with each flip-flop capable of storing one bit of information.

Result:-Bread Board Implementation of Counters and Shift register.

Precautions:-
1.Connection should be tight.
2.IC’s should be handled carefully.
 Experiment No.3

• Aim:- Determination of delay time AND , NAND , OR , NOR, X-

OR gates.
• Approved Required:- IC-7400,IC 7404 and logic trainer
board , connecting wire.
• Theory:-
NAND gate: If the minimum one input is low then the output is
high.
AND Gate : If both the inputs are high then the output is also
high.
OR Gate : If a minimum of one input is high then the output is
High.
XOR Gate : If the minimum one input is high then only the output
is high.
NOR Gate : If both the inputs are low then the output is high.

• Result:-Delay time of NAND,X-OR,NOR,AND,OR gate are

verified.
• Precautions:-
1.Connection should be tight.
2.It should be handled carefully.
Clocked Flip-Flop
 Experiment No.4

• Aim:-Experiment with clocked flip-flop.

• Material Required:-IC-7400,IC-7404 and logic trainer

board , connection wires.
• Theory:-So basically clock is used to synchronize the
inputs so as to get desired output. A Flip Flop [FF] is
one where there are Two inputs [ SR FF & JK FF] and
one input FF [ D-FF & T FF] . When used in Circuit an
additional input is given as Clock to synchronize with
other circuits in the system.
• Result:-Experiment with clocked flip –flop is verified.
• Precaution:-
1.All connection should be tight.
2.It should be handled carefully.
 Experiment no - 5

• Aim:- Design of counters.

• APPARATUS REQUIRED:-
• 1 Module-n-counter trainer 1
• 2 Connecting Leads 6
• THEORY:-
• A counter is one of the most useful and versatile sub systems in a
digital system. A counter driven by a clock can be used to count the
number of the clock cycles. Since the clock pulses occur at known
intervals, the counter can be used as an instrument for measuring time
and therefore period or frequency. There are basically two different
types of counters: Synchronous and Asynchronous. Module-N-counter
is a one type of counter, in which, instead of counting from the
beginning to the ending, we can restrict the counter to count up to
some set value and then to the beginning value. This can be achieved
by feeding the particular output to the reset input through digital gates.
The 74190 and 191 are synchronous, reversible up/down counters.
Having all flip-flops clocked simultaneously, so that the outputs change
coincide with each other when so instructed by the steering logic
provides synchronous counting operation.
• PRECAUTIONS:
• 1.Make the connection according to the circuit diagram.
• 2.Check the connections before on the supply.
• 3. Care should be taken in case of designing mode-n-counter for
counting less than n-bit in taken connection to the NAND gate.

• Result:-Design of Counter is successfully done.

 Experiment no – 6

• Aim :- Implementation of arithmetic algorithms.

• APPARATUS REQUIRED:
• S.No. Equipment Qty.
• 1 General purpose digital trainer 1
• 2 IC-74181 1
• THEORY :- Arithmetic logic unit is a multipurpose device capable of
providing several different arithmetic and logic operations. The specific
operation to be performed is selected by the user by placing a specific
binary code on the mode select i/p. ALU s are available in large scale
integrated circuit packages. Functional block diag. For 74181 ALU is
shown in fig. It is a 4-bit ALU, which provides 16 arithmetic plus 16 logic
operations. The unit accepts two 4-bit words (A3 A2 A1 A0 and B3 B2
B1 B0) and a carry i/p Cn as i/p’s. The operation to be performed on
these i/p are determined by logic levels on i/ps
• PROCEDURE :-
• 1. Put IC on the breadboard.
• 2. Apply Vcc supply at pin 24.
• 3. Apply ground at pin 12.
• 4. Make connections as shown in the circuit diagram.
• 5. Observe the different outputs.
• RESULT: -The functional table is verified for 74181 IC.
• PRECAUTIONS:-
• 1. Connection should be tight.
• 2. O/P should be finding sequentially.
• 3. IC’s should be handled carefully.
IC7483
 Experiment No.7

• Aim :- Bread Board Implementation of binary adder- subtractor .

• Apparatus Required:- IC 7483, 7486, Bread Board, Connecting
wires.
• Theory:-
The addition and subtraction operation can be combined into one
common circuit by including an X- OR gate with each Full adder. The
mode input M controls the operation. When M=0 the circuit is an
Adder and when M=1 the circuit becomes subtractor. Each X- OR gate
receives input M and one of the inputs of B. When M=0, we have B ⊕
0= B. The full adders receive the value of B, the input carry is 0, and the
circuit performs A plus B. When M=1, we have B ⊕ 1= B’ and C1=1.
• PROCEDURE: -
1) Put IC on the breadboard.
2) Apply 5V supply at pin 5.
3) Apply ground at pin 12.
4) Make connections as shown in the circuit diagram.
5) Keep SUB input LOW for Addition.
6) Keep SUB input HIGH for Subtraction.

Result:-The sum and difference of 4bit numbers is exactly same as

calculated .
4-bit Adder-Subtractor
 Experiment No.8

• Aim:- To design and set up the following adder/ subtractor

circuit using an IC 7483.

• Components Required:- IC 7483, IC 7486, breadboard,

logic probe etc.
• Theory :-
In the circuit we set mode control such
that when the mode control is zero, addition is performed,
and subtraction is performed when the mode control is
one. We use XOR gates to feed the input so that when
mode control is one, the complement of each of the four
bits are fed and when mode control is zero, the input as
such is fed. In 1’s complement subtraction, the complement
of the subtraction is taken and added with the other
number.
The final carry is then added to the LSB of the
result. In case there is no carry, the complement of the
result is taken, and this will be a negative number. This
indicates that, subtraction is performed from a smaller
number.
Adder Subtractor using IC 7483
 Experiment No.9

• Aim:- Demultiplexer/Decoder operation using IC-M138.

• Apparatus Required:- Digital trainer kit , wires.

• Theory:-
It is used as a decoder/demultiplexer. 3 to 8line decoder is a
combinational circuit that can be used as both a decoder and a
demux , IC74HC238 decodes three binary address
inputs(A0,A1,A2) into eight outputs (40 to 47).

Result:-The decoder(8:1) operation using IC -74138 is verified.

Precaution :-
1. Connection should be tight.
2. It’s should be handled.