Punjab Engineering College

Chandigarh

PRACTICAL FILE

NAME: - Arvinder Singh Sokhi

SID: - 23104130
COURSE NAME: - ANALOG AND DIGITAL ELECTRONICS
BRANCH: - ELECTRICAL Eng.
LAB INSTRUCTOR: - Dr. Hanuman
INDEX
Sr.No. Experiment Page no. Date Teacher’s sign

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EXPERIMENT – 1

Objective: Verification of Truth Table for the digital circuits of

1. 2 Bit Binary Half Adder
2. 3 Bit Binary Full Adder
3. 2 Bit Binary Half Subtractor

Apparatus Required: 1. Digital board DB08

2. DC Power Supply +5V from external source
3. Digital Multimeter or ST2611 Digital lab.

Theory:
In electronic devices, we need certain circuits that can be used for algebraic
computation. Thus, these circuits are extensively utilized in arithmetic and logic
units (ALUs), microprocessors, and various digital systems to execute binary
addition effectively.

A. ADDERS - An adder is a critical combinational circuit in digital

electronics, specifically engineered to carry out the arithmetic operation of
addition.
For this experiment we need to see 2 types of adders:

I. 2 Bit Binary Half Adder: The system comprises two integrated 1-bit
half adders operating in conjunction. Each half adder generates two
outputs: a sum and a carry. As a result, the addition process is
executed on a bit-by-bit basis.

Sum (Sh)[XOR] =A⊕B = AB’ + A’B

Carry (Ch) [AND]= A.B

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II. 3 Bit Binary Full Adder: It adds two 3-bit binary numbers and a carry
input. It combines three 1-bit full adders, each processing one bit and
carrying forward any carry to the next higher bit.

Sum (Sf) =A⊕B⊕Cin = A’B’Cin + A’BC’in + AB’C’in + ABCin

Cout= AB +ACin + BCin

B. SUBTRACTORS- A subtractor is a combinational circuit designed to

perform binary subtraction and are commonly used in arithmetic logic units
(ALUs) for performing subtraction and related operations.

I. 2 Bit Binary Half Subtractor: is a combinational circuit designed to

perform the subtraction of two single-bit binary numbers, A and B.
It produces two outputs, difference; result of the subtraction (A−B),
and borrow which indicates if a borrow is needed for the subtraction.

Difference (Dh) = A⊕B=AʹB+ABʹ

Borrow (Bh) = AʹB

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Procedure:
1. Connect +5V and ground to their indicated position on DB08 from external
DC power supply or from DC power block of digital lab ST-2611.
2. Switch on the Power Supply.
3. Connect inputs X, Y as per Truth Table to 2-bit binary half adder.
4. Observe output Sh , Ch on multimeter or on LED display of Digital Lab ST-
2611 and prove Truth Table.
5. Switch off the power supply.
6. Connect output Sh , Ch of 2-bit binary half adder to input Sh , Ch of 3-bit binary
Full Adder.
7. Connect input X, Y, Z to 3-bit binary full adder as per truth table shown.
8. Observe output Sf , Cf on multimeter or on LED display of Digital Lab ST2611
and prove truth table.
9. Repeat the above steps and prove truth table for 2-bit binary half subtractor.

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Observation Table:
A. 2 Bit Binary Half Adder
OBSERVATION INPUTS OUTPUTS
X Y Sh Ch
0 0 0 0

0 1 1 0

1 0 1 0

1 1 1 1

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B. 3 Bit Binary Full Adder

OBSERVATION INPUTS OUTPUTS
Sh Ch Z Sf Cf
0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

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1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

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C. 2 Bit Binary Half Subtractor

OBSERVATION INPUTS OUTPUTS
X Y Dh Bh
0 0 0 0

0 1 1 1

1 0 1 0

1 1 0 0

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Result:
The truth tables for the half adder, full adder, and half subtractor were verified.
The outputs for sum, carry, difference, and borrow matched the expected values,
confirming the correctness of the circuits.
Precautions:
1. Ensure proper connections to avoid short circuits or incorrect readings.
2. Verify input values before starting the experiment.
3. Handle the digital lab equipment carefully to prevent any damage.

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EXPERIMENT – 2

Objective: Flip flop circuits using NAND gate and 1TL IC has been designed
to verify the following gates-
1. RS Type Flip Flop Using NAND Gates
2. JK Type Flip Flop Using 1TL IC
3. D Type Flip Flop Using

Apparatus Required:
1. Fixed output DC regulated Power supply of 5V.
2. 1Hz Monoshot Clock pulse with pulser switch is provided on the front
panel.
3. Four Logic inputs logic '0' & logic '1' selectable using SPDT switches are
provided on the front panel.
4. Two red output indicators are also provided on the front panel.
5. IC 7400, 7410, 7474 & 7476 are mounted on the front panel & important
connections are brought out on sockets.
6. Single point 2mm Patch cords for Interconnection 7 No.
7. Double point Patch cords for Interconnection - 1 No.

Theory:
Flip-flops are fundamental building blocks of digital electronics used for storing
binary data. They are bistable multivibrators, meaning they have two stable states
(0 and 1). Flip-flops are triggered by a clock signal and are commonly used in
memory elements, counters, and sequential circuits. Flip-flops are widely used in
digital systems for data storage, synchronization, and building sequential logic
circuits like shift registers and finite state machine
A. RS Flip Flop (Reset - Set):
A SR flip-flop is a basic memory element in digital electronics that has
two inputs: Set (S) and Reset (R), and two outputs: Q and Q' (complement
of Q). It is used to store a single bit of data. SR flip-flops are used in simple
memory units, latches, and control circuits where a basic set-reset function
is required.

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B. JK Flip Flop:
A JK flip-flop is an advanced version of the SR flip-flop that eliminates the
indeterminate state when both inputs are high. It is widely used in sequential
logic circuits. It is used in counters, shift registers, and frequency dividers.
Commonly implemented in digital circuits requiring toggling or state changes.
The JK flip-flop is reliable and versatile, making it an essential component in
digital electronics.

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C. T Flip Flop:
A T flip-flop (Toggle flip-flop) is a type of flip-flop that toggles its output
state on every clock pulse if its input (T) is 1. If T is 0, the output remains
unchanged. It is derived from the JK flip-flop by connecting the J and K
inputs together. It is used in counters (e.g., binary counters, frequency
dividers) and also Simplifies toggling circuits. The T flip-flop is essential in
sequential logic circuits where state changes are triggered by clock pulses.

D. D Flip Flop:
A D Flip-Flop (Data or Delay Flip-Flop) is a type of flip-flop used to store
a single bit of data. It ensures that the output precisely follows the input
when triggered by a clock signal, making it an essential component in
digital circuits for synchronization.it is used in data storage elements like
registers, forms the basis of shift registers and counters and is commonly
used in synchronous circuits to maintain timing.

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Procedure:
A. Verification of ‘RS’ Type Flip Flop:
1. Connect the 4 logic inputs to 'Preset (PR)', Clear (CR)', 'S' & 'R' input of
the Flip-Flop as shown through patch cords. Also connect 'Q' & 'Q' outputs
to output Indicators.
2. Connect 1Hz clock output to 'Clock (CK)' Input of the flip flop.
3. Switch ON the instrument using ON/OFF toggle switch provided on the
front panel.
4. Verify the Truth Table No. (1) for various sets of input combinations

B. Verification of ‘JK’ Type Flip Flop:

1. Connect the 4 logic inputs to 'Preset (PR)', H Clear (CR)', 'J' & 'K' input
of the Flip-Flop as shown through patch cords. Also connect 'Q' & 'Q'
outputs to output indicators.
2. Connect 1Hz clock output to 'Clock (CK)' input of the flip flop.
3. Switch ON the instrument using ON/OFF toggle switch provided on the
front panel.
4. Verify the Truth Table for various sets of input combinations.

C. Verification of ‘T’ Type Flip Flop:

1. Short the "J" & "K" input of the IC 7476 to form "T" input. Also
connect three logic inputs to 'Preset (PR)', Clear (CR)' & 'T' inputs of
the Flip-Flop (To obtain "T" input short the 'J' & 'K' inputs). Also
connect 'Q' & 'Q' outputs to output indicators.
2. Connect 1Hz clock output to 'Clock (CK)' input of flip flop.
3. Switch ON the instrument using ON/OFF toggle switch provided on
the front panel.
4. Verify the Truth Table for various sets of input combinations.

D. Verification of ‘D’ Type Flip Flop:

1. Connect 3 logic inputs to 'Preset (PR)', Clear (CR)' & 'D' input of the
Flip-Flop as shown in Fig. No. (4) through patch cords. Also connect
'Q' & 'Q’' outputs to output indicators.
2. Connect 1Hz clock output to 'Clock (CK)' input of the flip flop.
3. Switch ON the instrument using ON/OFF toggle switch provided on
the front panel.
4. Verify the Truth Table for various sets of input combinations.
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Observation Table:
A. S-R FLIP FLOP
INPUTS OUTPUTS OBSERVATION
RESE CLEA CLOC S R Q Q’
T R K
(PR) (CR) (CK)
L H X X X H L

H L X X X L H

L L X X X H H

H H P L L Q Q

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H H P H L H L

H H P L H L H

H H P H H NOT TO
BE USED

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B. J-K FLIP FLOP

INPUTS OUTPUT OBSERVATION
S
RESE CLEA CLOC J K Q Q’
T R K
(PR) (CR) (CK)
L H X X X H L

H L X X X L H

L L X X X H H

H H P L L Q Q

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H H P H L H L

H H P L H L H

H H P H H NOT TO
BE USED

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C. T FLIP FLOP
INPUT OUTPUT OBSERVATION
T Q Q’
1 TOGGLE

D. D FLIP FLOP
INPUTS OUTPUTS OBSERVATION
RESET CLEAR CLOCK D Q Q’
(PR) (CR) (CK)
L H X X H L

H L X X L H

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L L X X H H

H H P H H L

H H P L L H

Result:
The truth tables for the ‘RS’, ‘JK’, ‘D’, ‘T’ type flip flops are matched and the
expected values, confirming the correctness of the circuits.
Precautions:
4. Ensure proper connections to avoid short circuits or incorrect readings.
5. Verify input values before starting the experiment.
6. Handle the digital lab equipment carefully to prevent any damage.

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EXPERIMENT – 3

Objective: To Study and Verify the Code Conversion Circuits

1. Binary to Gray Code
2. Gray to Binary Code

Apparatus Required:
1. Digital Board DB06
2. DC Power Supply +5 V from external source
or Scientech 2611 Digital lab.
3. Digital Multimeter or Digital Lab Scientech
2611.

Theory:
Code conversion using logic gates refers to the process of converting one type
of digital code into another using a combinational logic circuit. These
conversions are essential in digital systems to ensure compatibility between
different encoding schemes used in processors, memory, communication, and
control systems.
A Binary to Gray Code Converter is a
combinational circuit that converts a binary
number into its equivalent gray code. Gray code
is a reflected binary code where only one-bit
changes between successive numbers,
minimizing errors in digital systems.
Each Gray code bit Gn is derived from the
corresponding binary number Bn using XOR
(⊕) logic:
 MSB (Most Significant Bit) remains the
same:
Gn = Bn
 Other bits are obtained using XOR
operation:
Gn−1 = Bn⊕Bn-1
Gn-2 = Bn−1⊕Bn−2

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A Gray to Binary Code Converter is

a combinational circuit that converts a
gray code number back into its
equivalent binary form. Gray code is
designed so that only one-bit changes
between successive values, reducing
errors in digital systems. However, for
arithmetic and computational
operations, conversion back to binary is
necessary.
Each Binary bit (Bn) is derived from
the Gray code bit (Gn) using XOR (⊕)
logic:
 MSB (Most Significant Bit)
remains the same:
Bn = Gn
 Other bits are obtained using
cumulative XOR operation:
Bn−1 = Bn⊕Gn−1
Bn−2=Bn−1⊕Gn−2

Procedure:
1. Connect +5 V and ground to their indicated position on DB06 experiment
board from external DC power supply or from DC power block of Digital
Lab Scientech 2611.
2. Connect inputs B0, B1, B2, B3 as per truth table 2 to binary to gray code
converter as shown in fig. 1.
3. Switch ON the power supply.
4. Observe output G0, G1, G2, G3 on multimeter or on LED Display of
Digital Lab Scientech 2611.
5. Repeat above step for remaining inputs and prove truth table.

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Observation Table:
A. Binary to Gray Code
DECIMAL B3 B2 B1 B0 G3 G2 G1 G0 OBSERVATION
0 0 0 0 0 0 0 0 0

1 0 0 0 1 0 0 0 1

2 0 0 1 0 0 0 1 1

3 0 0 1 1 0 0 1 0

4 0 1 0 0 0 1 1 0

5 0 1 0 1 0 1 1 1

6 0 1 1 0 0 1 0 1

7 0 1 1 1 0 1 0 0

8 1 0 0 0 1 1 0 0

9 1 0 0 1 1 1 0 1

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B. Gray to Binary Code

DECIMAL G3 G2 G1 G0 B3 B2 B1 B0 OBSERVATION
0 0 0 0 0 0 0 0 0

1 0 0 0 1 0 0 0 1

2 0 0 1 1 0 0 1 0

3 0 0 1 0 0 0 1 1

4 0 1 1 0 0 1 0 0

5 0 1 1 1 0 1 0 1

6 0 1 0 1 0 1 1 0

7 0 1 0 0 0 1 1 1

8 1 1 0 0 1 0 0 0

9 1 1 0 1 1 0 0 1

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Result:
The truth tables for the code conversion of Binary to Gray and Gray to Binary
code are matched and the expected values, confirming the correctness of the
circuits.

Precautions:
1. Ensure proper connections to avoid short circuits or incorrect readings.
2. Verify input values before starting the experiment.
3. Handle the digital lab equipment carefully to prevent any damage.

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EXPERIMENT – 4

Objective: Studying and verifying BCD to Excess-3 code conversion circuit and
prove its Truth Table.

Apparatus Required:
1. Digital board DB07.
2. DC Power Supply +5 V from external source or
Scientech 2611 Digital lab.
3. Digital Multimeter or Digital Lab Scientech 2611.

Theory:
Binary Coded Decimal (BCD) and Excess-3 are both numerical coding systems
used in digital electronics. The BCD system represents decimal numbers (0-9) in
a 4-bit binary form, whereas Excess-3 (XS-3) is a self-complementary code that
is derived by adding 3 to the corresponding BCD value. This experiment aims to
design, implement, and verify a BCD to Excess-3 code converter circuit and
validate its truth table.
A. Binary Coded Decimal (BCD):
BCD is a 4-bit representation of decimal digits (0-9). The BCD code
follows a weighted binary system with place values of 8, 4, 2, and 1 (8421
code). Here, B3 is the most significant bit (MSB) and B0 is the least
significant bit (LSB)
B. Excess-3 (XS-3) Code:
Excess-3 code is derived by adding 3 (0011 in binary) to the BCD
representation of a decimal number. It is a self-complementary code,
meaning that the 1’s complement of an Excess-3 code represents the 9’s
complement of the decimal number. Here, E3 is the most significant bit
(MSB) and E0 is the least significant bit (LSB).
C. Converting BDC to Excess -3:
A BCD digit can be converted to its corresponding Excess-3 code by
simply adding 3 to it. Since we have only 10 digits (0 to 9) in decimal, we
don’t care about the rest and marked them with a cross (X).
Let A (MSB), B, C and D (LSB) be the bits representing the binary
numbers, and let w (MSB), x ,y and z (LSB) be the bits representing the
Excess-3 output. The truth table for the conversion is given below. The X’s
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mark is don’t care condition. To find the corresponding digital circuit, we

will use the K-Map technique for each of the Excess-3 code bits as output
with all of the bits of the BCD number as input.

Figure 1: K- Map for the Truth Table

Table 1: Truth table for code conversion

of BCD to Excess- 3

Thus, we get the following equations

which make the final Logic Circuit:
 w = A + (B.C) + (B.D)
 x=B⊕C⊕D
 y=C⊕D
 z = D'
Figure 2: Logic Circuit for the code conversion

Procedure:
1. Connect +5V and ground to their indicated position on DB07 experiment
board from external DC power supply or from DC power block of Digital Lab
Scientech 2611.
2. Connect inputs B0, B1, B2, E3 as per Truth Table to BCD to Excess-3 code
converter.
3. Switch 'On' the power supply.
4. Observe output E0, E1, E2, E3 on multimeter or on LED display of Digital
Lab Scientech 2611.
5. Repeat above steps for remaining of inputs and prove Truth Table.

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Observation Table:
TABLE FOR BCD TO EXCESS -3 CODE CONVERSION
DECIMA B3 B2 B1 B0 E3 E2 E1 E0 OBSERVATION
L
0 0 0 0 0 0 0 1 1

1 0 0 0 1 0 1 0 0

2 0 0 1 0 0 1 0 1

3 0 0 1 1 0 1 1 0

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4 0 1 0 0 0 1 1 1

5 0 1 0 1 1 0 0 0

6 0 1 1 0 1 0 0 1

7 0 1 1 1 1 0 1 0

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8 1 0 0 0 1 0 1 1

9 1 0 0 1 1 1 0 0

Result:
The truth tables for the code conversion of BCD to Excess – 3are matched and
the expected values, confirming the correctness of the circuits.

Precautions:
1. Ensure proper connections to avoid short circuits or incorrect readings.
2. Verify input values before starting the experiment.
3. Handle the digital lab equipment carefully to prevent any damage.

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EXPERIMENT – 5
Objective: To study the following circuit and verify Truth Table
1. 4 to 1 Line Multiplexer
2. 1 to 4 Line De-Multiplexer

Apparatus Required:
1. Digital board DB07.
2. DC Power Supply +5 V from external source or
Scientech 2611 Digital L.C. Platform.
3. Oscilloscope, Digital Multimeter or Scientech 2611
Digital L.C. Platform.

Theory:
A. 4 to 1 Line Multiplexer
A multiplexer is a combinational circuit that has many
data inputs and a single output, depending on control
or select inputs. For N input lines, log2(N) selection
lines are required, or equivalently, for 2n input lines, n
selection lines are needed. Multiplexers are also
known as “N-to-1 selectors,” parallel-to-serial
converters, many-to-one circuits, and universal logic
circuits. They are mainly used to increase the amount
of data that can be sent over a network within a certain
amount of time and bandwidth . Figure 1: MUX for 4 x 1

The 4-to-1 multiplexer is a multiplexer that has 4

inputs and a single output. The Output is selected as
one of the 4 inputs which is based on the selection
inputs. The number of the Selection lines will depend
on the number of the input which is determined by
the equation log2n, In 4×1 Mux the selection lines
can be determined as log4=2,slo two selections are
needed. The final equation becomes:
Y = S̅1 S̅0 I0 + S̅1 S0 I1 + S1 S̅0 I2 + S1 S0 I3
Table 1: Truth Table for 4 x 1 MUX

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Figure 2: Logic Circuit for the MUX

B. 1 to 4 Line De-Multiplexer
DEMUX or De-Multiplexer is a data distributor
combinational circuit. It works in a reverse way of the
Multiplexer. The DEMUX has 1 input port and 2n output
lines. Here n signifies the selection line for a DEMUX. As
per the selection line value, the DEMUX input lines will
be connected to receive the output. Demultiplexer receives
digital information from a single source and converts it
into several sources.
A 1x4 DEMUX has only one input which is denoted as I.
There are two selection lines i.e. S1 and S0. At last, the
DEMUX has output lines including Y3, Y2, Y1 &Y0. Here
Figure 3: DEMUX for 1 x 4 is the 1x4 DEMUX with diagram as mentioned below.
Y0=S1’S0’I; Y1=S1’S0I; Y2=S1S0’I; Y3=S1S0I

Table 2: Truth Table for 1 x4 DEMUX Figure 4: Logic Circuit for the DEMUX

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Procedure:
1. Connect +5 V and ground to their indicated position on DB10 from
external DC power supply or from DC power block of Scientech 2611
Digital L.C. Platform.
2. Switch ON the power supply.
3. Connect inputs D0-D3 as per Truth Table to 4 to 1 line multiplexer.
4. Observe output, Z on multimeter or on LED display of Scientech 2611
Digital 1.C. Platform and prove Truth Table.
5. Repeat step 3 and 4 for Table Ib. Observe results on Oscilloscope.
6. Connect input D as per Truth Table 2a to 1 to 4 Line Demultiplexer circuit
as shown in figure 2.
7. Observe output D0-D3 on multimeter or LED display of Scientech 2611
Digital I.C. Platform and prove Truth Table
8. Repeat steps 2 & 3 for Table 2b and observe output on Oscilloscope.

Observation Table:
A. For 4 to 1 Line Multiplexer
D0 D1 D2 D3 S1 S0 Z OBSERVATION
1 0 1 0 0 0 1

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1 0 1 0 0 1 0

1 0 1 1 1 0 1

1 0 1 0 1 1 0

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B. For 1 to 4 Line De-Multiplexer

D S1 S0 D0 D1 D2 D3 OBSERVATION
0 0 0 0 1 1 1

0 0 1 1 0 1 1

0 1 0 1 1 0 1

0 1 1 1 1 1 0

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Result:
The truth tables for the 4 to 1 Line Multiplexer and 1 to 4 Line De-Multiplexer
are matched and the expected values, confirming the correctness of the circuits.
Precautions:
1. Ensure proper connections to avoid short circuits or incorrect readings.
2. Verify input values before starting the experiment.
3. Handle the digital lab equipment carefully to prevent any damage.

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