Op-Amp and Linear ICs 18EE46

Module-1
Operational amplifiers: Introduction, Block diagram representation of a typical
Op-amp, schematic symbol, characteristics of an Op-amp, ideal op-amp,
equivalent circuit, ideal voltage transfer curve, open-loop configuration,
differential amplifier, inverting & non–inverting amplifier, Op-amp with
negative feedback(excluding derivations).

General Linear Applications: A.C. amplifier, summing, scaling & averaging

amplifier, inverting and non-inverting configuration, Instrumentation amplifier.

Introduction:

An operational amplifier commonly known as op-amp is a two-input single-

output differential voltage amplifier that is characterized by high gain, high input
impedance, and low output impedance.
The operational amplifier is called so because it has its origins in analog
computers, and was mainly used to perform mathematical operations. Depending
on its feedback circuit and biasing, an op-amp can be made to add, subtract,
multiply, divide, negate, and interestingly even perform calculus operations like
differentiation and integration.
Today, op-amps are very popular building blocks in electronic circuits. Op-amps
are used for a variety of applications such as AC and DC signal amplification,
filters, oscillators, voltage regulators, comparators and in most of consumer and
industrial devices. Op-amps exhibit little dependence on temperature changes or
manufacturing variations, which makes them ideal building blocks in electronic
circuits.
Block Diagram of Operational Amplifier (Op-amp)
OPAMP is a differential amplifier i.e., it will amplify the voltage which is
differentially present between its input terminals.

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Fig.1 Block Diagram of a typical op-amp

Input stage: The i/p stage is a dual i/p, balanced o/p differential amp. The 2 i/p
are inverting and non-inverting i/p terminals. This stage provides most of the
voltage gain of the OP-AMP and also establishes the input resistance of the op-
amp
Intermediate stage: This is usually another differential amplifier which is driven
by the output of the first stage. This stage is a dual –i/p unbalanced (Single-ended)
output.

Level- shifting stage: Due to direct coupling used between the 1st two stages, the
DC voltage at the output of the intermediate stage is well above ground potential.
The level shifting stage is used to bring the dc level to zero volts with respect to
ground.

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Output stage: This stage is normally a push-pull complementary amplifier o/p

stage. It increases output voltage swing and raises the current supplying capability
of OP-AMP. It also ensures that the o/p resistance of OPAMP is low.

Symbol of Operational Amplifier (Op-amp)

The schematic symbol of an op-amp is shown below.

Fig.2 Symbol of Operational Amplifier (Op-Amp)

The above-shown symbol is the most widely used op-amp symbol for all
electronic circuits.
An operational amplifier has
(a) Two input terminals
(b) One output
(c) Two supply terminals (+VCC => positive supply terminal and -VEE =>
Negative supply terminal).Typical supply voltages for OP-AMPs range
from ±9 to ±22V.
The two input terminals of the OP-AMP are designated as inverting and non-
inverting input. The output voltage tends to move in a negative direction when
a positive voltage is applied to the inverting terminals. Conversely, a negative-
going voltage signal at the inverting input causes the output voltage to move in
a positive direction. A positive-going voltage signal at the non-inverting input
produces a positive-going output and a negative-going voltage signal at the non-
inverting input produces a negative-going output.

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Thus any input signal at the inverting input terminal produces an inverted output
and any input signal at the non-inverting input terminal produces a non-inverted
output,
Currents, Impedances, voltage levels
 Typically the DC input current is nA or less.
 The circuit arrangement also affords to high input impedance 1MΩ or
greater.
 The output of an OP-AMP is typically an emitter follower for providing
low output impedance.
 The maximum output current that can be supplied is typically 25mA.
 The output impedance is around 75Ω.
 An op-amp with ±15V supply would produce a ±14V maximum output
swing.

 Voltage gain
 The op-amp input voltage (Vd) is the differential voltage or the
difference between voltage levels at the input terminals.
 The voltage gain of 200K is common with IC OP-AMP. This means
for example to produce 5V output, the required voltage difference at
the input terminals is:
5𝑉
𝑉𝑑 = = 25𝜇𝑉
200000

The Basic operational amplifier circuit

The Basic Circuit of an operational amplifier is as shown in Fig.3, which has a
differential amplifier input stage and an emitter follower output. Supply voltages
+VCC and -VEE are provided. The transistors Q1 and Q2 constitute a differential
amplifier, which produces voltage change at the collector of Q2 when a different
input voltage is applied to the bases of Q1 and Q2. Transistor Q3 operates as an
emitter follower to provide a low output impedance.
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Fig.3 basic circuit of an operational amplifier

The DC output voltage level at the output terminal is

V0=Vcc-VRC-VBE3 (1)
VO = VCC – IC2RC – VBE (2)

Assume that Q1 and Q2 are perfectly matched transistors, that is, They have equal
VBE and equal current gains. With both transistors bases at ground level, the
emitter currents are equal. Total emitter currents can be calculated as:

IE1 + IE2 = VRE / RE (3)

With Q1 and Q2 bases are grounded,

0 – VBE –VRE +VEE = 0

i.e. VRE = VEE – VBE

Therefore, IE1 + IE2 = (VEE – VBE) / RE (4)

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To investigate the circuit operation, assume that VCC= +10V, VEE=-10V, RE= 4.7
kΩ, RC=6.8KΩ, and VBE=0.7V

From equation (4), we get,

(10 − 0.7)
𝐼𝐸1 + 𝐼𝐸2 = = 2𝑚𝐴
4.7𝐾

Therefore, IE1=IE2=1mA

IC2=IE2=1mA

V0=10V-(1mAX6.8KΩ)-0.7V=2.5V

If a positive-going voltage is applied to non-inverting terminals, the Q1 base is

pulled up by the input voltage and its emitter terminals tend to follow the input
signal.
Since VBE=0.7 V
VB-VE=0.7V
VE=VB-0.7V ≈ VB≈ Input Voltage

Since Q1 and Q2 emitters are connected together, the emitter of Q2 also gets
pulled up by the positive input at the non-inverting terminal. The base of Q2 is
grounded, so the positive voltage at its emitter causes a reduction in its base-
emitter voltage VBE2. The reduction in VBE2 causes the emitter current IE2 to
decrease and consequently IC2 also reduced.
Assume that the positive-going input at the base of Q1 reduces IC2 by 0.2mA (i.e
from 1mA to 0.8mA). This gives a new level of the output voltage.

V0=10V-(0.8mAX6.8KΩ)-0.7V=3.9V

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Therefore the output voltage has changed from +2.5V to +3.9V, a change of 1.4V.
Thus a positive-going input signal at the non-inverting produces a positive-going
output voltage.,
Now consider, the non-inverting terminal is grounded and a positive-going input
is applied to the inverting input terminal. In this case, Q 2 base is pulled up, the
base-emitter voltage of Q2 is increased and that of Q1 is reduced by a similar
amount. This increases IE2 and a corresponding increase of IC2.
Assume that 0.2mA changes occur at IC2 (i.e. new value of IC2=1.2mA).
V0=10V-(1.2mAX6.8KΩ)-0.7V=1.1V

Therefore voltage change is -1.4V

Therefore a positive-going voltage at the inverting terminal produced a negative-

going voltage at the output. So, the output of the differential amplifier, is as
shown below

Operational Amplifier Characteristics

(a) Input voltage range:

Consider a voltage follower configuration as shown in Fig.4, where the inverting

input and the output terminals are connected together. The voltage level at
different nodes are shown in fig 4.

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Fig.4 Voltage follower circuit

If the voltage at the base of Q1 goes down to -4V, the output terminal also goes
to -4V as output follows the input. This means the emitter terminals of Q1 and Q2
pushed down to -4.7V. therefore VE= -4.7V.
Now, -VEE +4.3+VCE4=VE
VCE4=-4.7-4.3+ VEE
VCE4= -9+10=1V
Although Q4 might be operational, but it goes towards saturation, so there is a
limit to the negative going voltage that can be applied to the non-inverting
terminal if the circuit has to function properly.
There is also a limit to the positive going input voltages. when VB1 goes to +4V
in the circuit, the voltage drop across the resistor R1 must be reduced to something
less than 1V in order to move VB2 and VE3 up by 4V to follow the input. This
requires a reduction of IC2 to a level that makes Q2 approach cut-off. The input
voltage cannot be allowed to become large enough to drive Q2 into cut-off.
The maximum positive-going and negative-going input that can be applied to an
OP-AMP is termed as the input voltage range.
(b) The output voltage range:

A rough approximation for most of the op-amp is that the maximum output
voltage swing is approximately equal to 1V less than the supply voltage.

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(c) The Ideal operational amplifier

So, an ideal op amp is defined as, a differential amplifier with infinite open
loop gain, infinite input resistance and zero output resistance as shown in Fig.5 .
The ideal op amp has zero input current. This is because of infinite input
resistance. As the input resistance of ideal op amp is infinite, an open circuit
exists at input, hence current at both input terminals is zero.
There is no current through the input resistance; there will be no voltage drop
between the input terminals. Hence no offset voltage appears across the inputs of
an ideal operational amplifier.
If v1 and v2 are the voltages of inverting and non-inverting terminals of op amp,
and v1 = v2 then in ideal case. Therefore the voltage at the terminals of the op-
amp is equal for any finite output voltage. This concept is called Virtual
Ground. The bandwidth of operation of an ideal op-amp is also infinite. That
means the op-amp perform its function for all ranges of frequencies of operation.

Fig.5 A Ideal OP-AMP

Op-Amp Characteristic Table

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Note: Golden Rules of Op-amp

These ideal characteristics of the op-amp can be summarized as two golden rules.

 In a closed loop circuit, op-amp output will do whatever it can do to make

the voltage difference between the inputs zero.
 Op-amp inputs draws no current.

(d) Equivalent Circuit of an Op-Amp

Fig.6 Equivalent circuit of an op-amp

The circuit which represents op-amp parameters in terms of physical components,

for the analysis purpose is called equivalent circuit of an op-amp. The
equivalent circuit of an op-amp is shown in the Fig.6.The input voltage Vid is the
difference voltage (V2-V1). Ri is the input Resistance and Ro is the output
impedance. The gain parameter A is called the open loop gain. If an op-amp does

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not have any feedback from the output to either of the inputs, it is said to be
operating in open-loop configuration.

VO=AVid= A(V2-V1) (5)

Eq.(5) indicates that the output voltage is directly proportional to the algebraic
difference between the two input voltages.

Note: The op-amp amplifies the difference between the two input voltages;
It does not amplify the input signals themselves. For this reason polarity of
the output voltage depends on the polarity of the difference voltage.

(e) Ideal Voltage Transfer Curve:

The ideal op-amp produces the output proportional to the difference between the
two input voltages. The graphical representation of this statement gives the
voltage transfer curve. It is the graph of output voltage vo plotted against the
input voltage Vid assuming gain constant. This graph is
called Transfer characteristics of the op-amp as shown in Fig.7.

Now the output voltage is proportional to difference input voltage but only up to
the positive and negative saturation are specified by the manufacturer in
datasheet.

Fig.7 Ideal voltage transfer curve

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The curve is not drawn to the scale. If drawn to the scale, the curve
would be almost vertical due to large values of op-amp gain.

Note: The op-amp output voltage gets saturated at +Vcc and -

VEE and it cannot produce output voltage more than +Vcc and -
VEE. Practically saturation voltages +Vsat, and –Vsat are slightly less
than +Vcc and – VEE.
(f) CMRR (Common Mode Rejection Ratio)
CMRR is defined as the ability of an op-amp to reject the common mode input
signal. Higher the value of CMRR, better is the ability of the op-amp to reject a
common mode signal. Thus any unwanted signal such as noise would appear as
common to both input terminals and output due to this signal would be zero.
Therefore no undesirable noise signal will be amplified along with the desired
signal.

CMRR is defined as the ratio of differential gain to common mode gain.

CMRR = 20 log10 (|AD |/|AC|) dB (6)

Where, AD is the differential gain and AC is the common mode gain of the op
amp. As mentioned earlier, ideally output will be zero in common mode which
implies infinite CMRR.CMRR is expressed in decibels (dB) and the typical
practical value of CMRR of 741 op-amp is 95dB.

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(g) Input offset voltage (Vio)

Ideally, if both inputs of an op amp are at exactly ground potential or same

voltage, then the output should be at zero volts. In practice, a small
differential voltage must be applied to the inputs to force the output to zero.
This is known as the input offset voltage, Vos .Input offset voltage is
modelled as a voltage source, VOS, in series with the inverting input
terminal of the op amp as shown in Figure

Op Amp Offset Compensation:

For circuits where it is necessary to remove or null the offset, many op-amp chips
provide two pins (for IC741, its 1 and 5) that enable this to be done as in fig.8.
Using the offset null adjustment requires a potentiometer with its wiper connected
to the negative supply. The value for the potentiometer may typically be around
10 KΩ to 100 KΩ.

Fig.8 Offset null compensation

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It is also possible to provide external null circuits for amplifiers that do not
provide internal circuitry. The Fig.9 shows how this can be achieved for inverting
amplifier styles.

Fig.9 External offset adjustment for inverting amplifier

(h) Input offset-current

The operational amplifier input stage consists of a differential amplifier. This
differential amplifier is made up of a pair of NPN transistors (or a pair of PNP
transistors). Even though ideally the input currents of an op-amp is considered
zero, in practice these NPN (or PNP) transistors of an input stage of op-amp do
draw non-zero bias currents (IB1 & IB2). There is a difference in the input current

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that flows in or out of each of the input pins, even if the output voltage of the
operational amplifier is 0 V, due to the fact the pair characteristics (hFE, VBE) of
the differential transistor do not match. This difference is known as the input
offset current (IIO).

If an input stage of an op-amp has exactly matching a pair of NPN transistors,

then Input offset current will be zero. In actual, however, op-amps with transistor
based input stage do have few nA of the input offset current and as low as few
pA of input offset current for op-amps with JFET based input stage.

Fig.10 input offset current

(i) Input Bias Current

The input bias current IB is the average value of the base currents entering
into the terminals of the op-amp.
𝐼𝐵1 +𝐼𝐵2
𝐼𝐵 = (7)
2

(j) Input Impedance (Zin)

An ideal op-amp has infinite input impedance to prevent any flow of current from
the supply into the op-amp circuit. But when the op-amp is used in linear
applications, some form of negative feedback is provided externally. Due to this
negative feedback, the input impedance becomes
Zin = (1 + AOL β) Zi (8)
Where, Zi is the input impedance without feedback
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AOL is the open-loop gain

β is the feedback factor (1 for voltage follower)
The impedance of the signal sources connected to the input of an op-amp must
be very much smaller than the amplifier input impedance to avoid signal loss.

(k) Output Impedance (Zout)

An ideal op-amp has zero output impedance. This means that the output voltage
is independent of output current. Thus an ideal op-amp can act as a perfect
internal voltage source with zero internal resistance, so that maximum current can
be driven to the load.
Practically, the output impedance of the op-amp is affected by the negative
feedback and is given by,
Zout = Zo / (1 + AOL β) (9)

Where,
Zo is the output impedance of op-amp without feedback
AOL is the open-loop gain
β is the feedback factor
Load impedances connected at the output of the op-amp must be much larger than
the circuit output impedance, to avoid any significant loss of output as a voltage
drop across Zout.

(l) Open-Loop Gain (AOL)

Open-loop gain of an op-amp is defined as the gain of the op-amp when there is
no feedback from the output to either of its inputs. For an ideal op-amp, the gain
will be infinite theoretically, but practical value range from 20,000 to 200,000.

(m) Bandwidth (BW)

An ideal op-amp can amplify any frequency signal from DC to highest AC
frequencies, thus it has an infinite frequency response. Therefore, the bandwidth

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of an ideal op-amp should be infinite. In practical circuits, the bandwidth of the

op-amp is limited by the gain-bandwidth product (GB).

(n) Slew Rate

Slew rate is defined as the maximum change of output voltage per unit time and
is expressed as volts per second. An ideal op-amp will have an infinite slew rate.
In practical op-amps, the slew rate is inherently limited by the small internal drive
currents of the op-amp and also by the internal capacitances designed to
compensate for high-frequency oscillations. A slow slew rate, results in distortion
at the output. This is illustrated in fig.11, which shows a sine wave input to a
voltage follower producing a triangular output waveform. The triangular wave
results because the op-amp output simply cannot fast enough to follow thee sine
wave input.

Fig.11 Slew rate calculation for a sine wave

∆𝑉0
Slew Rate= ⌉ 𝑚𝑎𝑥
∆𝑡

Let Vi=Vm sinωt

𝑑𝑉0
= 𝑉𝑚 𝜔 𝑐𝑜𝑠𝜔𝑡
𝑑𝑡
𝑑𝑉0
( )𝑚𝑎𝑥 = 𝑉𝑚 𝜔
𝑑𝑡

i.e slew rate S=2πf Vm (10)

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or
𝑆
Input frequency f=
2πVm

The typical slew rate of IC 741 is 0.5V/μs.

(o) Power supply Rejection Ratio (PSSR)

The change in an op-amp’s input offset voltage, Vio, caused by variations in

supply voltage is called the power supply rejection ratio (PSRR) or supply
voltage Rejection Ratio (SVRR). A low value of SVRR is desirable.
∆𝑉𝑖𝑜
𝑆𝑉𝑅𝑅 =
∆𝑉
For 741C, SVRR=150μV/V
Open loop op-amp configurations

In the case of amplifiers, the term open loop indicates that no connection, either
directly or via another network, exists between the output and input terminals.
That is, there is no feedback in any form is fed to the input from the output. When
connected in an open – loop, the op-amp functions as a very high gain amplifier.
There are three open–loop configurations of op-amp namely

1. Differential amplifier
2. Inverting amplifier
3. Non-inverting amplifier
The above classification is made based on the number of inputs used and the
terminal to which the input is applied. The op-amp amplifies both ac and dc input
signals. Thus, the input signals can be either ac or dc voltage.

Open–loop Differential Amplifier:

In this configuration, the inputs are applied to both the inverting and the non-
inverting input terminals of the op-amp and it amplifies the difference between

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the two input voltages. The figure (12) shows the open-loop differential amplifier
configuration.

The input voltages are represented by Vi1 and Vi2. The source resistance Ri1 and
Ri2 are negligibly small in comparison with the very high input resistance offered
by the op-amp, and thus the voltage drop across these source resistances is
assumed to be zero. The output voltage V0 is given by

V0 = A(Vi1 – Vi2 ) (11)

where A is the large signal voltage gain. Thus the output voltage is equal to the
voltage gain A times the difference between the two input voltages. This is the
reason why this configuration is called a differential amplifier. In open–loop
configurations, the large signal voltage gain A is also called open-loop gain A.

Fig.12 Open-loop Differential Amplifier

2. Inverting amplifier:
Fig.13 shows the circuit of an open – loop inverting amplifier. In this
configuration, the input signal is applied to the inverting input terminal of the op-
amp and the non-inverting input terminal is connected to the ground. i.e in Eq.11,
substituting Vi1=0 and Vi2=Vi, we get

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V0 = -AVi (12)

The (-) sign indicates, the output voltage is 1800 out of phase with respect to the
input Thus, in an inverting amplifier, the input signal is amplified by the open-
loop gain A and in phase shifted by 1800.

Fig.13 Open-loop Inverting Amplifier

3. Non-inverting Amplifier

Fig.14 Open-loop Non-Inverting Amplifier

Fig.14 shows the open–loop non–inverting amplifier. The input signal is applied
to the non-inverting input terminal of the op-amp and the inverting input terminal
is connected to the ground.

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The input signal is amplified by the open–loop gain A and the output is in-phase
within the put signal.

V0 = AVi (13)

In all the above open-loop configurations, only very small values of input
voltages can be applied. Even for voltages levels slightly greater than zero, the
output is driven into saturation, which is observed from the ideal transfer
characteristics of op-amp shown in fig.7. Thus, when operated in the open-loop
configuration, the output of the op-amp is either in negative or positive saturation
or switches between positive and negative saturation levels. This prevents the use
of the open-loop configuration of op-amps in linear applications.

Limitations of Open-loop Op – amp configuration:

Firstly, in the open–loop configurations, clipping of the output waveform can
occur when the output voltage exceeds the saturation level of op-amp. This is due
to the very high open–loop gain of the op-amp. This feature actually makes it
possible to amplify very low-frequency signals of the order of microvolt or even
less, and the amplification can be achieved accurately without any distortion.
However, signals of such magnitudes are susceptible to noise and the
amplification for those applications is almost impossible to obtain in the
laboratory.

Secondly, the open–loop gain of the op-amps is not constant and it varies with
changing temperature and variations in power supply. Also, the bandwidth of
most of the open-loop op amps is negligibly small. This makes the open–loop
configuration of op-amp unsuitable for ac applications. The open–loop bandwidth
of the widely used 741 IC is approximately 5Hz. But in almost all ac applications,
the bandwidth requirement is much larger than this.

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For the reason stated, the open–loop op-amp is generally not used in linear
applications. However, the open–loop op-amp configurations find use in certain
non–linear applications such as comparators, square wave generators, and astable
multivibrators.

1. Determine the output voltage in each of the following cases for the open-loop
differential amplifier shown in fig.12:
a. Vi1=5μV dc, Vi2= -7 μV dc
b. Vi1=10mV rms, Vi2= 20 mV rms

The op-amp is 741 with the following specifications. A=200,000, Ri=2MΩ,

R0=75Ω, +VCC= +15V, -VEE= -15V, and output voltage swing=±14V.

Solution:

a. V0 = A(Vi1 – Vi2 )=200,000[(5)(10-6)-(-7)(10-6)]=2.4V

b. V0 = A(Vi1 – Vi2 )=200,000[(10)(10-3)-(20)(10-3)]=-2000V
However, the op-amp saturates at ±14V.Therefore the actual wave form
will be clipped and output will a square-wave at ±Vsat.
2. Determine the output voltage for the inverting amplifier shown in fig.13,if
a. Vin=20mV dc
b. Vin= -50μV peak sine wave
Assume that the op-amp is a 741
a. V0 = -AVi =-(2)(105)(20)(10-3)= -4000 V
This is theoretical value; the actual value will be a negative saturation
voltage.
b. V0 = -AVi =-(2)(105)(-50)(10-6)= 10V peak sine wave
Op-amp with negative feedback

The gain of the OPAMP can be controlled if fedback is introduced in the circuit.
That is, an output signal is fedback to the input either directly or via another

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network. If the signal fedback is of opposite or out phase by 180° with respect to
the input signal, the feedback is called negative feedback.
An amplifier with negative feedback has a self-correcting ability of change in
output voltage caused by changes in environmental conditions. It is also known
as degenerative feedback because it reduces the output voltage and, in tern,
reduces the voltage gain.
If the signal is feedback in phase with the input signal, the feedback is called
positive feedback. In positive feedback, the feedback signal aids the input signal.
It is also known as regenerative feedback. Positive feedback is necessary in
oscillator circuits.
The negative feedback stabilizes the gain, increases the bandwidth, and changes,
the input and output resistances. Other benefits are reduced distortion and reduced
offset output voltage. It also reduces the effect of temperature and supply voltage
variation on the output of an op-amp.
There are four types of feedback configurations according to whether the voltage
or current is feedback to the input in series or in parallel, as follows:
1. Voltage-series feedback
2. Voltage-shunt feedback
3. Current-series feedback
4. Current-shunt feedback

The four types of configurations are as illustrated in Fig.14

In fig. 14(a) and (c) the voltage across the resistor RL is the input to the
feedback circuit. The feedback quantity either voltage or current is the output
of the feedback circuit and is proportional to the output voltage. On the other
hand, in the current series and current-shunt feedback circuits of fig.14(b) and
(d),the load current iL flows into the feedback circuit. The output of the
feedback circuit either voltage or current is proportional to the load current
iL.

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Fig.14 Feedback configurations (a) Voltage-Series (b) m Current Series

(d) Voltage Shunt (d) Current Shunt

Inverting Amplifier configurations

An inverting amplifier using op-amp is a type of amplifier where the output
waveform will be phase opposite to the input waveform. The input waveform will
be amplified by the factor Av (voltage gain of the amplifier) in magnitude and its
phase will be inverted.
In the inverting amplifier circuit the signal to be amplified is applied to the
inverting input of the op-amp through the input resistance R1.Rf is the feedback
resistor. Rf and R1 together determines the gain of the amplifier. Inverting
operational amplifier gain can be expressed using the equation Av = – Rf/R1. A
negative sign implies that the output signal is negated. The circuit diagram of a
basic inverting amplifier using opamp is shown in fig.15.

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Fig.15 Inverting Amplifier

Let us derive the expression for its closed loop gain which is Vo / Vin

As node B is grounded, node A is also at ground potential, from the concept of

virtual ground, so VA = 0

(14)

Now from the output side, considering the direction of current I we can write,

(15)

Entire current I passes through R f as op-amp input current is zero.

Equating (14) and (15) we get,

(16)
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The Rf/R1 is the gain of the amplifier while negative sign indicates that the
polarity of output is opposite to that of input. Hence it is called inverting amplifier
Circuit.

Non-inverting Amplifier using Op-amp

Non-inverting amplifier is “the operational amplifier in which the output is in
phase with input signal”. In non-inverting amplifier, the input signal has applied
to non-inverting terminal of Op–Amp. Figure 16 is the Non-inverting amplifier.

Fig.16 Non-inverting Amplifier

The gain of non-inverting amplifier can be derived as

Apply KCL (Kirchhoff's current law) at node V–

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By virtual ground concept of Op–Amp

From Fig. 16,

Therefore,

Substitute equation (2) in (1)

Therefore, the voltage gain of non-inverting amplifier as

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Voltage follower (unity buffer amplifier]

If we made the feedback resistor, R1 equal to zero, (R1 = 0), and resistor R2 equal
to infinity, (R2 = ∞) in a non-inv amplifier Circuit(Fig.16), then the circuit would
have a fixed gain of “1” as all the output voltage would be present on the inverting
input terminal (negative feedback). This would then produce a special type of the
non-inverting amplifier circuit called a Voltage Follower or also called a “unity
gain buffer” as in Fig.17

The advantage of the unity gain voltage follower is that it can be used when
impedance matching or circuit isolation is more important than amplification as
it maintains the signal voltage. The input impedance of the voltage follower
circuit is very high, typically above 1MΩ as it is equal to that of the operational
amplifiers input resistance times its gain ( Rin x AO ). Also its output impedance
is very low since an ideal op-amp condition is assumed.

Fig.17 Voltage Follower

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Differential Amplifier using Op-amp

The circuit diagram of a differential amplifier using one op-amp is shown in

Fig.18. R1 and R2 are the input resistors, Rf is the feedback resistor and RL is the
load resistor.

Fig.18 Differential amplifier using one opamp

Derivation for voltage gain.

The equation for the voltage gain of the differential amplifier using one op-amp
can be derived as follows. The circuit is just a combination of an inverting and
non inverting amplifier. Finding the output voltages of these two configurations
separately and then summing them will result in the overall output voltage.

If Vb is made zero, the circuit becomes an inverting amplifier. The output voltage
Voa due to Va alone can be expressed using the following equation.

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When Va is made zero the circuit becomes a non inverting amplifier. Let V1 be
the voltage at the non inverting input pin. Relation between Vb and V1 can be
expressed using the following equation.

Output voltage Vob due to Vb alone is according to the equation

Let R1 = R2 and R3 =Rf then

Then overall output voltage is

Therefore overall gain is

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Practical differential amplifier.

A practical differential amplifier using uA741 op-amp is shown below. With used
components the amplifier has a gain of around 5. Remember the equation Av = -
Rf/R1. Here Rf = 10K and R1 =2.2K, -Rf/R1 = -10/2.2 = -4.54 = ~-5. Negative
sign represents phase inversion. Use +/-12V DC dual supply for powering the
circuit. uA 741 must be mounted on a holder.

Fig.19 Practical differential Amplifier

Op-amp Differentiator Circuit

This operational amplifier circuit performs the mathematical operation
of Differentiation that is, it “produces a voltage output which is directly
proportional to the input voltage’s rate-of-change with respect to time“. In other
words the faster or larger the change to the input voltage signal, the greater the

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input current, the greater will be the output voltage change in response, becoming
more of a “spike” in shape.

Since the node voltage of the operational amplifier at its inverting input terminal
is zero, the current, i flowing through the capacitor will be given as:

The charge on the capacitor equals Capacitance times Voltage across the
capacitor

Thus the rate of change of this charge is:

but dQ/dt is the capacitor current, i

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from which we have an ideal voltage output for the op-amp differentiator is given
as:

Op-amp Differentiator Waveforms

If we apply a constantly changing signal such as a Square-wave, Triangular or
Sine-wave type signal to the input of a differentiator amplifier circuit the resultant
output signal will be changed and whose final shape is dependant upon
the RC time constant of the Resistor/Capacitor combination.

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Op-amp Integrator Circuit

As its name implies, the Op-amp Integrator is an operational amplifier circuit
that performs the mathematical operation of Integration, that is we can cause
the output to respond to changes in the input voltage over time as the op-
amp integrator produces an output voltage which is proportional to the
integral of the input.

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We know from first principals that the voltage on the plates of a capacitor is
equal to the charge on the capacitor divided by its capacitance giving Q/C.
Then the voltage across the capacitor is output Vout therefore: -Vout = Q/C.
If the capacitor is charging and discharging, the rate of charge of voltage
across the capacitor is given as:

But dQ/dt is electric current and since the node voltage of the integrating op-amp
at its inverting input terminal is zero, X = 0, the input current I(in) flowing
through the input resistor, Rin is given as:

The current flowing through the feedback capacitor C is given as:

Assuming that the input impedance of the op-amp is infinite (ideal op-amp), no
current flows into the op-amp terminal. Therefore, the nodal equation at the
inverting input terminal is given as:

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From which we derive an ideal voltage output for the Op-amp integrator as:

To simplify the math’s a little, this can also be re-written as:

Where: ω = 2πƒ and the output voltage Vout is a constant 1/RC times the integral
of the input voltage VIN with respect to time.

Thus the circuit has the transfer function of an inverting integrator with the gain
constant of -1/RC. The minus sign ( – ) indicates a 180o phase shift because the
input signal is connected directly to the inverting input terminal of the operational
amplifier.

Summing, Scaling, and Averaging Amplifiers

The following Section shows how the inverting, non-inverting and differential
configurations are useful in such applications as summing, scaling and averaging
amplifiers.

A. Inverting Configurations

Summing amplifier is a type operational amplifier circuit which can be used

to sum signals. The sum of the input signal is amplified by a certain factor
and made available at the output. Any number of input signal can be summed
using an op-amp. The circuit shown in Fig.20 is a three input summing
amplifier in the inverting mode.

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Fig.20 Inverting Configuration with three inputs can be used as a summing amplifier, scaling,
or averaging amplifiers

In the circuit, the input signals Va,Vb,Vc are applied to the inverting input of the
op-amp through input resistors Ra,Rb,Rc. Any number of input signals can be
applied to the inverting input in the above manner. Rf is the feedback resistor. RL
is the load resistor. Non inverting input of the op-amp is grounded using resistor
Rm. To obtain equal bias current drops at both input terminals (to reduce output
offset voltage),Rm should be equal to parallel combinations of RA,RB,RC,RF.

Rm=(RA|| RB|| RC|| RF)

By applying kirchhoff’s current law at node V2 we get,

Ia+Ib+Ic = If+Ib

Since the input resistance of an ideal op-amp is close to infinity and has infinite gain.

We can assume Ib & V2 equal to zero.

Therefore Ia+Ib+Ic = If (17)

Equation (17) can be rewritten as

𝑉𝑎 𝑉𝑏 𝑉𝑐 𝑉2 −𝑉0
+ + =
𝑅𝑎 𝑅𝑏 𝑅𝑐 𝑅𝑓

Since V2=0, we get

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𝑉𝑎 𝑉𝑏 𝑉𝑐 −𝑉0
+ + =
𝑅𝑎 𝑅𝑏 𝑅𝑐 𝑅𝑓

𝑅𝑓 𝑅𝑓 𝑅𝑓
𝑉0 = − ( 𝑉𝑎 + 𝑉𝑏 + 𝑉𝑐 ) (18)
𝑅𝑎 𝑅𝑏 𝑅𝑐

Summing Amplifier

If in the circuit of Fig.20, Ra=Rb=Rc=R, then equation (18) can be written as

𝑅𝑓
𝑉0 = − (𝑉 + 𝑉𝑏 + 𝑉𝑐 ) (19)
𝑅 𝑎
If Rf=R, then the equation becomes,

𝑉0 = −(𝑉𝑎 + 𝑉𝑏 + 𝑉𝑐 ) (20)

This means that the output voltage is equal to the negative sum of all the inputs
times the gain of the circuit.

Scaling or weighted amplifier

In a scaling amplifier, each input will be multiplied by a different factor and then
summed together. Scaling amplifier is also called a weighted amplifier. Here
different values are chosen for Ra, Rb and Rc. The governing equation is
𝑅𝑓 𝑅𝑓 𝑅𝑓
𝑉0 = − ( 𝑉𝑎 + 𝑉𝑏 + 𝑉) (21)
𝑅𝑎 𝑅𝑏 𝑅𝑐 𝑐

𝑅𝑓 𝑅𝑓 𝑅𝑓
Where ≠ ≠
𝑅𝑎 𝑅𝑏 𝑅𝑐

Averaging Circuit

An averaging circuit can be made from the above circuit by making the all input
resistor equal in value ie; Ra = Rb = Rc =R and the gain must be selected such that
if there are ‘n’ inputs, then Rf/R must be equal to 1/n.i.e

𝑅𝑓 1
=
𝑅 𝑛

Where n is the number of inputs

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Thus, if there are three inputs,

𝑅𝑓 1
=
𝑅 3

𝑉𝑎 + 𝑉𝑏 + 𝑉𝑐
𝑉0 = ( ) (22)
3

Example problem:

a) In the circuit of Fig.20, Va=+1V, Vb=2V, Vc=+3V, Ra = Rb = Rc =3KΩ,

Rf=1KΩ, ROM= 270Ω and supply voltages are ±15V.Assuming that the op-
amp is initially nulled, determine the output voltage V0.

𝑅𝑓
Using equation 𝑉0 = − (𝑉𝑎 + 𝑉𝑏 + 𝑉𝑐 )
𝑅

1𝐾
𝑉0 = − (1 + 2 + 3) = −2𝑉
3𝐾

B. Non-inverting Configuration

 A non-inverting summing amplifier can be constructed, using the non-

inverting amplifier configuration. That is, the input voltages are applied to the
non-inverting input terminal and a part of the output is fed back to the inverting
input terminal, through voltage-divider-bias feedback.
 A non-inverting summing circuit is shown in the figure below.

The output equation of the above circuit is can be obtained by using the
superposition theorem. The voltage at V1 at the non-inverting terminal is

𝑅/2 𝑅/2 𝑅/2

𝑉1 = 𝑉𝑎 + 𝑉𝑏 + 𝑉 (23)
𝑅 + 𝑅/2 𝑅 + 𝑅/2 𝑅 + 𝑅/2 𝑐

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Fig.21 Non-inverting configuration with three inputs can be used as an averaging

amplifier or a summing amplifier

𝑉𝑎 𝑉𝑏 𝑉𝑐
𝑉1 = + +
3 3 3

𝑉𝑎 + 𝑉𝑏 + 𝑉𝑐
𝑉1 = (24)
3

Hence output voltage Vo is

𝑅𝐹
𝑉𝑜 = (1 + )𝑉
𝑅1 1

𝑅𝐹 𝑉𝑎 + 𝑉𝑏 + 𝑉𝑐
𝑉𝑜 = (1 + ) (25)
𝑅1 3

(a) Averaging amplifier :

From above equation in (25), it is clear that output voltage is equal to
average of all input voltages times the gain of the circuit (1+RF/R1), hence
the name averaging amplifier. If the gain is one, the output voltage will be
equal to the average of all input voltages.

(b) Summing Amplifier :

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A close examination of the equation Eq(25) reveals that if the gain

(1+RF/R1) is equal to the number of inputs, the output voltage becomes
equal to the sum of all input voltages. That is, if (1+RF/R1)=3 in eq(25),
V0=Va+Vb+Vc
Hence the circuit is called a non-inverting summing amplifier.
Example problem
1. In the circuit of figure (21), supply voltages= ±15V, Va=+2V, Vb= -3V,
Vc=+4V, R=R1=1KΩ and RF=2KΩ. Determine the voltage V1 at the non-
inverting terminal and the output voltage Vo. Assume that the op-amp is
initially nulled.
Using Eq(25),

𝑉𝑎 + 𝑉𝑏 + 𝑉𝑐 2 − 3 + 4
𝑉1 = = = 1𝑉
3 3

𝑅𝐹 𝑉𝑎 +𝑉𝑏 +𝑉𝑐 2𝐾
𝑉𝑜 = (1 + ) = (1 + ) (1) = 3𝑉
𝑅1 3 1𝐾

Which is the sum of the three inputs.

Instrumentation System
The measurement and control of physical conditions is very important in many
industrial and consumer applications. For example, the operator may make
necessary adjustments in the measurement of temperature or humidity inside a
dairy or meat plant to maintain the product quality, or to produce a particular type
of plastic, precise temperature control of the plastic furnace is needed.
A transducer is generally used at the measuring site to obtain the required
information easily and safely. A transducer is a device that converts one form
of energy into another.

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For example, when a strain gauge is subjected to pressure or force (physical

energy), the resistance of the strain gauge changes (electrical energy), i.e. it
converts mechanical energy into electrical energy. Actually, an instrumentation
system is used to measure the output signal produced by the transducer and
mostly used to control the physical condition producing the output signal.

Fig.22 Block diagram of an Instrument System

The simplified form of such an instrumentation system is shown in Fig.22. This

instrumentation system consists of a type of transducer as the input stage,
depending upon the physical quantity to be measured. The transducers output is
fed to the pre-amplifier. The instrumentation amplifier is the intermediate stage.
The output of the instrumentation amplifier can be connected to various devices,
such as meter, oscilloscope, charts or magnetic recorders.

Advanced technology has led to use of automatic instrumentation systems. This

system have an automatic process controller used at the output stage, which
compensates for changes in the operating condition.

The lines connecting the various stages, as shown in Fig. 22, are called the
transmission lines. On the system requirement and the physical quantity to be
monitored, the length of these transmission lines are chosen. These transmission
lines permit signal transfer from unit to unit.

The output of the transducer is the input signal source of the instrumentation
amplifier. A transducer which produces sufficient strength can be used to drive
the output device directly. Most do not produce sufficient output. Hence, to

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amplify these low level output signals of the transducer instrumentation ampli-
fiers are used which drive the indicator or display unit.

The instrumentation amplifier is required for precise low level signal ampli-
fication. In brief, they are used, where low noise, low thermal and time drift, high
input resistance and accurate closed loop gain are required.

Differential Instrumentation Amplifier using Transducer Bridge

Fig.23 Differential Instrumentation Amplifier using Transducer Bridge

Figure 23 shows a simplified circuit of a Differential Instrumentation Amplifier

using Transducer Bridge.

In this circuit a resistive transducer (whose resistance changes as a function of

some physical energy) is connected to one arm of the bridge.

Let RT be the resistance of the transducer and ΔR the change in resistance of the
resistive transducer. Hence the total resistance of the transducer is (RT ± ΔR).

The condition for bridge balance is Vb = Va, i.e. the bridge is balanced when Vb =
Va, or when

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The bridge is balanced at a desired reference condition, which depends on the

specific value of the physical quantity to be measured. Under this condition,
resistors RA, RB and RC are so selected that they are equal in value to the trans-
ducer resistance RT. (The value of the physical quantity normally depends on the
transducers characteristics, the type of physical quantity to be measured, and the
desired applications.)

Initially the bridge is balanced at a desired reference condition. As the physical

quantity to be measured changes, the resistance of the transducer also changes,
causing the bridge to be unbalanced ( Vb # Va ). Hence, the output voltage of the
bridge is a function of the change in the resistance of the transducer. The
expression for the output voltage V0, in terms of the change in resistance of the
transducer is calculated as follows.

Let the change in the resistance of the transducer be ΔR. Since R B and RC are
fixed resistors, the voltage Vb is constant, however, the voltage Va changes as a
function of the change in the transducers resistance.

Therefore, applying the voltage divider rule we have

The output voltage across the bridge terminal is Vab, given by Vab=Va-Vb

Therefore,

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The output voltage Vab of the bridge is applied to the Differential Instrumentation
Amplifier Transducer Bridge through the voltage followers to eliminate the
loading effect of the bridge circuit. The gain of the basic amplifier is (RF/R1) and
therefore the output voltage Vo of the circuit is given by

It can be seen from the above equation, Vo is a function of the change in resistance
ΔR of the transducer. Since the change is caused by the change in a physical
quantity, a meter connected at the output can be calibrated in terms of the units
of the physical quantity.

Generally ΔR is very small,therefore 2𝑅 + ∆𝑅 ≈ 2𝑅 ,Thus the output voltage,

∆𝑅(𝐸) 𝑅𝐹
𝑉𝑜 = − 𝑋
(4𝑅) 𝑅1

Applications of Instrumentation Amplifier Transducer Bridge

We shall now consider some important applications of instrumentation amplifiers
using resistance types transducers. In these transducers, the resistance of the
transducer changes as a function of some physical quantity. Commonly used
resistance transducers are thermistors, photoconductor cells, and strain gauges.

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Temperature Indicators Using Thermistor

The Thermistor is a relative passive type of temperature resistance transducer.
They are basically semiconductors.

In many respects, a thermistor resembles a conventional resistor. It is usually a

two-terminal device. It has resistance as its fundamental property. It is generally
installed and operated in the manner of an ordinary resistor. But its great
difference is that it has a negative temperature coefficient (NTC) or positive
temperature coefficient (PTC) type. Most thermistors exhibit an NTC charac-
teristic. An NTC type is one in which its resistance decreases with increase in
temperature. The temperature coefficient is expressed in ohms/°C.

Since it is a THERMally sensitive resISTOR, it has a high temperature coefficient

of resistance and is therefore well suited for temperature measurement and
control.

If in the bridge circuit of Fig. 23, the transducer used is a thermistor, the circuit
can thus be used as a temperature indicator. The output meter is then calibrated
in °C or °F. The bridge is balanced initially at a desired reference condition. As
the temperature varies, the resistance of the thermistor also changes, unbalancing
the bridge, which in turn produces a meter deflection at the output. By selecting
the appropriate gain for the Differential Instrumentation Amplifier Transducer
Bridge, the meter can be calibrated to read a desired temperature. In this circuit,
the meter movement (deflection) depends on the amount of unbalance in the
bridge, which is caused by a change in the value of thermistor resistance ΔR. The
change ΔR for the thermistor can be determined as follows.

If the meter in this circuit is replaced by a relay, and if the output of the
Differential Instrumentation Amplifier Transducer Bridge drives the relay that

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controls the current in the heat-generating circuit, a temperature controller can be

formed. A properly designed circuit should energise a relay when the temperature
of the thermistor drops below a desired value, causing the heater unit to turn on.

Light Intensity Meter

If in the bridge circuit of Fig.23, the transducer is a photocell, this circuit can be
used as a light intensity meter. Initially the bridge is balanced for the dark
condition, therefore when exposed to light the bridge becomes unbalanced, to a
degree depending upon the intensity of light. This unbalance causes the meter to
deflect. To measure the change in light intensity, the meter is calibrated in terms
of Lux or Lumen.

The light intensity meter can also be designed using a single input inverting or
non-inverting op-amp, but the light intensity meter using an instrumentation
amplifier is more accurate and stable, because the common mode (noise) voltages
are effectively cancelled by the differential mode.

Analog Weight Scale

Figure 23 can be converted into a simple analog weight scale by connecting strain
gauges in the bridge circuit. These strain gauges are connected in all the four arms
of the bridge,as shown in Fig. 24. The strain gauge elements are mounted on a
base of the specially made weight platform, on which an external force or weight
is placed. One pair of strain gauge elements in opposite arms elongates, (i.e.
RT1 and RT3 both increases in resistance) while the other pair compresses (RT2 and
RT4 both decreases in resistance), and vice-versa.

The bridge is balanced when no external force or weight is applied, i.e. RTI =
RT2 = RT3 = RT4 = R, and the output voltage of the weight scale is zero.

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Fig.24 Strain Gauge Bridge circuit for Analog Weight Scale

Suppose a weight is placed on the scale platform and RT1 and RT3 decreases in
resistance. Then RT2 and RT4 increase in resistance by the same value ∆R and the
bridge is unbalanced, thereby giving an unbalanced output voltage. This
unbalanced voltage Vab, is given by

where

E — excitation voltage of the bridge.

R = RT1 = RT2= RT3 = RT4 = unstrained gauge resistance

ΔR — change in gauge resistance.

The Differential Instrumentation Amplifier Transducer Bridge then amplifies the

voltage Vab, giving a deflection on the meter movement. As the gain of the
amplifier is (+ RF/R1), the output voltage Vo is given by

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The gain of the amplifier is selected depending on the sensitivity of the strain
gauge and on the full scale deflection requirements of the meter. The meter can
be then calibrated in grams or kilograms.

For better accuracy and resolution, a micro based digital weight scale may be
constructed. However, such a scale is much more complex and expensive then
the analog scale.

Example problem

1. In the circuit of Fig.23, R1=1KΩ,RF=4.7KΩ, RA= RB= RC=100KΩ, VDC=+5V

and op-amp supply voltages=±15V.The transducer is thermister with the
following specifications: RT=100KΩ at a reference temperature of 25°C;
temperature co-efficient of resistance=-1KΩ/°C. Determine the output
voltage at 0°C and 100°C.
At 25°C, RA= RB= RC= RT =100KΩ, therefore the bridge is balanced and
Vo=0V. However, at 0°C, the change ΔR in the resistance of thermistor is

∆𝑅 = −1𝐾Ω⁄℃ (0℃ − 25℃) = 25𝐾Ω

Therefore using the equation,

∆𝑅(𝐸) 𝑅𝐹 25(103 )(5) 4.7(103 )

𝑉𝑜 = − 𝑋 = 𝑋 = 1.46𝑉
(4𝑅) 𝑅1 (4𝑥100𝑥103 ) 1(103 )
Similarly at 100°C,

∆𝑅 = −1𝐾Ω⁄℃ (100℃ − 25℃) = −75𝐾Ω

Therefore using the equation,

∆𝑅(𝐸) 𝑅𝐹 −75(103 )(5) 4.7(103 )

𝑉𝑜 = − 𝑋 = 𝑋 = −4.41𝑉
(4𝑅) 𝑅1 (4𝑥100𝑥103 ) 1(103 )

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AC Amplifier

(b)

Fig.25 (a) AC inverting amplifier (b) AC non-inverting amplifier

If the designer needs the ac response characteristics of op-amp, that is low and
high frequency limits, or if the ac input is riding on some dc level, it is necessary
to use an ac amplifier with a coupling capacitor. For an example, in an audio
receiver system that consists of a number of stages, because of thermal drift,
component tolerances, and variations, the dc level is produced. To prevent the

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amplification of such dc levels, coupling capacitor must be used between the

stages. Fig.25 shows the ac inverting and non-inverting amplifiers with coupling
capacitors.

The coupling capacitor Ci, not only blocks the dc voltage but also sets the low-
frequency cut-off limit, which is given by

1
𝑓𝐿 = (1)
2𝜋𝐶𝑖 (𝑅𝑖𝑓 + 𝑅𝑜 )

Where fL=low-frequency cut-off or low end of the bandwidth

Ci=capacitance between two stages being coupled or dc blocking capacitor

Rif=ac input resistance of the second stage.

R0=ac output resistance of the first stage or the source resistance, Rin

High frequency cut-off fH depends on the closed loop gain of the amplifier

FH=(UGB) (K)/AF

Where UGB=unity gain BW which will be in the datasheet

K=Rf/(Rf+R1) and AF=closed lop gain of the op-amp

The required value of Ci can be calculated from equation (1).To minimize the
effect of output offset voltage, an offset minimizing resistor R OM or an output
coupling capacitor Co can be is used. Co can be used between the output terminal
of an amplifier and the following stage.

Example problem

1. In the circuit of fig. 25(a), Rin=50Ω,Ci=0.1μF,R1=100Ω,RF=1KΩ,

RL=10KΩ and supply voltages = ±15V. Determine the bandwidth of the
amplifier.
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Solution : input resistance of the inverting amplifier with feedback is

Rif=R1= 100Ω and the source resistance Rin=Ro=50Ω.Therefore

1 1
𝑓𝐿 = = = 10.6 𝐾𝐻𝑧
2𝜋𝐶𝑖 (𝑅𝑖𝑓 + 𝑅𝑜 ) (2𝜋)10−7 (150)

AF=-RF/R1=-10, K= Rf/(Rf+R1)=1k/(1k+100)=0.909

FH=(106) (0.909)/10=90.9 KHz

BW=fH-fL=80.3 KHz

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Module-2
Active Filters: First & Second order high pass & low pass Butterworth filters.
Band pass filters, all pass filters.
DC Voltage Regulators: voltage regulator basics, voltage follower regulator,
adjustable output regulator, LM317 & LM337 Integrated circuits regulators.

Introduction
A filter is an electrical network which has the ability to transmit certain range of
signal frequencies, and suppress or attenuate other frequencies. Filters are
extensively used in Electronic and communication circuits especially in Signal

and Image processing systems, in Dc power supplies, in instrumentation, in audio

electronics and in Analog to Digital Conversion (ADC) etc.

Applications of Filters:
Electric Filters have so many applications in our livelihood; some of these
applications are given below;
 The tuner in radio: The bandpass filter in the tuner of the radio allows a fixed
frequency to the output speaker.
 Treble & bass of the speaker: The bass has lower frequencies & treble has
higher frequencies. They are separated using high pass & low pass filter and
are separately routed to corresponding bass speaker & treble speaker for clear
music.
 Anti-Aliasing: it is a low pass filter that filters out the high-frequency
components from a signal before sampling. It prevents the aliasing component
form being sampled.
 Notch Filter: they are band rejects filters with a narrow bandwidth that filter
out any interfering signal.
 Power Supply Smoothing: The output of the power supply which is a rectifier
has an AC ripple in it. These frequencies are filtered out using a low pass filter
which results in smoothing the output signal.

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 Noise suppression: They are used in communication systems for noise

removal from the received signals.
An ideal filter should positively pass (or transmit) the band of frequencies which
it is designed to accept without attenuation. While at the same time, it should
attenuate, without fail, all frequencies outside the band. Thus in the pass band,
attenuation must be zero, whereas in the stop band, attenuation must be infinite.
Classification of filters
Electric filters may be classified in several different ways.
(i) Based upon the nature of the signal processed, filters may classified as
analog and digital filters
(ii) In yet another classification, the filters are categorised on the basis of range
of frequencies, as audio frequency filters and radio frequency filters. At
low or audio frequencies, resistance-capacitance filters are generally used,
whereas at high or radio frequencies, inductance –capacitance filters or
crystal filters find wider applications.
(iii)The most common types of practical filters are classified into four such as
a. Butterworth
b. Chebyshev
c. Bessel
d. Elliptical

Fig.1 Types of filters

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The key characteristics of the butterworth filter are that it has a flat passband
as well as stopband. it is sometime called as flat-flat filter. The chebyshev
filter has a ripple passband and flat stopband.
(iv) Based upon the circuit elements employed, filters may be classified as passive
filters and active filters.
Passive Filters
As the name suggests, passive filters are made up of passive components,
such as resistors, capacitors & inductors. It does not need any external source
of energy. Therefore there is no voltage gain in these filters. The output
voltage is always less than its input voltage.It can easily filter a high-
frequency signal but it cannot process any low frequencies.
Although its design is simple but connecting a load to this filter impacts on
its characteristics. Cascading the passive filters for higher order filter affects
the characteristics of the filter.
Active Filters
In addition to the resistor & capacitor, Active filter uses an active
component such as an operational amplifier, transistors, etc.
The downside is that it needs an external source of power, but it provides a
high voltage gain. This gain is used for amplifying any weak input signals.
The active filter can filter very low-frequency signals but it cannot process
very high-frequency signal.
Operational amplifiers can also be used to form or change the circuit
frequency response by making the filter’s output bandwidth narrower or
even wider by generating a more selective output reaction. An Op-Amp has
a high input impedance, a low output impedance and a voltage gain within
its feedback loop arising from the mixture of the resistor. Active filters,
when used with careful circuit design, generate excellent performance
features, very good precision with a steep roll-off and low noise.

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Fig.2 General Diagram of Active filter

Advantages of Active filters
The advantages of the active filters include the following
 These filters are less expensive than passive filters.
 The apparatus used in these filters is smaller than the components used in
passive filters.
 Active filter doesn’t show any insertion loss.
 It also permits the inter stage isolation for controlling of i/p and o/p
impedance.
 The closed loop gains of op-amps incorporated in active filters can be
effectively and more easily controlled.
Applications of Active filters
 Active filters are used in communication systems for suppressing noise, to
isolate a communication of signal from various channels to improve the
unique message signal from a modulated signal.
 These filters are used in instrumentation systems by the designers to choose
a required frequency apparatus and detach unwanted ones.
 These filters can be used to limit the analog signal’s bandwidth before
altering them to digital signals.

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 Analog filters are used in audio systems by engineers to send various

frequencies to various speakers. For example, in the music industry, record
& playback applications are needed to control the frequency components.
 Active filters are used in biomedical instruments to interface psychological
Sensors with diagnostic equipments & data logging.
(v) Practical filters are extensively used Based On Their Frequency Response:
The filters are classified based on the frequency response into the following
four categories.
1) Low pass filter(LP Filter)
2) High pass filter(LP Filter)
3) Band Pass Filter (BP filter)
4) Band stop filter (BS filter) or Band Reject(BR) Filter
5) All pass filter

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Low Pass Filters

A low pass filter has a constant gain from 0 Hz to a high cut-off frequency, fH.
Hence, the bandwidth of this filter is also fH. The ideal characteristic is shown in
Fig. 3 (a).

Fig. 3 – Low Pass Filter Characteristics (a) Ideal (b) Practical

The circuit allows the range of frequencies from 0 to fH. This range is known as
the pass band. The range of frequencies beyond f H, is completely attenuated and
hence called as stop band.

Practically, the gain of the filter decreases as the frequency increases and at f =
fH, the gain is down by 3 dB and after fH, it decreases at a higher rate. It begins to
roll-off (i.e decrease) at the rate of -20dB/decade or -6dB/octave.
Note: -20dB/decade implies that the gain decreases by -20dB if the frequency is
increased tenfold. After the end of transition band, the gain becomes zero.

High Pass Filters

The Fig. 4 shows the frequency response of high pass filter. For a high pass filter,
fL is the low cut off frequency. The range of frequency 0 < f < fL is the stop band
where f is the operating frequency. While the range of frequency f > fL is the
passband. The Fig. 4 (a) shows the ideal high pass filter characteristics while Fig.
4 (b) shows the practical high pass filter characteristics.
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The transition band is practically not shown in the characteristics as it is very

small. Hence, practically, also range upto fL is called as stop band and f > fL as
pass band. The range upto fL is completely attenuated by high pass filter. The gain
is zero in stop band, it increases linearly at a definite rate until it becomes equal
to the midband gain at f=fL and thereafter in the pass band, the gain remains
constant.

Fig. 4–High Pass Filter Characteristics (a) Ideal (b) Practical

Band Pass Filters

(a)Ideal (b) Practical

Fig. 5 – Band Pass Filter Characteristics

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A band pass filter has the property that it transmits, without attenuation ,all
frequencies lying between two cut-off frequencies fL, the lower cut-off
frequencies and fH, the higher cut-off frequencies.It attenuates all frequencies
below fL and beyond fH.
Referring to the frequemcy response characteristics of practical filter, it is seen
that the pass band extends from f=fL to f=fH and at both f=fL and f=fH, the gain
of the filter is 0.707 times the midband gain(in terms of decibels, this represents
a drop of 3dB in gain).
Band Stop Filters
It’s also known as Band reject filter or Band elimination filter or notch filter. In
Band stop filter, Specific Band of frequencies gets rejected and allows passing of
frequencies outside the Band. Referring to frequency response characteristics of
band stop filter, it transmits all frequencies below f L and above fH bur attenuates
all frequencies lying in between fL and fH.

(a)Ideal (b) Practical

Fig. 6 – Band Stop Filter Characteristics

All Pass Filters
It is a type of filter which passes all frequencies equally. It is also known as Phase-
Shift filter, time-delay filter as the output voltage shifts in phase with respect to
input voltage but they are equal in magnitude as shown in fig.7

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Fig. 7 – All Pass Filter Characteristics

First order low pass butterworth filter

The first order low pass butterworth filter is realised by R-C circuit used along
with an op-amp, used in the non-inverting configuration. The circuit diagram is
shown in Fig.7. This also called one pole low pass butterworth filter. The
resistances Rf and R1 decide the gain of the filter in the pass band.

Fig.7 First order low pass butterworth filter

Analysis of the Filter Circuit

The impedance of the capacitor C is – j Xc where Xc is the capacitive reactance
given by

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By the potential divider rule, the voltage at the non-inverting input terminal A
which is the voltage across capacitor C is given by,

As the op-amp is in the non-inverting configuration,

𝐕𝐨
is the transfer function of the filter and can be expressed in the polar form
𝐕𝐢𝐧

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as,

The phase angle Φ is in degrees. The equation (7) describes the behaviour of the
low pass filter.

Thus, for the range of frequencies, 0 < f < fH, the gain is almost constant equal to
fH which is high cut off frequency. At f = fH, gain reduces to 0.707 AF i.e. 3 dB
down from AF. And as the frequency increases than fH, the gain decreases at a
rate of 20dB/decade. The rate 20 dB/decade means decrease of 20 dB in gain per
10 times change in frequency. The same rate can be expressed as 6 dB/octave i.e.
decrease of 6 dB per two times change in the frequency. The frequency fH is called
cut off frequency, break frequency, - 3dB frequency or corner frequency. The
frequency response is shown in the Fig.8

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Fig.8 Frequency response of first order butterworth filter

The rate of decrease in gain is 20 dB/decade i.e. the decrease can be indicated by
a negative slope in the frequency response, as -20 dB/decade.

Design Steps
The design steps for the first order low pass Butterworth filter are

1) Choose the cut off frequency, fH.

2) Choose the capacitance C usually between 0.001μF and 1 μF. Generally, it is

selected as 1 μF or less than that. For better performance, mylar or tantalum
capacitors are selected.

3) Now, for the RC circuit,

Hence, as fH and C are known, calculate the value of R.

4) The resistances Rf and R1 can be selected depending on the required gain in

the pass band.

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Frequency Scaling
Once the filter is designed, sometimes, it is necessary to change the value of cut-
off frequency fH. The method used to change the original cut-off frequency fH to
a new cut-off frequency fH1 is called as frequency scaling.

To achieve such a frequency scaling, the standard value capacitor C is selected

first. The required cut-off frequency can be achieved by calculating
corresponding value of resistance R. But to achieve frequency scaling a
potentiometer is used as shown in Fig.7. Thus, the resistance R is generally a
potentiometer with which required cut-off frequency fH can be adjusted and
changed later on if required.

Second Order Low Pass Butterworth Filter

The practical response of Second Order Low Pass Butterworth Filter must be very
close to an ideal one. In case of low pass filter, it is always desirable that the gain
rolls off very fast after the cut off frequency, in the stop band. In case of first
order filter, it rolls off at a rate of 20 dB/decade. In case of second order filter, the
gain rolls-off at a rate of 40 dB/decade. Thus, the slope of the frequency response
after f = fH is - 40 dB/decade, for a second order low pass filter.

A first order filter can be converted to second order type by using an additional
RC network as shown in the Fig. 9.

The cut off frequency fH for the filter is now decided by R2, C2, R3 and C3. The
gain of the filter is as usual decided by op-amp i.e. the resistance R1 and Rf.

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Fig.9 Second Order Low Pass Butterworth Filter

Analysis of the Filter Circuit

For deriving the expression for the cut off frequency, let us use the Laplace
transform method.

The input RC network can be represented in the Laplace domain as shown in Fig.
10.

Fig.10

Using potential divider rule, we can Write

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Substituting in (1) and solving for VA, we get

Now, for op-amp in non-inverting configuration,

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As the order of s in the gain expression is two, the filter is called Second Order
Low Pass Butterworth Filter.

The standard form of the transfer function of any second order system is

Comparing (7) and (8), we can say that

In case of Second Order Low Pass Butterworth Filter, this frequency is nothing
but the cut-off frequency, ωH .

This is the required cut off frequency.

Replacing s by jω, the transfer function can be written in the frequency domain

and hence, finally, can be expressed in the polar form as,

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The frequency response is shown in Fig11.

Fig.11 Frequency response

At the cut off frequency fH, the gain is 0,707 Af i,e. 3 dB down from its 0 Hz level.
After, fH ( f > fH ) the gain rolls off at a frequency rate of 40 dB/decade,. Hence,
the slope of the response after, fH is – 40 dB/decade.

Design Steps
The design steps for second order low pass Butterworth titter are

1) Choose the cut-off frequency fH,

2) The design can be simplified by selecting R 2 = R3 = R and C2 = C3 = C And

choose a value of C less than or equal to 1 μF.

3) Calculate the value of R from the equation,

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4) As

From this we can write that,

Now, for Second Order Low Pass Butterworth Filter, the damping factor required
is 0.707, from the normalised Butterworth polynomial.

Thus, to ensure the Butterworth response, it is necessary that the gain Af is 1.586.

Hence, choose a value of R1 ≤ 100 kΩ and calculate the corresponding value of

Rf.

The frequency scaling method discussed earlier for first order filter is equally
applicable to the Second Order Low Pass Butterworth Filter.

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First Order High Pass Butterworth Filter

As mentioned earlier, a high pass filter is a circuit that attenuates all the signals
below a specified cut off frequency denoted as fL. Thus, a high pass filter performs
the opposite function to that of low pass filter. Hence, the First Order High Pass
Butterworth Filter circuit can be obtained by interchanging frequency
determining resistances and capacitors in low pass filter circuit.

Fig.12 First Order High Pass Butterworth Filter

The first order high pass filter can be obtained by interchanging the elements R
and C in a first order low pass filter circuit. The Fig. 12 shows the first order high
pass Butterworth filter.

It can be observed that as compared to first order low pass filter (Fig.7), the
positions of R and C are changed in the high pass circuit shown in Fig. 12.

The frequency at which the gain is 0.707 times the gain of filter in pass band is
called as low cut off frequency, and denoted as fL. So, all the frequencies greater
than fL are allowed to pass but the maximum frequency which is allowed to pass
is determined by the closed loop bandwidth of the op-amp used.

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Analysis of the Filter Circuit

The impedance of the capacitor is

Where f is the input i.e. operating frequency.

By the voltage divider rule, the potential of the non inverting terminal of the op-
amp is

Substituting in the above expression of VA,

This can be represented as

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Now, for the op-amp in non-inverting configuration,

This is the required expression for the transfer function of the filter. For the
frequency response, we require the magnitude of the transfer function which is
given by,

The equation (6) describes the behaviour of the high pass filter.

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Fig.13 Frequency response of first order high pass butterworth filter

Design Steps

Thus, the circuit acts as high pass filter with a passband gain as A f. For the
frequencies, f < fL, the gain increases till f = fL at a rate of + 20 dB/decade. Hence,
the slope of the frequency response in stop band is + 20 dB/decade for first order
high pass filter. The frequency response is shown in the Fig. 13.

Note : As high pass filter is basically a low pass filter circuit with positions of R
and C interchanged, the design steps and the frequency scaling method discussed
earlier for low pass filter is equally applicable to the first order high pass
Butterworth filter.

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Second Order High Pass Butterworth Filter

The second order high pass Butterworth filter produces a gain roll off at the rate
of +40dB/decade in the stop band. This filter also can be realised by interchanging
the positions of resistors and capacitors in a second order low pass Butterworth
filter. The Fig.14 shows the second order high pass Butterworth filter.

The analysis, design and the scaling procedures for this filter is exactly same as
that of second order low pass Butterworth filter.

Fig.14 Second Order High Pass Butterworth Filter

The voltage gain magnitude equation for the second order high pass filter is

and Rf = 0.586 R1
The frequency response of this filter is shown in the Fig.15.
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Fig.15 Frequency response

Solved problems on active filters

1. Design a low pass filter at a cut-off frequency of 1 KHz with a passband gain
of 2.Also draw the response curve.
Given fH=1KHz
Let C=0.01μF
Then R=1/(2π)(103)(0.01x10-6)=15.9 KΩ (use a 20-KΩ potentiometer)
Since the passband gain is 2. R1=Rf. Let R1=Rf=10KΩ
To plot the frequency response, the following equation of low pass filter will
be used.

Where AF=2, fH=1KΩ

The data of Table 1 are plotted as shown in fig.16

Table 1: Frequency response data

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Fig.16 Frequency response curve

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2. Using frequency scaling technique, convert the 1KHz cut-off frequency of the
low pass filter of problem(1) to a cut-off frequency of 1.6KHz

1
WKT 𝑓𝐻 =
2𝜋𝑅𝐶

1
(𝑓𝐻 )𝑜𝑟𝑖𝑔𝑖𝑛𝑎𝑙 = (1)
2𝜋(𝑅)𝑜𝑟𝑔 𝐶

1
(𝑓𝐻 )𝑛𝑒𝑤 = (2)
2𝜋(𝑅)𝑛𝑒𝑤 𝐶

Solving (1) and (2) we get

(𝑓𝐻 )𝑜𝑟𝑖𝑔𝑖𝑛𝑎𝑙 (𝑅)𝑛𝑒𝑤

=
(𝑓𝐻 )𝑛𝑒𝑤 (𝑅)𝑜𝑟𝑔

(𝑓𝐻 )𝑜𝑟𝑖𝑔𝑖𝑛𝑎𝑙
(𝑅)𝑛𝑒𝑤 = (𝑅)𝑜𝑟𝑔
(𝑓𝐻 )𝑛𝑒𝑤

1𝑘
(𝑅)𝑛𝑒𝑤 = 15.9𝐾 = 9.94𝐾 (𝑈𝑠𝑒 10𝐾 𝑝𝑜𝑡𝑒𝑛𝑡𝑖𝑜𝑚𝑒𝑡𝑒𝑟)
1.6𝐾

3. Design a second order low pass filter at a cut-off frequency of 1KHz.Draw

the frequency response of the network.

FH= 1KHz

Let C2=C3=0.0047 μF

Then R2=R3=1/[(2π)(103)(47)(10-10)]=33.86 KΩ (use 33KΩ potentiometer)

Rf=0.586 R1 let R1=27KΩ

Rf=0.586 x 27K=15.82 KΩ (use 20 kΩ potentiometer)

Thus the required components are

C2=C3=0.0047 μF, R2=R3=33KΩ, R1=27KΩ, Rf=15.82 KΩ(20 kΩ pot)

To obtain frequency response, we use the equation

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Table 2 Frequency response data

Fig.17 Frequency response graph

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4. Design a high pass filter at a cut-off frequency of 1KHz with a passband gain
of 2.Plot the frequency response of the filter

Let C=0.01μF

WKT fL=1/(2πRC)

R=1/ (2πC fL)=1/(2π X 0.01μ X 1K)=15.9KΩ

R1=RF=10KΩ since AF=2

The data for the frequency response plot can be obtained by substituting for
the input frequency f values 100Hz to 100KHz in the below equation.

Table 3 Frequency Response data for High pass Filter for Problem(4)

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Fig.18 Frequency Response Graph for Problem.4

5. Determine the low cutoff frequency fL of the second order high pass
butterworth filter given C2=C3=0.0047μF, R2=R3=33KΩ R1=27KΩ,
Rf=15.8KΩ. Draw the frequency plot of the filter.

1 1
𝑓𝐿 = = = 1𝐾𝐻𝑧
2𝜋𝑅𝐶 2𝜋𝑋33𝐾𝑋0.0047μ

The frequency data is obtained by using gain magnitude equation,

Table 4 Frequency response data for problem.5

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Fig.19 Frequency response for problem 5

6. Determine the gain of the first order low pass filter if the phase angle is
59.77o and the pass band gain is 7.

Given the phase angle, φ =-tan-1(f/fH)

=> f/fH=- tan(φ) = -tan(59.77o)

=> f/fH= -1.732.

Substituting the above value in gain of the filter, |(VO/Vin)| = AF/√ (1+(f/fH)2)
=7/√[1+(-1.716)2)] =7/1.986

=>|(VO/Vin)|=3.5.

Band Pass Filters

A Band Pass Filter Circuit designed to pass signals only in a certain band of
frequencies while rejecting all signals outside this band. There are basically two
types of Band Pass Filter Circuit,

 Wide band pass

 Narrow band pass

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A Band Pass Filter Circuit is defined as a wide band pass if its figure of merit or
quality factor ,Q < 10. While there is no firm dividing line between the two, if Q
> 10, the filter is a narrow Band Pass Filter Circuit. Hence Q is a measure of
selectivity meaning the higher the value of Q, the more selective is the filter, or
the narrower is the band width.

The relationship between Q, 3 db band widths and the centre frequency fC is

given by

For the wide Band Pass Filter Circuit, the centre frequency can be defined as

where,
fH = high cut-off frequency (Hz)
fL = low cut-off frequency of the wide band-pass filter (Hz)
Applications of Wide band-pass Filter

1. Used in wireless transmission and reception system

2. Bandpass filters are used in all kinds of instrumentation, as well, in
Seismology, Sonar, even medical applications...for example
Electrocardiograms, EEGs and such.
3. Audio Signal Processing, where a particular range of frequencies of sound is
required while removing the rest.
4. They are also widely used in optics, such as with lasers, LIDARS, etc.
5. Color filtering is actually a bandpass function

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Wide Band Pass Filter

 A wide band pass filter can be formed by simply cascading high pass and
low pass section and is generally the choice for simple to design.
 To obtain a ± 20 db/decade band pass filter, a first order high pass filter
and a first low pass sections are cascaded, for a ± 40 db/decade band pass
filter, second order high pass filter and second order low pass filter are
cascaded and so on for higher orders.
 In other words, the order of the Band Pass Filter Circuit depends upon the
order of the High pass and Low pass sections.
 Fig.20 shows the ±20 dB/decade wide band-pass filter where as fig.21
shows the ±40 dB/decade wide band-pass filter

Fig.20 ±20 dB/decade wide band-pass filter

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Fig.21 ±40 dB/decade wide band-pass filter

Fig.22 Frequency Response curve for ±20 dB/decade and ±40 dB/decade wide band-pass
filter

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7 a. Design a wide band-pass filter with fL=200Hz, fH=1KHz and a pass-band

gain =4.

b. Draw the frequency response of this filter

c. Calculate the value of Q for the filter

Solution

a. Design a low pass filter with fH=1KHz

Let C’=0.01μF,

then fH=1/(2πR’C’)

R’=1/(2π*fH*C’ )=1/(2π*1K*0.01μ)=15.9KΩ

Design a High pass filter with fL=200Hz

let C=0.05μF,

then fC=1/(2πRC)

R=1/(2π*fL*C)=1/(2π*200*0.05μ)=15.9KΩ

Since the band pass gain is 4, the gain of low pass and high pass filter could
be set equal to 2.

i.e 1+(RF/R1)=1+(R’F/R’1)=2

Therefore RF=R1 R’F=R’1

Let RF=R1=R’F=R’1 =10KΩ

(b) The voltage gain magnitude of the band-pass filter is equal to the product
of the voltage gain magnitudes of high pass and low pass filters. Therefore,

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 Op-Amp and Linear ICs 18EE46

𝒇
𝑽𝒐 𝑨𝑭𝑻 ( )
𝒇𝑳
| |= (𝑨)
𝑽𝒊𝒏 √[𝟏 + (𝒇/𝒇𝑳 )𝟐 ][𝟏 + (𝒇/𝒇𝑯 )𝟐 ]

Where 𝐴𝐹𝑇 =Total pass-band gain

f=frequency of the input signal (Hz)

fL=lower cut-off frequency(Hz)

fH=high cut-off frequency(Hz)

Here 𝐴𝐹𝑇 =4 , fL=200 Hz , fH=1 kHz

The frequency response data in Table 5 are obtained by substituting into

equation(A) the values of f from 10Hz to 10kHz.The frequency response plot
is shown in Fig.23.

Table 5 Frequency Response Data for the Band Pass Filter for problem(6)

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Fig. 23 Frequency Response for problem(6)

(c) fC=√fL*fH = √200*1000 = 447.2 Hz

Q= fC/(fH-fL)=447.2/(1000-200)=0.56

Narrow Band-Pass Filter:

Fig. 24 (a) Multiple feedback narrow band-pass filter (b)ite frequency response

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 The narrow Band Pass Filter Circuit using multiple feedback is shown in
Fig. 24(a). As shown in this circuit, the filter uses only one op-amp.
 It has two feedback paths, which is why it is called a multiple feedback
 The op-amp is used in the inverting mode.
 Generally a narrow band pass filter is designed for specific values of
centre frequency fc and Q, or fc and band width.
 Figure 24(b) shows the frequency response of a narrow Band Pass Filter
Circuit.
 To simplify the design calculations, choose C1=C2=C

𝑄
𝑅1 = (1)
2𝜋𝑓𝐶 𝐶𝐴𝐹

𝑄
𝑅2 = (2)
2𝜋𝑓𝐶 𝐶(2𝑄2 − 𝐴𝐹 )

𝑄
𝑅3 = (3)
𝜋𝑓𝐶 𝐶

Where AF is the gain at fC given by

𝑅3
𝐴𝐹 = (4)
2𝑅1

The gain AF , however, must satisfy the condition

AF < 2Q2 (5)

Another advantage of multiple feedback filter of fig.24 is that its center

’
frequency can be changed to a new frequency f C without changing the
gain or bandwidth. This is accomplished by simply changing R 2 to R’2 so
that

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 Op-Amp and Linear ICs 18EE46
2
𝑓𝐶
𝑅2′ = 𝑅2 ( ′ ) (6)
𝑓𝐶

8(a) Design the narrow band pass filter so that fC=1KHz, Q=3 and AF=10.

(b) Change the center frequency to 1.5KHzs, keeping AF and the BW

constant.

Solution :

(a) let C1= C2=0.01μF

𝑄 3
𝑅1 = = = 4.77𝑘Ω
2𝜋𝑓𝐶 𝐶𝐴𝐹 2𝜋(1000)(10−8 )(10)

𝑄 3
𝑅2 = = = 5.97𝑘Ω
2𝜋𝑓𝐶 𝐶(2𝑄 2 − 𝐴𝐹 ) 2𝜋(1000)(10−8 )(10−8 )[2(32 ) − 10]
𝑄 3
𝑅3 = = = 95.5𝑘Ω
𝜋𝑓𝐶 𝐶 2𝜋(1000)(10−8 )
Use R1=4.7kΩ, R2=6.2KΩ, and R3=100KΩ

𝑓 1000
(b) 𝑅2′ = 𝑅2 ( 𝑓𝐶′ ) = (5.97𝐾) (1500) = 2.65𝐾Ω
𝐶

Use R’2= 2.7KΩ

All-PASS FILTER:
The All Pass Filter is one that passes all frequency components of the input signal
without attenuation. Any ordinary wire can be used to perform this characteristic
but the most important factor in an all pass filter is that it provides predictable
phase shifts for different frequencies of the input signal.
These filters are widely used in communications. For example, when signals are
transmitted over transmission lines, such as telephone wires, from one point to
another, they undergo a change in phase. All pass filters are used to compensate

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for these phase changes. They are also called delay equalizers or phase
correctors.
Fig.25 shows an All pass filter where RF=R1.The output voltage Vo of the filter
can be obtained by using the superposition theorem.

Fig.25 All Pass Filter (a) Circuit (b) Phase shift between input and output voltages

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The above equation indicates that the amplitude of Vo/Vin is unity, that is IVoI =
|Vin| throughout the useful frequency range and the phase shift between Vo and
Vin is a function of input frequency f.

The phase angle Φ is given by,

2𝜋𝑓𝑅𝐶
𝜙 = −2 tan−1 ( )
1

Negative sign (-) indicates output lags input voltage.

Referring to Fig. 25(a), if the positions of R and C are interchanged, the phase
shift between input and output becomes positive. That is, output Vo leads input
Vin.

9.For the All pass filter, find the phase angle Φ if the frequency of Vin is 1KHz.
Given R=15.9KΩ C=0.01μF

Solution :

2𝜋𝑓𝑅𝐶 (2𝜋)(103 )(15.9)(103 )(10−8 )

𝜙 = −2 tan−1 ( ) = −2 tan−1 ( )
1 1
= −90°

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DC Voltage Regulators

Introduction

 DC voltages required by Electronic devices or circuits are derived by

transforming and rectifying the AC supply.The raw DC voltage produced
this way is not stable and contains unacceptable large ripple waveform
 All voltage regulators employ a Zener diode as a stable reference voltage
source.
 A Zener diode with a series resistor can be used as simple low-current
voltage regulator.
 The addition of a transistor allows a larger load current to be supplied
 An error amplifier can be added to detect and amplify the difference
between the regulator output and the reference voltage.
 IC operational amplifier make ideal voltage amplifiers

A voltage regulator , regulates the voltage, regardless of the changes in the

input voltage or connected load. It works as a shield for protecting devices
from damage. It can regulate both AC or DC voltages, depending on its design
as shown in block diagram (Fig.26)

Fig.26 Block diagram representation of voltage Regulator

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Voltage Regulator Basics

A DC voltage regulator accepts an unregulated supply voltage and produces a

stable output voltage. This is illustrated in Fig.27 (a), where the regulator supply
voltage is VS and the output is V0.The unregulated supply is VS is derived by
transforming, rectifying, and smoothing an ac supply voltage, or line voltage. The
regulator normally produces a reasonably constant output voltage regardless of
variations in the line voltage and/or load current.

As shown in Fig.27 (b), The unregulated supply has a substantial ripple (V rs)
superimposed upon its average DC level. However the output voltage Vo of the
DC regulator has very much lesser voltage ripple. However the output voltage
Vo is lower than the minimum level of supply voltage, Vs(min).The maximum
voltage that can be provided by the regulator is normally at least 3V lower than
Vs(min.

Fig. 27(a) DC power supply

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Fig.27(b) Regulator input and output voltages

Regulator Performance:

Ideally

 The output voltage of regulator should remain perfectly constant

irrespective of changes in the supply voltage and load current.
 There should not be any ac ripple voltage at the output

Practical voltage regulator do have some output ripple, and the output voltage is
affected to some extent by variations in load current and line voltage. The
performance of a voltage regulator is defined in terms of line regulation, load
regulation and ripple rejection

The line regulation defines the variation in output voltage (ΔVo) that occurs in
the supply voltage, increases or decreases by a specified amount,usually 10%.Its
usually expressed in percentage and is given by equation (1)

(∆𝑉0 𝑓𝑜𝑟 ± 10% 𝑉𝑆 𝑐ℎ𝑎𝑛𝑔𝑒)𝑋 100%

𝐿𝑖𝑛𝑒 𝑅𝑒𝑔𝑢𝑙𝑎𝑡𝑖𝑜𝑛 = (1)
𝑉0

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The load regulation defines the regulator performance in relation to load current
changes. When the load current changes from zero to full load, output voltage
changes by an amount(ΔVo).The load regulation expressed as a percentage of the
normal output voltage is given by equation (2),

(∆𝑉0 𝑓𝑜𝑟 ∆𝐼𝐿 = 𝐼𝐿(𝑚𝑎𝑥) )𝑋 100%

𝐿𝑜𝑎𝑑 𝑅𝑒𝑔𝑢𝑙𝑎𝑡𝑖𝑜𝑛 = (2)
𝑉0

The Ripple Rejection is a measure of how much the voltage regulator attenuates
the supply voltage ripple. It is usually expressed in decibels as in equation (3).

𝑉𝑟𝑠
𝑅𝑖𝑝𝑝𝑙𝑒 𝑅𝑒𝑗𝑒𝑐𝑡𝑖𝑜𝑛 = 20 log [ ] 𝑑𝐵 (3)
𝑉𝑟𝑜

Where Vrs is the supply voltage ripple and Vro is the output voltage ripple

Voltage Follower Regulator

Fig.28 Voltage follower Regulator

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The voltage follower DC voltage regulator is as shown in Fig.28.Op-amp supply

is +VS and ground .The stable input to the op-amp non-inverting terminal is
provided by the zener diode.Op-amp inverting terminal is connected to output
voltage, V0 will remain close to the voltage at non-inverting terminal; that is, V0
equals the zener diode voltage VZ. The function of series pass transistor Q1is to
provide a load current larger than maximum supplied by the op-amp alone. If load
current required is < 25mA, Q1can be omitted.C1 is a large value capacitor (50μF-
100μF), which is connected at output to suppress oscillations.

Design performance

Line Regulation:When the supply changes, the voltage drop across the R1
changes by the same amount. Consequently, the zener diode current changes.
This causes a slight change in VZ and the output voltage also changes as it is equal
to VZ.

The zener current variation is first calculated as,

∆𝑉𝑆
∆𝐼𝑍 = (1)
𝑅1

Using the dynamic impedance specified for the zener diode (Z z), ΔVo is
determined as
∆𝑉0 = ∆𝑉𝑍 = ∆𝐼𝑍 𝑍𝑧 (2)

Substituting Eq.(1) in Eq(2), we get

∆𝑉𝑆 𝑍𝑧
∆𝑉0 = (3)
𝑅1

If ΔVo is calculated for 10% change in Vs,it can be substituted in Eq(4) to

determine the line regulation of regulator.

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(∆𝑉0 𝑓𝑜𝑟 ± 10% 𝑉𝑆 𝑐ℎ𝑎𝑛𝑔𝑒)𝑋 100%

𝐿𝑖𝑛𝑒 𝑅𝑒𝑔𝑢𝑙𝑎𝑡𝑖𝑜𝑛 = (4)
𝑉0

Load Regulation: To calculate the load regulation, the supply source resistance
must be known. The value of RS depends on the components of the rectifying and
smoothing circuit. The drop in supply voltage when the load current goes from
zero to IL(max) is,

∆𝑉𝑆 = 𝐼𝐿(𝑚𝑎𝑥) 𝑅𝑆 (5)

Substituting Eq(5) in Eq(3)

𝐼𝐿(𝑚𝑎𝑥) 𝑅𝑆 𝑍𝑧
∆𝑉0 = (6)
𝑅1

The Equation (6) can be substituted in Equation(7) to find load regulation.

(∆𝑉0 𝑓𝑜𝑟 ∆𝐼𝐿 = 𝐼𝐿(𝑚𝑎𝑥) )𝑋 100%

𝐿𝑜𝑎𝑑 𝑅𝑒𝑔𝑢𝑙𝑎𝑡𝑖𝑜𝑛 = (7)
𝑉0

Ripple Rejection:The supply voltage ripple (Vrs) can be treated like a supply
voltage change to determine the output voltage ripple Vro. In equation (3) replace
ΔVS by Vrs and ΔVo by Vro, we get

𝑉𝑟𝑆 𝑍𝑧
𝑉𝑟𝑜 = (8)
𝑅1

Using Eq. (8), we can calculate ripple rejection by using Eq.(9).

𝑉𝑟𝑠
𝑅𝑖𝑝𝑝𝑙𝑒 𝑅𝑒𝑗𝑒𝑐𝑡𝑖𝑜𝑛 = 20 log [ ] 𝑑𝐵 (9)
𝑉𝑟𝑜

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6. The DC voltage source VS =12V, V0 =6.3V, R1 =270Ω, D1 is a IN753

Zener diode and IL(max)=42mA , Rs =25Ω, determine Line regulation, load
regulation and ripple rejection for the circuit.

Solution:

From IN753 data sheet ZZ =7Ω

Line Regulation:

A 10% change in VS , ΔVS=10% of 12V=0.1*12=1.2V

∆𝑉𝑆 𝑍𝑧 1.2 ∗ 7
∆𝑉0 = = = 31𝑚𝑉
𝑅1 270

(∆𝑉0 𝑓𝑜𝑟 ± 10% 𝑉𝑆 𝑐ℎ𝑎𝑛𝑔𝑒)𝑋 100 31𝑚𝑉 𝑋 100%

𝐿𝑖𝑛𝑒 𝑅𝑒𝑔𝑢𝑙𝑎𝑡𝑖𝑜𝑛 = = = 0.5%
𝑉0 6.3𝑉

𝐼𝐿(𝑚𝑎𝑥) 𝑅𝑆 𝑍𝑧 42𝑚𝐴 ∗ 25𝛺 ∗ 7𝛺

∆𝑉0 = = = 27𝑚𝑉
𝑅1 270𝛺

Load Regulation:

𝐼𝐿(𝑚𝑎𝑥) 𝑅𝑆 𝑍𝑧 42𝑚𝐴 ∗ 25𝛺 ∗ 7𝛺

∆𝑉0 = = = 27𝑚𝑉
𝑅1 270𝛺

(∆𝑉0 𝑓𝑜𝑟 ∆𝐼𝐿 = 𝐼𝐿(𝑚𝑎𝑥) )𝑋 100% 27𝑚𝑉𝑋 100

𝐿𝑜𝑎𝑑 𝑅𝑒𝑔𝑢𝑙𝑎𝑡𝑖𝑜𝑛 = = = 0.4%
𝑉0 6.3𝑉

Ripple Rejection

𝑉𝑟𝑆 𝑍𝑧 𝑉𝑟𝑆 7
𝑉𝑟𝑜 = = = 25.9𝑋10−3 𝑉𝑟𝑠
𝑅1 270

𝑉𝑟𝑠 𝑉𝑟𝑠
𝑅𝑖𝑝𝑝𝑙𝑒 𝑅𝑒𝑗𝑒𝑐𝑡𝑖𝑜𝑛 = 20 log [ ] 𝑑𝐵 = 20 log [ ] 𝑑𝐵 = 31.7𝑑𝐵
𝑉𝑟𝑜 25.9𝑋10−3 𝑉𝑟𝑠

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Adjustable Voltage Regulator:

Fig.29 (a) shows how the simple voltage follower regulator can be modified to
produce an output voltage which is greater than the zener diode voltage.The
voltage across R3 is always going to be equal to Zener diode voltage.If VR3 were
to become greater than VZ, the op-amp output would fall, thus reducing Vo until
VR3 again equals VZ. If VR3 drops below the level of VZ, the op-amp output moves
in a positive direction until VR3 equals VZ once again.

Hence the output voltage is maintained constant by keeping VR3 equal to VZ. The
op-amp here is basically operating as error amplifier because it amplifies any
error in the output to keep the output stabilized at the desired value. we have

VR3= VZ (1)

𝑉𝑍 (𝑅2 + 𝑅3 )
𝑉𝑂 = (2)
𝑅3

The output voltage can be made adjustable by including potentiometer R4

between R2 and R3 as shown in fig. 29(b).

Fig.29 (a) Adjustable voltage Regulator (b) Potentiometer R4 makes Vo Adjustable

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Just as VZ is multiplied by (R2+R3)/R3 to find V0,so too any variations in VZ must

be multiplied by the same factor to determine the output voltage changes,
Therefore,

∆𝑉𝑆 𝑍𝑧 (𝑅2 + 𝑅3 )
∆𝑉0 = (3)
𝑅1 𝑅3

All supply voltage changes, whether due to line voltage variations, load current
changes, or ripple voltages, can be substituted in Eq.(3) to determine the effect
on the output.

7. (a)Using 741 op-amp, design an adjustable voltage regulator circuit as shown

in Fig 29 to produce an output of 12V with a maximum load current of 50mA.
(b) Also determine line regulation, load regulation and ripple rejection. The
source resistance is 10Ω

Solution: (a) VS(min)= V0+3V=12V+3V= 15V

Allowing Vrs=2V peak to peak,

𝑉𝑟𝑠
𝑉𝑆 = 𝑉𝑠(𝑚𝑖𝑛) + = 15𝑉 + 1𝑉 = 16𝑉
2

The supply voltage is Vs=16V with a 2V (max) ripple superimposed.

𝑉𝑆 16
Let 𝑉𝑍 ≈ = = 8𝑣 (Use a IN756 zener diode which has VZ=8.2V)
2 2

IZ≈20mA

𝑉𝑆 − 𝑉𝑍 16𝑉 − 8.2𝑉
𝑅1 = = = 390Ω(𝑆𝑡𝑑 𝑣𝑎𝑙𝑢𝑒)
𝐼𝑍 20𝑚𝐴

I2 >> IB(max)

I2=50μA

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𝑉𝑜 − 𝑉𝑍 12𝑉 − 8.2𝑉
𝑅2 = = = 76𝑘Ω (use a std value of 68𝑘Ω)
𝐼2 50μA

𝑉𝑜 − 𝑉𝑍 12𝑉 − 8.2𝑉
𝐼2 = = = 55.9μA
𝑅2 68𝑘Ω

𝑉𝑍 8.2𝑉
𝑅3 = = = 147𝑘Ω (use 150KΩ)
𝐼2 55.9μA

Select C1=50μF

Q1 specifications are

VCE(max)=Vs(max)=Vs+Vrs/2=16V+2V/2=17V

IE=IL=50mA

P=VCE X IL=(Vs-Vo)x IL=(16V-12V)X 50mA=200mW

A 2N718 is a suitable device

(b) From IN753 data sheet ZZ =8Ω

Line Regulation:

A 10% change in VS , ΔVS=10% of 16V=0.1*16=1.6V

∆𝑉𝑆 𝑍𝑧 (𝑅2 + 𝑅3 ) 1.6 ∗ 8(68𝑘 + 150𝐾)

∆𝑉0 = = = 48𝑚𝑉
𝑅1 𝑅3 390 𝑋 150𝐾

(∆𝑉0 𝑓𝑜𝑟 ± 10% 𝑉𝑆 𝑐ℎ𝑎𝑛𝑔𝑒)𝑋 100 48𝑚𝑉 𝑋 100

𝐿𝑖𝑛𝑒 𝑅𝑒𝑔𝑢𝑙𝑎𝑡𝑖𝑜𝑛 = = = 0.4%
𝑉0 12𝑉

Load Regulation: For an IL change of 50mA

𝐼𝐿(𝑚𝑎𝑥) 𝑅𝑆 𝑍𝑧 (𝑅2 + 𝑅3 ) 50𝑚𝐴 ∗ 10𝛺 ∗ 8𝛺 (68𝐾 + 150𝐾)

∆𝑉0 = = ≈ 15𝑚𝑉
𝑅1 𝑅3 390𝛺 150𝐾

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(∆𝑉0 𝑓𝑜𝑟 ∆𝐼𝐿 = 𝐼𝐿(𝑚𝑎𝑥) )𝑋 100 15𝑚𝑉𝑋 100

𝐿𝑜𝑎𝑑 𝑅𝑒𝑔𝑢𝑙𝑎𝑡𝑖𝑜𝑛 = = = 0.125%
𝑉0 12𝑉

Ripple Rejection

𝑉𝑟𝑆 𝑍𝑧 (𝑅2 + 𝑅3 ) 𝑉𝑟𝑆 8 (68𝐾 + 150𝐾)

𝑉𝑟𝑜 = = = 28.9𝑋10−3 𝑉𝑟𝑠
𝑅1 𝑅3 390 150𝐾

𝑉𝑟𝑠 𝑉𝑟𝑠
𝑅𝑖𝑝𝑝𝑙𝑒 𝑅𝑒𝑗𝑒𝑐𝑡𝑖𝑜𝑛 = 20 log [ ] 𝑑𝐵 = 20 log [ ] 𝑑𝐵 ≈ 31 𝑑𝐵
𝑉𝑟𝑜 28.9𝑋10−3 𝑉𝑟𝑠

LM 317 and LM337 IC regulators

Iadj
I1

Fig.28 LM 317 Integrated circuit positive voltage regulator

The LM 317 and LM 337 integrated circuit voltage regulators are three-terminal
devices which are easy to use. The 317 shown in Fig.28 is a positive voltage
regulator. The 337 is a negative voltage regulator with similar to the 317.In each
case, input and output terminals are provided for supply and regulator output
voltage and a third adjust terminal (ADJ) is included to facilitate output voltage

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selection. The Pin configuration and its functions of LM317 are as shown in
Fig.29

Fig.29 LM 317 Pin configuration and its functions

The internal reference voltage is typically 1.25 V, and it appears across the ADJ
and Vout terminals, giving a regulator output voltage of,

𝑽𝒓𝒆𝒇 (𝑹𝟏 +𝑹𝟐 )

𝑽𝒐𝒖𝒕 = (𝟏)
𝑹𝟏

To determine the suitable values for R1 and R2 for a desired output voltage, I1is
first selected to be much greater than the current the flows in the adjustment
terminal of the device. This is a maximum of 100μA, according to the device data
sheet. Then the resistors are calculated using Eq. (1).

An appropriate supply voltage should be selected each time a regulator is

designed. Once again, to avoid a high amplitude output ripple, the supply voltage
at the lowest point on the ripple waveform should be at least 3V greater than the
regulated output voltage. The total power dissipation in the device should be
calculated to ensure that the IC will operate satisfactory.

Capacitor C1 helps to eliminate oscillation tendencies that might occur with long
connecting leads between the filter and the regulator circuit. Typically, no
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 Op-Amp and Linear ICs 18EE46

capacitors are needed unless the device is situated more than 6 inches from the
input filter capacitors, in which case an input bypass is needed. An optional output
capacitor C2 can be added to improve transient response.

Applications of LM317

• Automotive LED Lighting

• Post Regulation for Switching Supplies

• Constant Current Regulators

• Microprocessor Supplies

• Desktop PC

• Digital Signage and Still Camera

• ECG Electrocardiogram

• Energy Harvesting

• Ethernet Switch

• Fingerprint and Iris Biometrics

• HVAC: Heating, Ventilating, and Air Conditioning

• High-Speed Data Acquisition and Generation

• Hydraulic Valve

• IP Phone: Wired and Wireless

• Intelligent Occupancy Sensing

• Motor Control: Brushed DC, Brushless DC, Low-Voltage, Permanent Magnet,

and Stepper Motor

• Point-to-Point Microwave Backhaul

• Power Bank Solutions

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• Power Line Communication Modem

• Power Over Ethernet (PoE)

• Power Quality Meter

• Power Substation Control

• RFID Reader

• Refrigerator

• Signal or Waveform Generator

• Software Defined Radio (SDR)

• Washing Machine: High-End and Low-End

• X-ray: Baggage Scanner, Medical, and Dental

Applications of LM337

• Applications Requiring Negative Output Voltage or Precision Current

Regulation

• Consumer Electronics

• End Equipment

• Portable Applications
8. Calculate the resistances of R1 and R2 for the LM317 voltage regulator in
Fig.28, to produce an output voltage of 9V

Solution: I1 >>> (Iadj=100μA) Let I1=5mA

𝑉𝑟𝑒𝑓 1.25𝑉
𝑅1 = = = 250Ω (𝑢𝑠𝑒 270Ω and recalculate I1 )
𝐼1 5𝑚𝐴

𝑉𝑟𝑒𝑓 1.25𝑉
𝐼1 = = ≈ 4.6 𝑚𝐴
𝑅1 270Ω

𝑽𝟎 − 𝑽𝑹𝟏 𝟗𝑽 − 𝟏. 𝟐𝟓𝑽
𝑹𝟐 = = = 𝟏. 𝟕 𝑲𝛀 (𝐮𝐬𝐞 𝐚 𝟏. 𝟓𝐤𝛀 𝐚𝐧𝐝 𝐚 𝟐𝟐𝟎𝛀 𝐢𝐧 𝐬𝐞𝐫𝐢𝐞𝐬
𝑰𝟏 𝟒. 𝟔𝒎𝑨

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Module-3
Signal generators: Triangular / rectangular wave generator, phase shift
oscillator, saw tooth oscillator.
Comparators & Converters: Basic comparator, zero crossing detector,
inverting & non-inverting Schmitt trigger circuit, voltage to current converter
with grounded load, current to voltage converter and basics of voltage to
frequency and frequency to voltage converters.

Triangular / rectangular wave generator

A triangular/Rectangular wave form generator can be constructed simply by
using an integrating circuit and a Schmitt trigger circuit.Fig.1 shows Triangular /
rectangular wave generator circuit. It consists of an integrator and non-inverting
Schmitt trigger circuit. Schmitt output is applied as an input to the integrator and
the integrator output is the Schmitt circuit input.
As illustrated by the waveform diagram in Fig.1, The integrator produces a
triangular output waveform when it has a square wave input. The Schmitt trigger
changes from one saturation voltage level to the other each time the integrator
output arrives at the Schmitt upper or lower trigger point.
At time instant t1, integrator output is at the UTP and the Schmitt output is at +
Vo(sat).The positive input voltage to the integrator causes current I1 to flow through
R1 and C1 as illustrated. I1 charges C1 positive on the left and negative on the
right, thus producing a negative-going ramp output from the integrator during the
time interval t1 to t2.
At time t2, the ramp voltage arrives at the Schmitt LTP. The Schmitt output
immediately switches from +V0(sat) to -V0(sat) and reverses the direction of I1.C1
is now discharged and recharged with the opposite polarity generating a positive-
going ramp output voltage. The positive-going ramp continues during time
interval t2 to t3 until it arrives at the Schmitt UTP. At this point, the Schmitt output
switches to + Vo(sat) once again and the cycle recommences.
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The circuit is a free running signal generator producing triangular and

square output waveforms.

Fig.1Triangular/rectangular waveform generator

Frequency and duty cycle adjustment

The frequency of the triangular and square wave output from the circuit in fig.1
can be adjusted by including a variable resistor in series with R1. Increasing the
resistance reduces the level of capacitor charging current, thus charging c 1 more
slowly and increasing the time intervals t1 to t2 and t2 to t3.This constitutes an
increase in time period T and a reduction in output frequency. Decreasing the
total resistance at the integrator input reducers the capacitor charging times and
increases output frequency. In fig. 2(a), resistor R4 is connected in series with the
integrator input to provide frequency adjustment.
Along with R4, resistors R5, R6 and R7 in fig.2a have an effect on the capacitor
charging times. Ignoring R5 for the moment, it is seen that when the Schmitt

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output voltage is positive, current I1 flows through diode D1 and resistor R6 to

charge capacitor C1. when the Schmitt output is negative, the capacitor current
is I2,flowing through D2 and R7.

Fig.2 Triangular/rectangular waveform generator with frequency and duty cycle controls

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Now note that I1 also flows through R5a( the top portion of potentiometer R5) and
that I2 flows through R5b( the bottom portion of R5) . With the moving contact
exactly at the centre of R5 and R6 equal to R7, I1 will equal I2. Consequently, the
time intervals t1 to t2 and t2 to t3 will be equal, as in fig.1. With the moving contact
adjusted to make R5a smaller than R5b, I1will be larger than I2 and C1 will charge
faster during the time interval t1 to t2 than during t2 to t3 .This gives a saw-tooth
output waveform from the integrator and a pulse output from the Schmitt as
illustrated in fig.2b
When the R5 moving contact is adjusted to make R5a larger R5b, I2 is larger than
I1. This makes the interval t1 to t2 longer than t2 to t3 and gives the kind of saw-
tooth and pulse outputs illustrated in fig.2c.
Duty cycle of the pulse waveform is the ratio of the positive pulse width to the
time period T. So, the duty cycle of output waveform is controlled by adjustment
of potentiometer R5.The circuit in fig.2a is a ramp and pulse waveform generator
with the frequency adjustment afforded by R4 and duty cycle adjustment provided
by R5.

Waveform Generator Design

To design Triangular/Rectangular Waveform Generator, the output
frequency and duty cycle must be specified.
From the frequency and duty cycle, the time durations of the maximum
and minimum pulse widths at the high and low frequencies can be
determined.
The non-inverting Schmitt Circuit Design:
I3 >>>> IB(max)
Let I3=50μA
𝑉𝑜(𝑠𝑎𝑡)
Determine R2 by using the formula: 𝑅2 = (1)
𝐼3

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Choose the standard value of resistance near to calculated R2 and then recalculate
𝑉𝑜(𝑠𝑎𝑡)
I3 by using : 𝐼3 = (2)
𝑅2 (𝑠𝑡𝑑 𝑣𝑎𝑙𝑢𝑒)

𝑈𝑇𝑃
𝑅3 = (3)
𝐼3

Integrator Design:
To calculate the capacitance C1, the following equation is used:
𝐼1 ∆𝑡
𝐶1 = (4)
∆𝑉
Where I1= I1(min)= 50μA for 741 op-amp
Δt=PW(max) at the lowest output frequency
ΔV=UTP-LTP.
Minimum I1 level requires that R4 be a maximum and that all of R5 be in series
with resistor R6.Therefore,
+𝑉𝑜(𝑠𝑎𝑡) − 𝑉𝐹
𝑅4 + 𝑅5 + 𝑅6 = (5)
𝐼1(𝑚𝑖𝑛)

Where VF is the forward voltage drop of diode D1.

The output frequency is at its highest when R4 is adjusted to zero. Also, the ratio
of charging currents for maximum pulse width at lowest frequency f1 and
maximum pulse width at the high frequency f2 is
𝐼𝑓1 𝑓1
= (6)
𝐼𝑓2 𝑓2
Or
𝐼1(min) 𝑓1
= (7)
𝐼𝑓2 𝑓2

Therefore
𝑓2
𝐼𝑓2 = 𝐼 (8)
𝑓1 1(min)

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If2 is determined from equation (8),

+𝑉𝑜(𝑠𝑎𝑡) − 𝑉𝐹
𝑅5 + 𝑅6 = (9)
𝐼𝑓2
The resistance R4 is calculated by using Eq(5) and (9).
For maximum pulse width (positive) pulse width, all of R5 must be in series with
R6 where as for minimum pulse width no part of R5 is in series with R6. Therefore,
𝑅5 + 𝑅6 𝑃𝑊(𝑚𝑎𝑥)
= (10)
𝑅6 𝑃𝑊(min)

Note that for Eq(10) PW(max) and PW(min) must be calculated at the same
frequency.
R5 and R6 are calculated by using the Eq. (9) and (10)
For equality in the output pulse width and space width adjustments, the resistance
of R7 should equal R6.
The required op-amp slew rates are determined from the usual considerations of
output waveform distortion.
The diode reverse recovery times must be much smaller than minimum pulse
width at the highest at the highest frequency.
Solved problems
1. A triangular/rectangular signal generator is to be designed to have a 5V peak-
to-peak triangular output, a frequency ranging from 200Hz to 2KHz, and a
duty cycle adjustable from 20% to 80%. Bipolar op-amps with a supply of
±15V are to be used. Determine suitable components values.
Solution:

The non-inverting Schmitt Circuit Design:

I3 >>>> IB(max)
Let I3=50μA
Determine R2 by using the formula:

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𝑉𝑜(𝑠𝑎𝑡) (15𝑉−1𝑉)
𝑅2 = = ≈ 280𝑘Ω (1)
𝐼3 50𝜇𝐴

Use 270 KΩ standard value and recalculate I3

𝑉𝑜(𝑠𝑎𝑡) 15𝑉−1𝑉
𝐼3 = = ≈ 52𝜇𝐴 (2)
𝑅2 (𝑠𝑡𝑑 𝑣𝑎𝑙𝑢𝑒) 270𝑘Ω

𝑈𝑇𝑃 5𝑉/2
𝑅3 = = = 48𝐾Ω (Use 47 KΩ and 1KΩ ) (3)
𝐼3 52𝜇𝐴

Integrator Design:
Let C1 charging current be I1= I1(min)= 50μA
At lowest frequency f1, PW(max)=80% of T(max)
1 1
𝑃𝑊(𝑚𝑎𝑥) = 0.8 𝑋 = 0.8 𝑋 = 4𝑚𝑠
𝑓1 200𝐻𝑧
𝐼1 ∆𝑡 50𝜇𝐴 𝑋 4𝑚𝑠
𝐶1 = = = 0.04 𝜇𝐹
∆𝑉 5𝑉
Minimum I1 level requires that R4 be a maximum and that all of R5 be in series
with resistor R6.Therefore,
+𝑉𝑜(𝑠𝑎𝑡) − 𝑉𝐹 14𝑉 − 0.7𝑉
𝑅4 + 𝑅5 + 𝑅6 = = = 266 𝐾 Ω
𝐼1(𝑚𝑖𝑛) 50𝜇𝐴
i.e
𝑅4 + 𝑅5 + 𝑅6 = 266 𝐾 Ω (4)

𝑓2 2𝐾𝐻𝑧
𝐼𝑓2 = 𝐼 = 𝑋 50𝜇𝐴 = 500 𝜇𝐴
𝑓1 1(min) 200𝐻𝑧

+𝑉𝑜(𝑠𝑎𝑡) − 𝑉𝐹 14𝑉 − 0.7𝑉

𝑅5 + 𝑅6 = = ≈ 26.6𝐾Ω
𝐼𝑓2 500 𝜇𝐴

𝑅5 + 𝑅6 = 26.6𝐾Ω (5)

The resistance R4 is calculated by using Eq(4) and (5).

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𝑅4 = 266 𝐾 Ω − (𝑅5 + 𝑅6 )
= 266 𝐾 Ω − (26.6𝐾Ω ) = 240𝐾 Ω (Use 250 KΩ std value potentiometer)

1 1
𝑃𝑊(𝑚𝑎𝑥) = 0.8 𝑋 = 0.8 𝑋 = 4𝑚𝑠
𝑓1 200𝐻𝑧
1 1
𝑃𝑊(𝑚𝑖𝑛) = 0.2 𝑋 = 0.2 𝑋 = 1𝑚𝑠
𝑓1 200𝐻𝑧
𝑅5 + 𝑅6 𝑃𝑊(𝑚𝑎𝑥) 4𝑚𝑠
= = =4
𝑅6 𝑃𝑊(min) 1𝑚𝑠
𝑅5 + 𝑅6
=4 (6)
𝑅6
Using Eq. (5) and (6)
26.6𝐾Ω
=4
𝑅6
R6=6.6 KΩ (use 6.8 KΩ standard value)
From Eq,(5)
𝑅5 = 26.6𝐾Ω − 𝑅6
𝑅5 = 26.6𝐾Ω − 6.6𝐾Ω = 20 𝐾Ω
𝑅7 = 𝑅6 = 6.8𝐾Ω

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RC Phase Shift Oscillator:

RC Phase Shift Oscillator basically consists of an amplifier and a feedback
network consisting of resistors and capacitors arranged in ladder fashion. Hence
such an oscillator is also called ladder type RC Phase Shift Oscillator.

To understand the operation of this oscillator let us study RC circuit first, which
is used in the feedback network of this oscillator. The Fig. 3 shows the basic RC
circuit.

Fig.3 (a) Circuit diagram (b) Phasor Diagram

The capacitor C and resistance R are in series. Now Xc is the capacitive reactance
in ohms given by,

The total impedance of the circuit is,

The r.m.s. value of the input voltage applied is say Vi volts. Hence the current is
given by,

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From expression of current it can be seen that current I leads input voltage V i by
angle

The output voltage VR is the drop across resistance R given by,

The voltage across the capacitor is,

The drop VR is in phase with current I while the drop Vc lags current I by 90°
i.e. I leads Vc by 90°. The phasor diagram is shown in the Fig. 3 (b).

By using proper values of R and C, the angle is adjusted in practice equal to

60°

RC Feedback Network
As stated earlier, RC network is used in feedback path. In oscillator, feedback
network must introduce a phase shift of 180° to obtain total phase shift around a
loop as 360°. Thus if one RC network produces phase shift of 60° then to produce
phase shift of 180° such three RC networks must be connected in cascade.

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Hence in RC phase shift oscillator, the feedback network consists of three RC

sections each producing a phase shift of 60°, thus total phase shift due to feedback
is 180° (3x 60°). Such a feedback network is shown in the Fig. 4

Fig.4 Feedback network in RC phase shift oscillator

The network is also called the ladder network. All the resistance values and all
the capacitance values are same, so that for a particular frequency, each section
of R and C produces a phase shift of 60°.

RC Phase Shift Oscillator Using Op amp

R-C phase shift oscillator using op-amp employs op-amp in inverting amplifier
mode. Thus it introduces the phase shift of 180° between input and output. The
feedback network consists of 3 RC sections each producing 60° phase shift. Such
a RC phase shift oscillator using op-amp is shown in the Fig. 5.

The output of amplifier is given to feedback network. The Output of feedback

network drives the amplifier. The total phase shift around a loop is 180° of
amplifier and 180° due to 3 RC section, thus 360°. This satisfies the required
condition for positive feedback and circuit works as an oscillator.

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Circuit 1

Circuit2
Fig.5 R-C Phase Shift oscillator using op-amp

The frequency of sustained oscillations generated depends on the values of R and

C and is given by,

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The frequency is measured in Hz.

At this frequency the gain of the op-amp must be at least 29 to satisfy Ap = 1.

Now gain of the op-amp inverting amplifier is given by,

Thus circuit will work as an oscillator which will produce a sinusoidal waveform
if gain is 29 and total phase shift around a loop is 360°. This satisfies the
Barkhausen criterion for the oscillator. These oscillators are used over the audio
frequency range i.e. about 20 Hz up to 100 kHz.

Advantages
The advantages of R-C phase shift oscillator are,

1. The circuit is simple to design.

2. Can produce output over audio frequency range.
3. Produces sinusoidal output waveform. –
4. It is a fixed frequency oscillator.
Disadvantages
1. By changing the values of R and C, the frequency of the oscillator can be
changed. But the values of R and C of all three sections must be changed
simultaneously to satisfy the oscillating conditions. But this is practically
impossible. Hence the phase shift oscillator is considered as a fixed frequency
oscillator, for all practical purposes.

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2. And the frequency stability is poor due to the changes in the values of various
components, due to effect of temperature, aging etc.

Problem 2. Design the phase shift oscillator so that fC =200 HZ

1 1
𝑅= = = 3.25𝐾Ω (𝑢𝑠𝑒 3.3𝐾Ω)
2𝜋√6𝑓0 𝐶 2𝜋√6 ∗ 200 ∗ 0.1𝜇

Sawtooth Wave Generator

Fig.6 Sawtooth Generator (a) Circuit Diagram (b) Waveform

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The sawtooth wave generators have wide application in time-base generators and
pulse width modulation circuits. The difference between the triangular wave and
sawtooth waveform is that the rise time of triangular wave is always equal to its
fall of time while in saw tooth generator, rise time may be much higher than its
fall of time , vice versa. The triangular wave generator can be converted in to a
sawtooth wave generator by injecting a variable dc voltage into the non-inverting
terminal of the integrator.

Sawtooth Generator circuit is as shown in Fig.6.In this circuit a potentiometer, R4

which is connected to +VCC and -VEE is used. The output of integrator is a
triangular wave riding on some dc level that is a function of R4 setting. The duty
cycle of square wave will be determined by the polarity and amplitude of dc level.
A duty cycle less than 50% will cause output of integrator be a sawtooth. With
the wiper at the centre of R4, the output of integrator is a triangular wave. when
the wiper of potentiometer moves towards −VEE,the rise time of the sawtooth
become longer than the fall time. If the wiper moves towards +VCC , the fall time
becomes more than the rise time.Also frequency of the sawtooth wave decreases
as R4 is adjusted is adjusted toward +Vcc or -VEE. However the amplitude of the
sawtooth wave is independent of the R4 setting.

Comparator Op Amp Circuit:

In the op-amp applications discussed so far, the amplifiers use negative feedback.
Under normal conditions, when negative feedback is used in such a circuit, the
amplifier output voltage takes on values between the positive and negative
saturation limits. The amplifier has a high gain and negative feedback forces the
voltage between the differential inputs to be small at all times.

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When op-amp is used without feedback (open loop operation), the amplifier
output is usually in one of its saturated states. The application of a small differ-
ence input signal of appropriate polarity causes the output to switch to its other
saturation states.

Therefore, a Comparator Op Amp Circuit is a circuit with two inputs and a single
output. The two inputs can be compared with each other, i.e., one of them can be
considered a reference terminal.

When the non-inverting input is higher or greater than the inverting input voltage,
the output of the comparator is high and when the non-inverting voltage is less
than the latter output of the Comparator Op Amp Circuit is low.

Comparators are used in circuits such as digital interfacing, schmitt triggers,

discriminators, voltage level detectors, and oscillators

Non-inverting Op-amp Comparator Circuit

The Fig.7 shows a Non-inverting Op-amp Comparator Circuit and It is called a

non-inverting comparator circuit as the sinusoidal input signal Vin is applied to
the non-inverting terminal. The fixed reference voltage Vref is given to the
inverting terminal (-) of the op-amp.

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Fig.7 Non-Inverting Comparator Circuit

When the value of the input voltage Vin is greater than the reference voltage Vref
the output voltage Vo goes to positive saturation. This is because the voltage at
the non-inverting input is greater than the voltage at the inverting input.
However,When the value of the input voltage Vin is less than the reference voltage
Vref ,the output voltage Vo goes to negative saturation. This is because the voltage
at the non-inverting input is less than the voltage at the inverting input.Fig.8
shows the input and output waveforms for both positive and negative Vref. i.e

V0 = A ( V+ - V_ )

If V+ > V_ then ( V+ - V_ ) is positive Hence, Vo is positive

If V+ < V_ then ( V+ - V_ ) is negative hence Vo is negative

Fig.8. Op-amp Non-inverting Comparator Waveform

The circuit diagram included the diodes D1and D2. These two diodes are used
to protect the op-amp from damage due to increase in input voltage. These diodes
are called clamp diodes as they clamp the differential input voltages to either 0.7V
or -0.7V. Most op-amps do not need clamp diodes as most of them already have

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built in protection. Resistance R1 is connected in series with input voltage Vin and
R is connected between the inverting input and reference voltage Vref. R1 limits
the current through the clamp diodes and R reduces the offset problem.

Inverting Op-amp Comparator Circuit

The inverting comparator circuit is as shown in Fig.9.It is called an inverting

comparator circuit as the sinusoidal input signal Vin is applied to the inverting
terminal. The fixed reference voltage Vref is given to the non-inverting terminal
(+) of the op-amp. A potentiometer is used as a voltage divider circuit to obtain
the reference voltage to the non-inverting input terminal. Bothe ends of the POT
are connected to the dc supply voltage +VCC and -VEE. The wiper is connected to
the non-inverting input terminal. When the wiper is rotated to a value near +VCC,
Vref becomes more positive, and when the wiper is rotated towards -VEE, the value
of Vref becomes more negative. We have V0 = A ( V+ - V-)
If V+ > V- then ( V+ - V- ) is positive Hence, Vo is positive
If V+ < V- then ( V+ - V- ) is negative, Hence Vo is negative.
The op-amp inverting comparator input and output waveforms are as shown in
Fig.10.

Fig.9 Inverting Comparator Circuit

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Fig.10 Op-amp Non-inverting Comparator Waveform

Comparator Characteristics

1. Operation Speed – According to change of conditions in the input, a

comparator circuit switches at a good speed between the saturation levels and the
response is instantaneous.

2. Accuracy – Accuracy of the comparator circuit causes the following

characteristics:-

(a) High Voltage Gain – The comparator circuit is said to have a high voltage
gain characteristic that results in the requirement of smaller hysteresis voltage.
As a result the comparator output voltage switches between the upper and lower
saturation levels.

(b) High Common Mode Rejection Ratio (CMRR) – The common mode input
voltage parameters such a noise is rejcted with the help of a high CMRR.

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(c) Very Small Input Offset Current and Input Offset Voltage – A negligible
amount of Input Offset Current and Input Offset Voltage causes a lesser amount
of offset problems. To reduce further offset problems, offset voltage
compensating networks and offset minimizing resistors can be used.

Zero crossing detector circuit Using Op-Amp

The zero crossing detector circuit is an important application of the op-amp
comparator circuit. It can also be called as the sine to square wave converter. Any
one of the inverting or non-inverting comparators can be used as a zero-crossing
detector. The only change to be brought in is the reference voltage with which the
input voltage is to be compared, must be made zero (Vref = 0V). An input sine
wave is given as Vin. An inverting zero crossing detector is as shown in Fig.11a
and corresponding waveforms are shown in Fig.11b.

Fig.11 inverting Zero crossing detector (a) Circuit diagram (b) Waveform

As shown in the waveform, for a reference voltage 0V, when the input sine wave
passes through zero and goes in positive direction, the output voltage Vout is
driven into negative saturation. Similarly, when the input voltage passes through
zero and goes in the negative direction, the output voltage is driven to positive
saturation. The diodes D1 and D2 are also called clamp diodes. They are used to

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protect the op-amp from damage due to increase in input voltage. They clamp the
differential input voltages to either +0.7V or -0.7V.

In certain applications, the input voltage may be a low frequency waveform. This
means that the waveform only changes slowly. This causes a delay in time for the
input voltage to cross the zero-level. This causes further delay for the output
voltage to switch between the upper and lower saturation levels. At the same time,
the input noises in the op-amp may cause the output voltage to switch between
the saturation levels. Thus zero crossing are detected for noise voltages in
addition to the input voltage. These difficulties can be removed by using
a regenerative feedback circuit with a positive feedback that causes the output
voltage to change faster thereby eliminating the possibility of any false zero
crossing due to noise voltages at the op-amp input.
The applications of zero crossing detector are as follows.
 It is used to track the change in the sine waveform from positive to negative
or vice versa while it crosses Zero voltage.
 It can also be used as a Square Wave Generator.
 Zero Crossing Detector has many applications like time marker generator,
phase meter, frequency counter etc.
Schmitt Trigger Circuit
Schmitt trigger is an electronic circuit with positive feedback which holds the
output level till the input signal to comparator is higher than the threshold.
It converts a sinusoidal or any analog signal to digital signal. It exhibits hysteresis
by which the output transition from high to low and low to high will occur at
different thresholds. Schmitt trigger devices are typically used in signal
conditioning applications to remove noise from signals used in digital circuits,
particularly mechanical contact bounce in switches. They are also used in closed
loop negative feedback configurations to implement relaxation oscillators, used
in function generators and switching power supplies.
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Inverting Schmitt Trigger Circuit

A Schmitt Trigger Circuit Diagram is a fast-operating voltage level detector.

When the input voltage arrives at a level determined by the circuit components,
the output voltage switches rapidly between its maximum positive level and its
maximum negative level. The circuit diagram and i/p-o/p waveforms as shown in
Fig.12

Fig.12 Op-amp Inverting Schmitt trigger Circuit Diagram and input and output waveforms

An op-amp inverting Schmitt Trigger Circuit Diagram is shown in Fig. 12

together with input and output waveforms. At first glance the circuit looks like a
non-inverting amplifier. But note that (unlike a non-inverting amplifier) the input
voltage (Vi) is applied to the inverting input terminal, and the feedback voltage
goes to the non-inverting input. The waveforms shows that the output switches
rapidly from the positive saturation (+Vo(sat)) voltage to the negative saturation
level (-Vo(sat)) when the input exceeds a certain positive level called the upper
trigger point (UTP). Similarly, the output voltage switches from low to high
when the input goes below a negative triggering point called the lower trigger
point (LTP).

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Note that after Vi has increased to the UTP and Vo has switched to -Vo(sat), the
output remains at -Vo(sat) even when Vi falls below the UTP. Switch over from -
Vo(sat) to +Vo(sat) does not occur until Vi = LTP. Similarly, after Vi has been
reduced to the LTP and Vo has switched to +Vo(sat), the output remains
at +Vo(sat) when Vi is increased above the LTP. Switch-over from +Vo(sat) to -
Vo(sat) does not occur again until Vi = UTP.

Triggering Points:
If the output voltage to the circuit in Fig. 12 is high, the voltage at the non-
inverting terminal is,

If the input voltage (at the inverting input terminal) is below VR2 (at the non-
inverting input), the output voltage is kept at its high positive level. For the output
to switch to its low level, the input voltage must exceed V R2 by a very small
amount (approximately 70 μV for a 741 op-amp). So, the UTP essentially equals
VR2.

When the output is negative, the LTP can be calculated as,

Input/ Output Characteristic:

A graph of output voltage (Vo) versus input voltage (Vi) can be plotted for an
inverting Schmitt Trigger Circuit Diagram, as shown in Fig. 13.

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 Op-Amp and Linear ICs 18EE46

Fig.13 Output/input characteristics for an inverting Schmitt trigger circuit.

Commencing with the output at +Vo(sat) and the input at zero,when Vi is raised
to UTP, the output switches from +V0(sat) to -V0(sat) ((point a to b).Any further
increase in Vi above the UTP maintains the output at - V0(sat),(Point b to
c).While input being reduced from UTP to the LTP (point b to point d). the output
remains at - V0(sat).When Vi equals the LTP, the output rapidly switches from -
V0(sat) to +V0(sat) ((point d to e).Now any further in Vi below the LTP maintains
the output voltage at +Vo(sat).

The difference between the UTP and the LTP is termed as hysteresis. Some
applications require a small amount of hysteresis, and for other applications a
large amount of hysteresis is essential.

Schmitt Circuit Design:

Design procedure for a Schmitt Trigger Circuit Diagram is similar to op-amp
amplifier design. A voltage divider current (I2 in Fig. 12) is selected much larger
than the op-amp input bias current. The resistor values are then calculated

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as,

Problem 3. Using a 741 op-amp with a supply of ±12V, design an inverting

Schmitt trigger point to have trigger point of ±2V.

Solution: I2 >>>> IB(max)

let I2=50μA

VR2 =UTP=2V

𝑽𝑹𝟐 𝟐𝑽
𝑹𝟐 = = = 𝟒𝟎𝑲𝛀
𝑰𝟐 𝟓𝟎𝝁𝑨

Use 39KΩ standard value and recalculate I2

𝑽𝑹𝟐 𝟐𝑽
𝑰𝟐 = = ≈ 𝟓𝟏. 𝟑𝝁𝑨
𝑹𝟐 𝟑𝟗𝑲𝛀

VR1=Vo(sat)-VR2≈(12V-1V)-2V=9V

𝑉𝑅1 9𝑉
𝑅1 = = = 175𝐾Ω (use 180 kΩ standard Value)
𝐼2 51.3𝜇𝐴

Adjusting the Trigger Points:

Many Schmitt trigger circuit applications require UTP and LTP levels that are not
equal in magnitude. This is usually achieved by the use of diodes. There are three
different cases for the adjustment of trigger points

Case 1: Adjusting the Trigger Points: LTP=0 and UTP ≠ 0

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The circuit shown in Fig14(a) simply has a diode (D1) connected in series with
resistor R1. The diode D1 is forward biased only when the op-amp output is a
positive quantity. At this time, the UTP is VR2.Considering diode forward voltage
drop as VF.We can write UTP as

(|𝑽𝟎 | − 𝑽𝑭 )𝑿𝑹𝟐
𝑼𝑻𝑷 = 𝑽𝑹𝟐 =
𝑹𝟏 + 𝑹𝟐

When Vo is negative, D1 is reverse biased, making I2 equal zero. Consequently,

there is no voltage drop across R2, and so the noninverting terminal is grounded
via R2. This gives a zero level for the LTP. Thus, this circuit has a positive UTP
and a zero voltage LTP.The input and output waveforms are as as shown in
Fig.14b.

The diode must have reverse recovery time much smaller than the minimum pulse
width of the signal.

𝑀𝑖𝑛. 𝑝𝑢𝑙𝑠𝑒 𝑤𝑖𝑑𝑡ℎ

𝑡𝑟𝑟 ≤
10

Fig.14 (a) Schmitt trigger with LTP=0 (b) Input and Output voltage Waveform

Case 2: Adjusting the Trigger Points: UTP=0 and LTP ≠ 0

When the output signal is positive, then Diode D1 reverse biased. So VR2=0 and
hence UTP=0.When output signal is negative, Diode D1 is forward biased.

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Considering diode forward voltage drop as VF.We can write LTP as

(|𝑽𝟎 | − 𝑽𝑭 )𝑿𝑹𝟐
𝑳𝑻𝑷 = 𝑽𝑹𝟐 = −
𝑹𝟏 + 𝑹𝟐

Fig.15 (a) Schmitt trigger with UTP=0 (b) Input and Output voltage Waveform

Case 3: Adjusting the Trigger Points: Different LTP and UTP

Fig.16 (a) Schmitt trigger with Different UTP and LTP (b) Input and Output voltage
Waveform

Figure 16(a) shows a circuit with two different-level trigger points. This circuit
is a combination of circuits of case 1 and case 2.

When Vo is positive, D1 is forward biased and D2 is reversed, and the UTP is set
by resistors R1 and R2.

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(|𝑽𝟎 | − 𝑽𝑭 )𝑿𝑹𝟐
𝑼𝑻𝑷 = 𝑽𝑹𝟐 =
𝑹𝟏 + 𝑹𝟐

With Vo negative, D2 is forward biased and D1 is reversed. The LTP is now

determined by the resistances of R3 and R2.

(|𝑽𝟎 | − 𝑽𝑭 )𝑿𝑹𝟐
𝑳𝑻𝑷 = 𝑽𝑹𝟐 = −
𝑹𝟐 + 𝑹𝟑

By adjusting the resistors R1 and R3 in the circuit, the desired UTP and LTP values
are obtained.

Another important design consideration is that the voltage divider current (I 2)

should normally be a minimum of 100 μA for satisfactory diode operation.

Problem4: Inverting Schmitt trigger circuit is to have UTP=0V and an LTP=-

2.5V. Design a suitable circuit using bipolar op-amp with ±15V supply.
Solution:
VO =±(15-1)V=±14V

(|𝑽𝟎 | − 𝑽𝑭 )𝑿𝑹𝟐 (𝟏𝟒 − 𝟎. 𝟕)𝑿𝑹𝟐

𝑳𝑻𝑷 = 𝑽𝑹𝟐 = − =
𝑹𝟏 + 𝑹𝟐 𝑹𝟏 + 𝑹𝟐

(𝟏𝟒 − 𝟎. 𝟕)𝑿𝑹𝟐
−𝟐. 𝟓𝑽 = −
𝑹𝟏 + 𝑹𝟐

2.5(R1+R2)=13.3R2

2.5R1=10.8R2

R1=4.32R2

WKT VR2=LTP=2.5V and Let I2 =50μA

𝑽𝑹𝟐 𝟐. 𝟓𝑽
𝑹𝟐 = = = 𝟓𝑲𝛀 (𝟒. 𝟕𝐊𝛀 𝐬𝐭𝐚𝐧𝐝𝐚𝐫𝐝 𝐯𝐚𝐥𝐮𝐞)
𝑰𝟐 𝟓𝟎𝟎𝝁𝑨

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 Op-Amp and Linear ICs 18EE46

R1=4.32R2=4.32 X 4.7K=20.3KΩ(22KΩ Standard Value)

Problem 5:Using a bipolar op-amp with a ±18V supply, design an inverting

Schmitt trigger Circuit to have LTP= -3V and UTP=1.5V.

Solution: VO=(18-1)V=17V

(|𝑽𝟎 | − 𝑽𝑭 )𝑿𝑹𝟐
𝑼𝑻𝑷 = 𝑽𝑹𝟐 =
𝑹𝟏 + 𝑹𝟐

(𝟏𝟕 − 𝟎. 𝟕)𝑿𝑹𝟐
𝟏. 𝟓 =
𝑹𝟏 + 𝑹𝟐

1.5(R1+R2)=16.3R2

1.5R1=14.8R2

R1=9.866R2 --(1)

(|𝑽𝟎 | − 𝑽𝑭 )𝑿𝑹𝟐
𝑳𝑻𝑷 = 𝑽𝑹𝟐 = −
𝑹𝟑 + 𝑹𝟐

(𝟏𝟕 − 𝟎. 𝟕)𝑿𝑹𝟐
−𝟑 = −
𝑹𝟑 + 𝑹𝟐

3(R3+R2)=16.7R2

R3=4.566R2 ---------(2)

For adequate diode forward current I2 =500μA

𝑽𝑹𝟐 𝟏. 𝟓𝑽
𝑹𝟐 = = = 𝟑𝑲𝛀 (𝟐. 𝟕𝐊𝛀 𝐬𝐭𝐚𝐧𝐝𝐚𝐫𝐝 𝐯𝐚𝐥𝐮𝐞)
𝑰𝟐 𝟓𝟎𝟎𝝁𝑨

R1=9.866R2 =9.866 X 2.7K=26.6382K (27KΩ Standard value)

R3=4.566*2.7K=12.32KΩ(12KΩ standard value)

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Non-inverting Schmitt Trigger:

A non-inverting Schmitt Trigger Circuit Diagram is shown in Fig.17a. This
circuit looks like an inverting amplifier, but note that (unlike an inverting
amplifier) the inverting input is grounded and the non-inverting input is
connected to the junction of R1 and R2. The waveforms in Fig17b.,show that
Vo switches rapidly from -Vo(sat) to +Vo(sat) when Vi arrives at the UTP, and that
Vo switches back to -Vo(sat) when Vi falls to the LTP.

Fig. 17 Non-inverting schmitt trigger circuit (a)Circuit (b)Input and output Waveforms

Suppose that input voltage is at ground ground level and the output voltage is at
its negative saturation level. The voltage across resistor R1 is

𝑉𝑜 𝑋 𝑅1
𝑉𝑅1 =
𝑅1 + 𝑅2

With Vo negative, VR1 is a negative quantity. Thus, the non-inverting input

terminal is negative with respect to the (grounded) inverting input terminal and
the output voltage is held at the negative saturation level.

To cause the output to switch from the negative saturation level to positive
saturation, the input voltage must be raised until the voltage at the non-inverting

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input terminal is just slightly(microvolts) above ground level.This is illustrated in

Fig.18b.with non-inverting terminal at ground level, the output voltage Vo is
developed across resistor R2 and the input voltage Vi appears across R1.
Therefore, the UTP for this circuit is

Fig.18 Non-inverting Schmitt trigger

UTP=Vi=I2R1

|𝑉0 |
Where 𝐼2 =
𝑅2

|𝑉0 |
Giving 𝑈𝑇𝑃 = 𝑋𝑅1
𝑅2

When the input voltage switches to the positive saturation level, the voltage at the
non-inverting terminal is raised substantially above the ground, thus maintaining
the output at its positive saturation voltage. To return the output to the negative
saturation voltage, the input has to be made sufficiently negative to pull the non-
inverting terminal down to ground level. This lower trigger voltage is

|𝑉0 |
𝐿𝑇𝑃 = − 𝑋𝑅1
𝑅2

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Design procedure for a non-inverting Schmitt Trigger Circuit Diagram is just as

simple as for the inverting circuit. Voltage divider current I2 is again selected
much larger than the op-amp input bias current.

I2 >>>> IB(max) let I2=50μA

Then the resistor values are,

Problem 6: Design a non-inverting Schmitt trigger circuit using bipolar op-amp

to trigger at ±0.5V and to produce an output of approximately ±14V.
Solution:

Let I2 be the current flowing through R1 andR2 and Let I2 =50μA

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Adjusting the trigger points

Non-inverting Schmitt trigger circuits can be designed for different upper and
lower trigger point voltages by the use of diodes, as in the case of the inverting
circuit.

(a) (b)

(c )

Fig.19 Non-inverting Schmitt trigger with different UTP and LTP

Figure 19(a) (b) and (c) shows two possible circuits. The diode forward voltage
drop (VF) must be included in the UTP and LTP calculations.

In fig 19(a), diode D1 is reversed biased when output is positive .This makes the
voltage at the non-inverting input terminal equal to the input voltage Vi .The
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 Op-Amp and Linear ICs 18EE46

output switches from positive to negative when Vi goes just below ground level,
so the lower trigger point is zero. The upper trigger point is

(|𝑽𝟎 | − 𝑽𝑭 )𝑿𝑹𝟏
𝑼𝑻𝑷 =
𝑹𝟐

Where VF is the forward voltage drop of the diode

Fig.19(c ) shows a non-inverting Schmitt trigger circuit which has different UTP
and LTP voltage levels determined by the resistances of R2 and R3. The upper
trigger point is given by the above equation and the lower trigger point is

(|𝑽𝟎 | − 𝑽𝑭 )𝑿𝑹𝟏
𝑳𝑻𝑷 =
𝑹𝟑

Schmitt Trigger Applications

The uses of the Schmitt trigger include the following.

 Schmitt triggers are mainly used for changing a sine wave to square wave.
 They must be utilized in the switch de-bouncer circuit for a noisy otherwise
slow input requirements like to be cleaned up or speed up
 These are normally utilized in applications like signal conditioning for
removing signals noise in digital circuits.
 These are used to implement relaxation oscillators for closed loop negative
response designs
 These are used in switching power supplies as well as function generators
Problem 7: A non-inverting Schmitt trigger circuit is to have UTP=0V and
LTP=-2.5V. Design a suitable circuit using a bipolar op-amp and a ±18V
supply

Design for LTP=-2.5V

For adequate diode forward current, let I3 = 500μA

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 Op-Amp and Linear ICs 18EE46

VR1 =LTP=-2.5V

VR3=|V0|-VF =|(18V-1V)|-0.7V=16.3V

Problem 8:Design a non-inverting Schmitt trigger circuit to have UTP=+3V and

LTP=-5V. Use a 741 op-amp with VCC = ±15V.Using the selected values find the
actual UTP and LTP.

Solution:

(a) Design first for UTP

For adequate diode forward current, let

I2 = 500μA

VR1 =UTP=3V

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 Op-Amp and Linear ICs 18EE46

𝑉𝑅1 3𝑉
𝑅1 = = = 6𝐾Ω (use 5.6KΩ standard value and recalculate 𝐼2 )
𝐼2 500𝜇𝐴

𝑉𝑅1 3𝑉
𝐼2 = = ≈ 536𝜇𝐴
𝑅2 5.6𝐾

VR2=|V0|-VF =|(15V-1V)|-0.7V=13.3V

𝑉𝑅2 13.3𝑉
𝑅2 = =
𝐼2 536𝜇𝐴
= 24.8𝐾Ω (use series connected 22KΩ and 2.7KΩ standard value resistors

Now design for LTP, using the already selected resistance for R1

VR1 =LTP=-5V

𝑉𝑅1 5𝑉
𝐼3 = = ≈ 893𝜇𝐴
𝑅1 5.6𝐾Ω

VR3=|V0|-VF =|(15V-1V)|-0.7V=13.3V

𝑉𝑅3 13.3𝑉
𝑅3 = = = 14.9𝐾Ω (use 15KΩ standard value resistor)
𝐼3 893𝜇𝐴

Select the diodes , with minimum reverse voltage, VR> VCC=15V

Reverse Recovery time Trr less than (min pulse width)/10 of input signal.

|𝑉0 |−𝑉𝐹 14−0.7

(b) 𝐼2 = = = 538𝜇𝐴
𝑅2 22𝐾+2.7𝐾

UTP=I2 X R1=538μAX 5.6KΩ=3.02V

|𝑉0 | − 𝑉𝐹 14 − 0.7
𝐼2 = = = 887𝜇𝐴
𝑅3 15𝐾

UTP=-I2 X R1=-887μAX 5.6KΩ=-5V

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Current-to-voltage Converter

A current to voltage converter will produce a voltage proportional to the given

current. This circuit is required if the measuring instrument is capable of
measuring only voltages and current output needs to be measured.The current-to-
voltage (I-to-V) converter is a special case of the inverting amplifier in which
input current is converted a proportional output voltage.

One of the most common uses of the current-to-voltage converter is in digital-to-

analog converter applications and in sensing current through photo detectors such
as photocells, photodiodes and photovoltaic cells

Fig.20 Current-to-voltage Converter

Let us consider ideal voltage gain of the inverting amplifier.

Therefore,

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However, since V1=0 and V1=V2

Substituting Eq (3) in Eq(2),we get

V0= -Iin RF (4)

Vin and R1 combination in inverting amplifiers is replaced by a current source I in,

the output voltage V0 becomes proportional to the input current Iin and is as shown
in Fig.20. In other words, the circuit of Fig.20 converts the input current into a
proportional output voltage.

One of the most common uses of the current-to-voltage converter is in sensing

current from photo detectors such as photocells, photodiodes, and photovoltaic
cells and in digital-to-voltage converter applications.

Application 1:DAC using Current-to-Voltage Converter

Fig.21 shows a combination of a DAC and current to voltage converter. The 8

digit binary signal is the input to the MC1408 DAC and V 0 is the corresponding
analog output of the current to voltage converter. The output of the DAC is
current I0, the value of which depends on the logic state (0 or 1), of the binary
inputs as indicated by the Eq.(1).

Where I0=output current of the DAC (mA),R1=resistance (KΩ)

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Vref= reference voltage (volts),D0 through D7=eight binary inputs

This means that I0 is zero when all inputs are logic 0.I0 is max when all inputs are
logic 1. The variations in I0 can be converted into a desired o/p voltage range by
selecting a proper value for RF. since,

V0 = I0 RF (2)

Where I0 is given by equation eq(1).

It is common to parallel RF with capacitance C to minimize the overshoot and

ringing. In the fig.21 the o/p voltage of the current to voltage converter is positive
because the direction of input current I0 is opposite to that in the basic I – V
Converter.

Fig.21 DAC using current-to-voltage converter

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Problem 9: In the circuit of DAC using I-V converter, Vref=2V, R1=1KΩ and
RF=2.7KΩ. Assuming that the op-amp is initially nulled, determine the range for
the output V0.

Solution:

When all the binary inputs D0 to D7, are logic 0, then I0=0; therefore, minimum
value of V0=0V

However When all the binary inputs D0 to D7, are logic 1, then I0 is

Hence, maximum value of V0=I0 X RF=(1.992mA)(2.7KΩ)=5.38V

Thus the output voltage range is 0 to 5.38V

Application 2: Detecting current through photosensitive devices using I-V

converter

Fig.22 Measurement of current through the photocell using I-V converter

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Photocells, photodiodes, photovoltaic cells give an output current that depends

on the intensity of light and independent of the load. The current through this
devices can be converted to voltage by I – V converter and it can be used as a
measure of the amount of light.Fig.22 shows a photocell, the Clairex CL505L,
connected to the I-V converter .Photocell is a passive transducer, hence it
requires an external dc voltage(Vdc).The CL505L has the following
specifications.

Resistance when illuminated (at 0.61 lux) =1.5kΩ

Minimum dark resistance=100 kΩ

Measurement voltage = 10V

Temperature Range= -50° to 75°C

The circuit shown in Fig.22 can be used as a light-intensity meter by connecting

at the output of a meter that is calibrated for light intensity.

The dc voltage can be eliminated if a photovoltaic cell is used instead of a

photocell. The Photovoltaic Cell is a semiconductor device that converts the
radiant energy to electrical power. It is a self generating circuit because it does
not require dc voltage externally. Ex of Photovoltaic Cell: used in space
applications and watches.

The lower limit on current measurement with an I-to-V converter is set by the
bias current IB of the op-amp. This means that op-amps with smaller IB values,
can be used to detect lower currents.

Problem 10:In the circuit of I-V converter used to measure current through the
photocell, Vdc=5V and RF=3KΩ. Determine the change in the output voltage if

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 Op-Amp and Linear ICs 18EE46

the photocell is exposed to light of 0.61 lux from a dark condition. Assume the
op-amp is initially nulled.

Solution:

Given : The resistance RT of the CL505L in darkness is 100KΩ and resistance

when illuminated(at 0.61 lux) is 1.5KΩ

The minimum output voltage is

The maximum output voltage is

Thus V0 varies from -0.15V to -10V.

Voltage to Current Converter

In circuits in instrumentation for analog representation of certain physical

quantities (weight, pressure, motion etc), DC current is preferred. This is because
DC current signals will be constant throughout the circuit in series from the
source to the load. The current sensing instruments also have the advantage of
less noise. So, sometimes it is essential to create current which is corresponding
or proportional to a definite voltage. For this purpose Voltage to Current
Converters are used. It can simply change the carrier of electrical data from
voltage to current.

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Simple Voltage to Current Converter:

When we talk about the connection between voltage and current, it is obvious to
mention the Ohm’s law.

We all know that when we supply a voltage as input to a circuit which comprises
of a resistor, the proportional current will commence to flow through it. So, it is
clear that the resistor performs as a simple voltage to current converter for a
linear circuit.

Voltage to current converter using op-amp with grounded load:

This converter is also known as Howland Current Converter and is as shown in

Fig.23. Here, one end of the load is always grounded and load current is
controlled by input voltage. For the circuit analysis, first the voltage at the non-
inverting terminal is determined and then the relationship or the connection
between the input voltage and load current can be achieved.we apply Kirchhoff’s
current law at the node V1

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Fig.23 Voltage-to-current converter with grounded load

For a non-inverting amplifier, gain is

Hence the voltage in the output will be

Thus, we can conclude from the above equation that the current IL is related to
the voltage, VIN and the resistor, R.
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 Op-Amp and Linear ICs 18EE46

Problem 11:In the circuit of voltage to current converter with grounded load,
V voltage to current converter with grounded load Vin=5V , R=10KΩ and
V1=1V. Find (a) the load current and (b) the output voltage V0 .

Vo=2V1=2 V

Voltage-to-Frequency/Frequency-to-Voltage Converters

The TC9400/TC9401/TC9402 is low cost voltage-to-frequency (V/F) converters,

utilizing low power CMOS technology. The converters accept a variable analog
Input signal and generate an output pulse train, whose Frequency is linearly
proportional to the input voltage. The devices can also be used as highly accurate
frequency-to-voltage (F/V) converters, accepting virtually any input frequency
waveform and providing a linearly proportional voltage output. A complete V/F
or F/V system only requires the addition of two capacitors, three resistors, and
reference voltage. The pin diagram of TC9400/TC9401/TC9402 is shown in
Fig.24 and the function of various pin of IC is given in table1.
Applications of TC9400/TC9401/TC9402

• µP Data Acquisition
•13-bit Analog-to-Digital Converters
• Analog Data Transmission and Recording
•Phase Locked Loops
•Frequency Meters/Tachometer
•Motor Control
•FM Demodulation

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Fig.24 TC9400/TC9401/TC9402

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The TC9400 V/F converter operates on the principal of Charge balancing. The
operation of the TC9400 is easily understood by referring to Figure 25.The input
voltage (VIN )is converted to a current(IIN) by the input resistor. This current is
then converted to a charge on the integrating capacitor and shows up as a linearly
decreasing voltage at the output of the Op-Amp. The Lower limit of the output
swing is set by the threshold detector, which causes the reference voltage to be
applied to the reference capacitor for a time period long enough to charge the
capacitor to the reference voltage. This action reduces the charge on the
integrating capacitor by a fixed amount (q=CREF xVREF), causing the Op-Amp
output to step up a finite amount.

Fig.25 Functional block diagram of TC9400/TC9401/TC9402

At the end of the charging period, CREF is shorted out. This dissipates the charge
stored on the reference capacitor, so that when the output again crosses zero, the
system is ready to recycle. In this manner, the continued discharging of the
integrating capacitor by the input is balanced out by fixed charges from the
reference voltage. As the input voltage is increased, the number of reference
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pulses required to maintain balance increases, which causes the output frequency
to also increase. Since each charge increment is fixed, the increase in frequency
with voltage is linear. In addition, the accuracy of the output pulse width does not
directly affect the linearity of the V/F. The pulse must simply be long enough for
full charge transfer to take place.

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Module-4
Signal processing circuits: Precision half wave & full wave rectifiers.
A/D & D/A Converters: Basics, R–2R D/A Converter, Integrated circuit 8-bit
D/A, successive approximation ADC, linear ramp ADC

Precision half wave & full wave rectifiers:

Although the series diode is the classic rectifier, it can't rectify signals smaller
that it own forward voltage! But what if expected amplitude of the signal can be
as low as 100 mV? Op amps to the rescue! !!!!
The advantage of op amp circuits lies in their ability to compensate for non-
linear devices in the feedback loop. Combining the rectifying action of a diode
with the accuracy of an op amp, this circuit creates a precision rectifier.
A circuit which can act as an ideal diode or precision signal – processing
rectifier circuit for rectifying voltages which are below the level of cut-in
voltage of the diode can be designed by placing the diode in the feedback loop
of an op-amp.
Saturating precision Half Wave Rectifier:

Fig.1 Saturating precision Half Wave Rectifier Circuit

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It is simply a voltage follower with a diode inserted between the op-amp output
terminal and the circuit output point.
When the input signal is positive, the diode is forward biased and output voltage
follows the input.
We know that negative feedback causes the voltage at the inverting input
terminal to follow that at the non-inverting terminal. Since the output of the
circuit and the inverting terminal are common, the output follows the input
within micro-volts. The diode forward voltage drop is not involved.
When the input voltage is in negative half cycle, the op-amp output is negative
and the diode is reverse biased. Consequently the feedback path is interrupted.
The negative half cycle of the input does not pass to the output. it is clipped off.
If the diode polarity is reversed in fig.1, the negative half cycle of the input
waveform will be passed to the output and the positive half cycle is clipped off.
Advantages of Precision HWR
 No diode voltage drop between input and output
 The ability to rectify very small voltages (less than the typical 0.7 V
diode forward voltage drop)
 Amplification if required
 Low output impedance
Disadvantages of saturating Precision HWR
While the input waveform is in negative half cycle, the output of the op-amp in
Fig(1) is saturated in negative direction. Some time is required to get the op-
amp out of saturation and this will limit the frequency response of the circuit.
Saturating precision half wave rectifier with voltage gain
The circuit is a non-inverting amplifier, with the diode included .The circuit is
designed exactly as a non-inverting amplifier, except that the current through R1
and R2 should be minimum of 100μA to ensure the diode is operating properly

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in the absence of load current. A minimum diode current of 500 μA is a good

design objective.

Fig.2 Saturating precision half wave rectifier with voltage gain

Non-saturating Precision Rectifier circuit:

Fig.3 Non-saturating Precision Rectifier circuit

The precision rectifier circuit shown in fig.3 uses an inverting amplifier

configuration. Diode D1 is reverse biased and diode D2 is forward biased when

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the op-amp output terminal is positive. This occurs when the input signal is
negative. The output of the circuit is Vo = - R2 / R1 ∙ Vi
During the positive half cycle of the input, the op-amp output terminal goes
negative, causing diode D2 to be reverse biased and diode D1 forward biased.
The diode D1 shorts the output of the op-amp to the inverting terminal. Using
the concept of virtual ground the inverting terminal will be at ground potential
(Non-inverting terminal will be at 0 v). Hence the output of op-amp will be zero
volts.
In fig.3, the negative cycle of the input is inverted and passed to the output
while the positive cycle is clipped off. If the polarity of the two diodes are
reversed, the positive cycle of the input is inverted and passed to the output
while the negative cycle is clipped off
Design of a non-saturating precision rectifier involves the design of an inverting
amplifier. The diodes should have a maximum reverse voltage greater than the
supply voltage. They should also have a switching time that will not limit the
circuit frequency response. This requires reverse time (trr) be much smaller than
the time period of the highest signal frequency to be processed.
Problem 1. Design a non-saturating precision half wave rectifier as in fig.3 to
produce 2V peak output from a sine wave input with a peak value of 0.5V
and frequency of 1MHz. Use a bipolar op-amp with a supply voltage of ±15V.
Solution: I1 >>> IB(max)
Let I1 = 500μA (for adequate diode current)
𝑽𝒊 𝟎.𝟓𝑽
𝑹𝟏 = = = 𝟏𝑲𝛀 (standard value)
𝑰𝟏 𝟓𝟎𝟎𝝁𝑨

𝑽𝟎 𝟐𝑽
𝑹𝟐 = = = 𝟒𝑲𝛀 (𝐮𝐬𝐞 𝐬𝐭𝐚𝐧𝐝𝐚𝐫𝐝 𝐯𝐚𝐥𝐮𝐞 𝐨𝐟 𝟑. 𝟗𝐊𝛀
𝑰𝟏 𝟓𝟎𝟎𝝁𝑨
R3=R2 || R1=1KΩ || 3.9KΩ=796Ω (use 820Ω standard value)
For diodes D1 and D2 ,
VR = [VCC-(-VEE)]=15V-(-15V)] >> 30V

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Trr << T
𝑻 𝟏 𝟏
Let 𝒕𝒓𝒓(𝒎𝒂𝒙) = = = = 𝟎. 𝟏𝝁𝒔
𝟏𝟎 𝟏𝟎𝒇 𝟏𝟎 𝑿 𝟏𝑴
Two output precision rectifier

Fig.4 Two output precision rectifier

Fig.4 shows a two output precision rectifier. It has two output terminals. Diode
D2 is connected in series with the op-amp output and resistor R2 .Diode D1 is
connected in series with the op-amp output and resistor R4. During positive
cycle of input, op-amp output terminal goes negative, causing D1 to be forward
biased and D2 reversed. In this situation, the op-amp together with R1and R4
functions as an inverting amplifier to give an output at terminal B. The output at
point A remains at ground level for the duration of the positive half cycle of the
input.

During negative cycle of input, op-amp output terminal goes positive, causing
D2to be forward biased and D1 reversed. In this situation, the op-amp together

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with R1and R2 functions as an inverting amplifier to give an output at terminal

A. with D1 reversed, no current flows through R4 and hence the output at
terminal B is zero.

Concluding the circuit is a precision rectifier with positive half cycle of output
at terminal A and negative half cycle of output at terminal B.

Precision Full wave rectifier

Fig.5 positive and negative full wave rectifier

The Precision Full Wave Rectifiers circuits accept an ac signal at the input,
inverts either the negative or the positive half, and delivers both the inverted and
non-inverted halves at the output, as shown in the Fig.5.

Precision Full wave rectifier using a half wave rectifier and a summing
circuit
A Precision Full wave rectifier is as shown in fig.6.The left side of the circuit is
a precision half wave rectifier and right hand side of the circuit is an inverting
summing amplifier circuit. The input voltage is applied to terminal A of the
summing amplifier and to the input of the precision rectifier. The resistor R2 in

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precision rectifier circuit has twice the resistance of R1, so the rectified voltage
applied to terminal B of the summing amplifier is -2 Vi .

Fig.6 Precision Full wave rectifier

During positive half cycle of input, the voltage at terminal A is + Vi , while that
at terminal B is -2 Vi . The output from the summing circuit with R5=R4 is

During negative half cycle of input of the input, VA= -VI and VB=0,
consequently the output is

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The output is a full-wave rectified version of the input voltage. If resistor R6

equals R4and R5, the circuit has an overall voltage gain of 1.when resistor R6 is
greater than R4 and R5, the amplification and rectification both occur.
Problem 2: Design a precision full-wave rectifier, to produce a 2V peak
output from a sine wave input with a peak value of 0.5V and a frequency of
1MHz. Use a bipolar op-amps with a supply voltage of ±15V.
Solution:
I1 >>> IB(max)
Let I1 = 500μA (for adequate diode current)

(standard value)
R2=2R1= 2KΩ (use two 1kΩ resistors in series)
R3=R1 || R2 = 1k Ω || 2K Ω = 670 Ω (use 680 Ω std value)
R4=R5=R1=1k Ω (standard value)
For the output to be 2V when the input is 0.5V

R7=R4 ||R5|| R6=1K || 1K|| 3.9K=443Ω (use 470Ω std value)

For diodes D1 and D2 ,
VR = [VCC-(-VEE)]=15V-(-15V)] >> 30V
T rr << T

High input impedance Full wave precision Rectifier

A precision rectifier that uses a non-inverting amplifier configuration to present

a high input impedance is as shown in Fig.7.Op-amp A1 together with resistors
R3 and R4 constitutes a non-inverting amplifier, as does A2,R5 and R6.However,
diodes D1 and D2 also affect the operation of the circuit.

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Fig.7 High input impedance Full wave precision Rectifier

During positive half-cycle of the input waveform, the output terminal of A2

is positive, D2 is forward-biased, and D1 reversed. The voltage at the junction
of resistors R5 and R6 (terminal C) follows Vi at the non-inverting input
terminal of A2 .The voltage at the junction of R3 and R4 (terminal A) also
follows the input voltage applied to the non-inverting input of A1. With Vi
appearing at terminal A and at terminal C, there is no current flowing
through R3 and no voltage drop across R3.So,the circuit output voltage is the
same as that at terminal A; that is Vi .
When the input voltage goes negative,D2 is reverse biased and D1 is forward
biased giving an output at the junction of R4 and R5 (terminal B). Since
R5=R6, the voltage at terminal B is 2(-Vi).A1, R3 and R4 constitute an
inverting amplifier to voltages applied at the bottom of R 4. and a non-
inverting amplifier for voltages applied to R1, the circuit output would be
𝑅3 + 𝑅4
𝑉𝑥 = (−𝑉𝑖 )
𝑅4
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With R3=2R4
Vx= -3Vi
With voltage -2Vi terminal B, output voltage would be
𝑹𝟑
𝑽𝒚 = (−𝟐𝑽𝒊 ) (− )
𝑹𝟒
With R3=2R4
Vx= 4Vi
Applying superposition theorem, the output voltage is the sum of VX and Vy
Vo=VX+Vy =-3V+4Vi = Vi
Hence output voltage equals input and is positive when the input is negative.
To design this type of precision FWR, R6 is first calculated then R4= R5= R6 and
R3= 2R4
To design this type of precision FWR, R6 is first calculated then R4= R5= R6 and
R3= 2R4

Problem 3: Using bipolar op-amp with Vcc=±15V, Design the high input
impedance precision full-wave rectifier circuit. The input peak voltage is 1V
and no amplification occur.
Let I6=500μA (for adequate diode current)
𝑽𝒊 𝟏𝑽
𝑹𝟔 = = = 𝟐𝑲𝛀 (𝑼𝒔𝒆 𝟏. 𝟖𝑲𝛀 𝒔𝒕𝒂𝒏𝒅𝒂𝒓𝒅 𝒗𝒂𝒍𝒖𝒆)
𝑰𝟔 𝟓𝟎𝟎𝝁𝑨
R4= R5= R6=1.8KΩ
R3= 2R4=3.6KΩ (use two 1.8KΩ resistors in series)
R1=R3 || R4 =3.6K || 1.8K =1.2KΩ (std value)
R2=R6 || R5 =1.8K || 1.8K =900Ω (use 1KΩ std value)

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Introduction to A/D & D/A Converters

Connecting digital circuitry to sensor devices is simple if the sensor devices are
inherently digital themselves. Switches, relays, and encoders are easily
interfaced with gate circuits due to the on/off nature of their signals. However,
when analog devices are involved, interfacing becomes much more complex.
What is needed is a way to electronically translate analog signals into digital
(binary) quantities, and vice versa. An analog-to-digital converter, or ADC,
performs the former task while a digital-to-analog converter, or DAC, performs
the latter.
An ADC inputs an analog electrical signal such as voltage or current and
outputs a binary number. In block diagram form, it can be represented as such

A DAC, on the other hand, inputs a binary number and outputs an

analog voltage or current signal. In block diagram form, it looks like this:

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Together, they are often used in digital systems to provide complete interface
with analog sensors and output devices for control systems such as those used
in automotive engine controls:

Basic DAC technique:

Fig.1 schematic of a DAC

The input is an n-bit binary word D and is combined with a reference voltage
VR to give an analog output signal.The output of is either voltage or current.

𝑉𝑂 = 𝐾𝑉𝐹𝑆 (𝑑1 2−1 + 𝑑2 2−2 + … … … … … . +𝑑𝑛 2−𝑛 ) (1)

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Weighted Resistor DAC

Fig.2 Weighted Resistor DAC

The circuit shown in fig.2 uses a summing amplifier with binary weighted
resistor network. It has n-electronic switches d1,d2,……….., dn controlled by
binary input word. These switches are single pole double throw (SPDT) type.
The reference voltage is (-VR).
If binary input is ‘zero’, the switch connects it to ground. If input is ‘1’,the
switch is connected to –VR.
Applying KCL at the inverting terminal we get,
IO=I1+I2+I3+………………+In (2)
𝑉𝑅 𝑉𝑅 𝑉𝑅 𝑉𝑅
𝐼0 = 𝑑1 + 2 𝑑2 + 3 𝑑3 + ⋯ + 𝑛 𝑑𝑛
2𝑅 2 𝑅 2 𝑅 2 𝑅
Or,
𝑉0 𝑉𝑅 𝑑1 𝑑2 𝑑3 𝑑𝑛
= ( + 2 + 3 + ⋯ + 𝑛)
𝑅𝑓 𝑅 2 2 2 2
Or

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𝑅𝑓
𝑉0 = 𝑉𝑅 (𝑑1 2−1 + 𝑑2 2−2 + 𝑑3 2−3 + ⋯ + 𝑑𝑛 2−𝑛 ) (3)
𝑅

Comparing the above equation with the general expression of DAC we get,
𝑅𝑓
VR =VFS , 𝐾 =
𝑅

If, Rf=R then K=1, full scale voltage (VFS) =VR

𝑉0 = 𝑉𝑅 (𝑑1 2−1 + 𝑑2 2−2 + 𝑑3 2−3 + ⋯ + 𝑑𝑛 2−𝑛 ) (4)
Transfer Characteristics of a 3-bit DAC which shows the analog output v/s
digital input is as shown in fig.3.

Fig.3 Transfer Characteristics of a 3-bit DAC

R-2R ladder DAC

R-2R ladder DAC uses only two values of resistor and hence it is easy to
fabricate all resistors on a chip. The typical values of R ranges from 2.25 KΩ to
10kΩ.
The resistors (R-2R) are so arranged as to form a ladder network as shown in
Fig.4.

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Fig.4 R-2R Ladder DAC

Let the digital input be a 3-bit digital word D=100. i.e d1=1,d2=0, d3=0 and
circuit is redrawn as shown in fig.5

Fig.5
To calculate voltage at node 3 (V3), calculate equivalent voltage to the left of
node.

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Fig.6 Finding equivalent resistance

The equivalent resistance to the left of node 3 is 2R. The modified circuit is as
shown in Fig.7

Fig.7 Equivalent resistance

The voltage at node 3 is given by

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2𝑅 2𝑅
−𝑉𝑅 −𝑉𝑅
𝑉3 = 3 = 3 = −𝑉𝑅
2𝑅 8𝑅 4
2𝑅 +
3 3

Fig.8
Fig,8 is a inverting amplifier and its output voltage is given by

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Performance parameters of ADC

The various performance parameters of ADC are:
1. Resolution
2. Accuracy
3. Monotonicity
4. Conversion time
5. Settling time

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6. Stability
1. Resolution:
Resolution is defined in two ways
i) Resolution is the number of different analog output values that can be
provided by DAC. For an n-bit ADC,
𝐑𝐞𝐬𝐨𝐥𝐮𝐭𝐢𝐨𝐧 = 𝟐𝐧
ii) Resolution is also defined as the smallest change in the analog voltage
it can detect ,which is also known as step size of the DAC . For an n
bit DAC resolution is calculated by the formula;
Resolution = (Range /(2^n -1)) .
2. Accuracy: is the comparison of actual output voltage with the expected
output. It is expressed in percentage. Ideally the accuracy of DAC is±1/2
LSB.
𝑅𝑎𝑛𝑔𝑒
𝐴𝑐𝑐𝑢𝑟𝑎𝑐𝑦 =
(2𝑛 − 1)2
3. Monotonicity : is a property of certain types of digital-to-analog converter
( DAC ) circuits. In a monotonic DAC, the analog output always increases
or remains constant as the digital input increases. If the analog output
decreases at any point during the input sequence, a DAC is said to be non-
monotonic.
4. Conversion time: It is the time required for conversion of analog signal
into its digital equivalent or vice-versa..
5. Settling time: This is the time required for the output of the DAC to settle
to within ±1/2 LSB of the final value for a given digital input.
6. Stability: The performance of the converter changes with temperature, age
and power supply variation. so all the relevant parameters such as offset,
gain, linearity error and monotonicity must be specified over the full
temperature and power supply ranges. These parameters represent the
stability of the converter.

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Problems:
1. What output voltage would be produced by a D/A converter
whose output range is 0 to 10V and whose input binary number
is
i) 10 (for a 2 bit DAC)
ii) 0110 (for a 4 bit DAC)
iii) 10111100 (for an 8 bit DAC)

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2. Calculate the values of LSB,MSB and full scale output for an 8-bit DAC for
the 0 to 1oV range.

Solution:

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3. An 8-bit DAC has an output voltage range of (0-2.55) V. Define its resolution
in two ways.
Solution:

4. The digital input for a 4-bit DAC is 0110.Calculate its final output
voltage, Given VOFS=15V.
Solution:

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5. An 8-bit DAC has resolution of 20mV/LSB. Find VOFS and V0 if the input is
(10000000)2
Solution:

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6. Find out step size and analog output for a 4-bit R-2R ladder DAC when
input is 1000 and 1111.Assume Vref= +5V.
Solution:
𝑉𝑟𝑒𝑓 5
𝑅𝑒𝑠𝑜𝑙𝑢𝑡𝑖𝑜𝑛 = = = 0.3125
24 16

i) D=(1000)2 =8
VO=Resolution * D=0.3125*8=2.5V
ii) D=(1111)2 =15
VO=Resolution * D=0.3125*15=4.6875V
7. A 12 bit DAC has a step size of 8mV. Determine the full scale output
voltage. Also find the output voltage for the input 010101101101
Solution:

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Analog to digital Converters(ADC)

Fig.9 Functional Diagram of ADC

Fig.9 shows the block schematic of ADC.It accepts an analog input signal V a
and produces an output binary word d1,d2,………………..,dn.

Where d1 is the Most Significant bit(MSB) and dn is Least Significant Bit (LSB)
An ADC has two additional control lines.
i. The start input to tell the ADC when to start the conversion.
ii. The EOC(End Of Conversion) output indicates when the conversion is
complete.
Classification of ADC
ADC are broadly classified into two groups depending upon their conversion
technique.
1. Direct type ADCs
2. Integrating type ADCs

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Direct types ADCs compare the given analog signal with the internally
generated equivalent signal. Some of the direct types ADCs are:
a) Flash type Converter
b) Counter type converter
c) Tracking or servo converter
d) Successive approximate type converter
Integrating type ADCs, the analog input signal is first converted into a linear
function of frequency or time and this is subsequently converted into a digital
code. Two most widely used Integrating type ADCs are
a) Charge balancing type ADCs
b) Dual slope ADCs

Successive approximate type converter

Fig.10 Block diagram of Successive approximate type converter

A successive approximation A to D converter is based on a very efficient code

searching strategy called binary search.The searching process is very fast. A n-
bit conversion is being completed in only n-clock periods.It consists of
a) DAC
b) Comparator
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c) Successive Approximate Register (SAR)

The external clock input sets the internal timing parameters. The SOC
signal starts the process of conversion and the activated EOC signal
announces the end of conversion process.
Operation:
The SOC signal initiates the process of search. SAR sets the MSB d1=1,
as soon as start signal arrives and all other bits are set to zero. For an 8-bit
converter, the initial setting would be 10000000.
The output Va of the DAC for this trial code is compared with the analog
input Vi. If the analog input Vi is greater than DAC output Va (i.e Vi >
Va), it implies the trial code 10000000 is less than the correct digital
representation of Vi. The MSB d1 is left at 1 and the next lower significant
bit is set at 1 and the process is repeated.
On the other hand,If the analog input Vi is less than DAC output Va (i.e Vi
< Va), it implies the trial code 10000000 is greater than the correct digital
representation of Vi. In such a case,the MSB d1 is reset at 1 and the next
lower significant bit is set at 1 and the process is repeated.(i.e 01000000).
The above process of comparison is repeated for all subsequent bits, one
at a time, until all bit positions have been tested.
The comparator changes the state whenever the DAC output crosses Vi
and this activates the EOC commands.
The SAR output after comparing all 8-bits 10110010=digital
representation of analog input.
In practice, an additional pulse is needed to load the output register and to
reinitialize the circuit.
The time required for one conversion from analog to digital depend on
both the clock period ‘T’ and the number of bits ‘n’.
Tc=T(n+1)
Where Tc is the conversion time.
Dept. of EEE, BNMIT Page 28
 Op-Amp and Linear ICs 18EE46

Advantages of Successive Approximation ADC

 Speed is high compared to counter type ADC.
 Good ratio of speed to power.
 Compact design compared to Flash Type and it is inexpensive.
Disadvantages of Successive Approximation ADC
 Cost is high because of SAR
 Complexity in design.
Applications
The SAR ADC will used widely data acquisition techniques at the sampling
rates higher than 10KHz

Ramp type ADC

• The Ramp type ADC is the basic type of ADC, which is also known as
staircase approximation ADC, or a counter type ADC. The circuit
diagram of ramp type ADC is shown in fig.10. The circuit diagram can be
built with N-bit counter, digital to analog converter, and op-amp
comparator.

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 Op-Amp and Linear ICs 18EE46

Fig.10 Block diagram of Ramp type ADC

• The N-bit counter produces an n-bit digital o/p which is given as an i/p to
the digital to analog circuit (DAC). This produces a ramp wave. The
analog output equivalent to the digital i/p from DAC is compared with the
i/p analog voltage with the help of an op-amp comparator. This
comparator Circuit evaluates the two voltages and if the produced DAC
voltage is low, it gives a high Reset pulse to the N-bit counter as to
increment the counter.
• The similar procedure will be continued until the output of the DAC
equals to the i/p analog voltage then it produces a low reset pulse to clear
the counter as well as to latch the data. In this way the analogue input is
converted to binary numbers.
• The block diagram in Fig.10 shows a 4 bit ADC. 8, 12 and 16 bit
converters are more common.
• For each sampling interval, the output of DAC tracks a rampway so that it
is named as a Digital ramp kind ADC. And this ramp seems like
staircases for each sampling moment, so that it is also named as a
staircase approximation kind ADC.

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 Op-Amp and Linear ICs 18EE46

Fig.11 Ramp type ADC

• Counter Type ADC Conversion Time: The ADC conversion time is the
time taken by the process to change the input sampled analog signal to a
digital value. Here the most conversions of high i/p voltage for an N-bit
ADC is the CLK pulses necessary to the counter to calculate its
maximum count value. So The Counter or ramp type ADC conversion
can be done by this formula, that is = (2N-1) T.
Where ‘T’ is the time period of the CLK pulse.
If N=3 bits, then the Tmax = 7T.

Counter type ADC Advantages

• Counter type ADC is very simple to understand and also to operate.

• Counter type ADC design is less complex, so the cost is also less
Counter type ADC Disadvantages

• Speed is less, since each time the counter has to begin from ZERO.
• There may be conflicts if the next i/p is sampled before completion of one
process.

Dept. of EEE, BNMIT Page 31

 Op-Amp and Linear ICs 18EE46

Dual Slope ADC

Dual slope ADC is an integrating type D to A converter. Its accuracy is quite
high, even though the speed of operation is quite slow.

In dual slope ADC, the analog input voltage and a reference input voltage are
both converted into time periods by means of an integrator and are then
measured by means of a counter.

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 Op-Amp and Linear ICs 18EE46

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 Op-Amp and Linear ICs 18EE46

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 Op-Amp and Linear ICs 18EE46

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 Op-Amp and Linear ICs 18EE46

Dept. of EEE, BNMIT Page 36

 Module-5

Phase Locked Loop (PLL): Basic PLL, components,

performance factors.
Timer: Internal architecture of 555 timer, Mono
stable multivibrators and applications.
 555 Timer IC
• Timers are those circuits, which provide periodic signals to a
digital system which change the state of that system. In other
words, those circuits, which work on the base of multivibrator
changes or a device, which can be used as multivibrator is
called Timer.
• The 555 timer IC is an integrated circuit (chip) used in a variety
of timer, delay, pulse generation, and oscillator applications
• The 555 timer IC is an integral part of electronics projects. Be it
a simple project involving a single 8-bit micro-controller and
some peripherals or a complex one involving system on chips
(SoCs), 555 timer working is involved. These provide time
delays, as an oscillator and as a flip-flop element among other
applications.
 555 Timer IC
• Introduced in 1971 by the American company Signetics,
the 555 is still in widespread use due to its low price,
ease of use and stability. It is made by many companies
in the original bipolar and low-power CMOS types. As
of 2003, it was estimated that 1 billion units were
manufactured every year. The 555 is the most popular
integrated circuit ever manufactured
• Depending on the manufacturer, the standard 555 timer
package includes 25 transistors, 2 diodes and 15 resistors
on a silicon chip installed in an 8-pin mini dual-in-line
package (DIP-8). Variants consist of combining multiple
chips on one board.
 555 Timer IC
Features of 555 Timer IC
• There are two types of 555 timer based on its
nomenclature – NE 555 Timer and SE 555 Timer. While
NE 555 timer can be used in the temperature range
from 0 to 70°C, the SE 555 Timer can be used in the
temperature range from -55°C to 125°C and has a
temperature stability of 0.005% per °C.
• it can be operated of different power supplies ranging
from 5 Volts to 18 Volts.
• It can be used either as a pulse generator or
an oscillator by operating it in different modes.
• The name 555 comes from the fact that it contains
three 5 Kilo-Ohm resistors in series to form the voltage
divider pattern.
 555 Timer IC
Features of 555 Timer IC
• It can drive both Transistor-Transistor Logic (TTL)
due to its high output current and CMOS logic
circuits.
• It has high output current and adjustable duty cycle.
• 555 timer can be operated in
both astable and monostable modes.
• The output of 555 timer can source or absorb current
up to 200mA sinking or sourcing current to the load.

• 555 timer is available as an 8-Pin Dual in

Line Package (DIP), 8-Pin Metal Can or 14-Pin Dual
in Line Package (DIP).
 555 Timer IC
Specifications
These specifications apply to the bipolar NE555. Other 555 timers can have
different specifications depending on the grade (industrial, military, medical,
etc.). These values should be considered "ball park" values; the current
official datasheet from the exact manufacturer of each chip should be
consulted instead for parameter limitation recommendations.
 555 Timer IC
Applications of 555 Timer
555 timer is most important integrated circuit (chip) used widely
in digital electronics. Some common uses and application of 555
timer IC are as follows:
• PWM (Pulse Width Modulation) & PPM (Pulse Position
Modulation)
• Duty Cycle Oscillator
• Lamp Dimmer
• To provide Accurate time delays
• As a flip-flop element
• Digital logic probes
• Analog frequency meters
• Quad Timer applications
• Pulse, Waveform, and square wave generation
• Stepped tone & tone burst generator & linear ramp generation
 555 Timer IC
Applications of 555 Timer
• Tachometers & temperature measurement
• It can be used as monostable multivibrator and astable multivibrator
• DC to DC Converters
• DC Voltage Regulators
• Voltage to Frequency Converter
• Frequency Divider
• Schmitt trigger
• Cable tester
• Pulse detector
• Wiper speed control
• Timer Switch
• Time delay generation, precision timing and sequential timing
• The 555 Timer IC are widely used in most of interesting electronic
circuits and project like Traffic Light Circuit using 555 Timer, LED
Flashing circuits, police siren, LED dice, Music Box, Metal
detector, Joystick and game paddles, & low cost line receiver, Clap
switch activated circuit and lots of other projects and circuits designs.
 555 Timer IC

The 555 Timer IC combines the following

elements :
• A relaxation oscillator
• RS flip flop
• Two comparators
• Discharge transistor
 The figure shows the part of the
RS Flip Flop Circuit basic RS flip flop circuit. It used a
pair of cross coupled Transistors.
Each Collector Drives the base of
opposite transistor thorough a
resistance RB. In such a Circuit, One
transistor Operates in saturation
while the other in cut off region.
This if the transistor Q2 is in
saturation then its collector voltage
is zero. This voltage is the base
drive of transistor Q1. So there is
no base drive for Q1 and it goes
into cut off. Thus its collector
voltage is approximately +VCC. This
drives the base of Q2 which
ensures that the Q2 operates in
saturation region.
RS Flip Flop Circuit
• If transistor Q2 goes into cut off, its collector voltage
approaches to +VCC which drives the transistor Q1 into
saturation. This makes collector voltage of Q1 almost zero
which keeps the transistor Q2 in cut off. So all the time,
circuit ensures that one transistor operates in saturation
and other in cut off.
• The two outputs Q and are taken from two collectors.
Depending upon the transistor operation, the output value
gets decided.
• This basic circuit along with some additional components
gives us a popular RS flip flop circuit. It has two inputs
set (S) and reset (R). With the help of these inputs, the
output Q can be made high or low. Depending on Q,
complementary will be the value of output Q i.e. low or
high.
The Fig. shows the symbol of RS flip flop circuit. When input set
(S) is high, the output Q is high and Q is low. The high reset (R)
input resets the output Q to low. The output Q remains in its state
of high or low unless and until it is triggered externally into the
opposite state.
Basic Timer Circuit:
 Basic Timer Circuit:
The Fig. shows the Basic Timer Circuit, which uses R S Flip Flop
Circuit along with some other elements.

To understand the operation, consider that the output Q is high.

This drives the base of Q1 and as it is high it drives Q1 into
saturation. It makes the capacitor voltage zero and as other end of
capacitor is grounded, the capacitor is shorted. In this condition it
can not be charged.
The circuit uses a comparator. The noninverting input of
comparator is called threshold voltage. While its inverting input is
called control voltage. The R1 and R2 forms a potential divider
which maintains control voltage constant at +10V. As Q is high and
transistor Q1 is in saturation, the threshold voltage is zero.
 Basic Timer Circuit:

If high voltage is applied to the reset (R) input of flip-flop

then it resets R-S flip-flop and output Q goes low. This
drives the transistor Q1 in cut off. Now the capacitor is free
to charge and starts charging through resistance R. The
threshold voltage thus starts increasing. When it becomes
just greater than +10V which is the control voltage, the
comparator output goes high. This high signal is driving
the set (S) input of R-S flip flop. This changes the state of
output Q back to high. This drives transistor Q1 into
saturation which quickly discharges the capacitor C.
 Waveforms of Basic Timing Circuit:
The Fig. shows the waveforms of
threshold voltage and output voltage
Vout. The charging of capacitor is
exponential hence the threshold voltage
is also exponential in nature. When Q
goes low,the becomes high and
positive going pulse appears at Vout.
Similarly when capacitor voltages
increases more than the control voltage,
Q becomes high and becomes low.
This brings Vout to zero instantly. Thus a
rectangular output gets produced.
It can be observed that output remains high for the time which is
required by the capacitor to charge upto control Voltage, through R.
Thus by varying R or C, the output pulse width can be varied. This is
the working principle of 555 Timer IC.
 IC 555 Pin Diagram and IC 555 Timer Block
Diagram:
The Fig. (a) and (b) show the IC 555 Pin Diagram and the IC 555
Timer Block Diagram. This is 8 pin IC timer.
IC 555 Pin Diagram and IC 555 Timer
Block Diagram:
Pin Function of 555 Timer IC:
The pin numbers of Timer IC 555 and their functions are
discussed below :
• Pin 1 : Ground
All the voltages are measured with respect to this terminal.
• Pin 2 : Trigger
The 555 Timer IC uses two comparators. The voltage divider
consists of three equal resistances. Due to voltage divider, the
voltage of noninverting terminal of comparator 2 is fixed at
VCC/3. The inverting input of comparator 2 which is compared
with VCC/3, is nothing but trigger input brought out as pin
number 2. When the trigger input is slightly less than VCC/3
the comparator 2 output goes high. This output is given to
reset input of R-S flip-flop. So high output of comparator 2
resets the flip-flop.
• Pin 3 : Output
The complementary signal output (Q) of the flip-
flop goes to pin 3 which is the output. The load
can be connected in two ways. One between pin 3
and ground while other between pin 3 and pin 8.
• Pin 4 : Reset
This is an interrupt to the timing device. When
pin 4 is grounded, it stops the working of device
and makes it off. Thus, pin 4 provides on/off
feature to the 555 Timer IC. This reset input
overrides all other functions within the timer
when it is momentarily grounded.
Pin 5 : Control Voltage Input
• In most of the applications, external control
voltage input is not used. This pin is nothing but
the inverting input terminal of comparator 1. The
voltage divider holds the voltage of this input at
2/3 VCC. This is reference level for comparator 1
with which threshold is compared. If reference
level required is other than 2/3 VCC for comparator
1 then external input is to be given to pin 5.
• If external input applied to pin 5 is alternating then
the reference level for comparator 1 keeps on
changing above and below 2/3 VCC. Due to this, the
variable pulse width output is possible:, This is
called pulse width modulation, which is possible
due to pin 5.
Pin 6 : Threshold
This is the noninverting input terminal of comparator 1. The
external voltage is applied to this pin 6. When this voltage is more
than 2/3 VCC, the comparator 1 output goes high. This is given to
the set input of R-S flip-flop. Thus high output of comparator 1 sets
the flip-flop. This makes Q of flip-flop high and Q low. Thus the
output of 555 Timer IC at pin 3 goes low.
Remember that output at pin 3 is which is complementary output
of flip-flop. In short,
Pin 7 : Discharge
This pin is connected to the collector of the discharge
transistor Qd. When the output is high then Q is low and
transistor Qd is off. It acts as an open circuit to the
external capacitor C to be connected across it, so
capacitor C can charge as described earlier. When output
is low, Q is high which drives the base of Qd high, driving
transistor Qd in saturation. It acts as short circuit,
shorting the external capacitor C to be connected across
it.
Pin 8 : Supply +VCC
The 555 Timer IC can work with any supply voltage
between 4.5 V and 16 V.
Connecting Load to IC 555:
The output of 555 is used
to drive load (controlling
devices) such as transistors
and relays. There are two
ways of connecting load to
output terminal : either
between output terminal
(pin 3) and ground (pin 1)
or between output terminal
(pin 3) and supply voltage
(pin 8) as shown in Fig.
Normally output is low. Thus, load current flows
through the load connected between VCC and output
terminal. The load connected in this way is called
normally ON LOAD and load current is called
the sink current. However, the current through the
grounded load is zero when the output is low. Thus,
the load connected between output terminal and
ground is called normally OFF LOAD. On the other
hand, when the output is high, the current through
the load connected between VCC and output terminal
is zero. However, the output terminal supplies current
to the normally off load. This current is called
the source current. In 555 timer maximum value
of sink or source current is 200 mA.
 Monostable Multivibrator Using IC
555:
• The IC 555 timer can be operated as a
Monostable Multivibrator Using IC 555 by
connecting an external resistor and a capacitor as
shown in the Fig.
• The circuit has only one stable state. When
trigger is applied, it produces a pulse at the
output and returns back to its stable state. The
duration of the pulse depends on the values of R
and C. As it has only one stable state, it is called
one shot multivibrator.
Operation
The flip-flop is initially set i.e. Q is high. This drives the transistor
Qd in saturation. The capacitor discharges completely and voltage
across it is nearly zero. the output at pin 3 is low.
When a trigger input, a low going pulse is applied, then circuit state
remains unchanged till trigger voltage is greater than 1/3 Vcc. When
it becomes less than 1/3 Vcc, then comparator 2 output goes high.
This resets the flip-flop so Q goes low and goes high. Low Q
makes the transistor Qd off. Hence capacitor starts charging through
resistance R, as shown by dark arrows in the Fig
The voltage across capacitor increases exponentially. This voltage is
nothing but the threshold voltage at pin 6. When this voltage
becomes more than 2/3 Vcc , then comparator 1 output goes high.
This sets the flip-flop i.e. Q becomes high and low. This high Q
drives the transistor Qd in saturation. Thus capacitor C quickly
discharges through Qd as shown by dotted arrows in the Fig.
So it can be noted that Vout at pin 3 is low at start, when trigger is
less than 1/3 Vcc it becomes high and when threshold is greater than
2/3 Vcc again becomes low, till next trigger pulse occurs. So a
rectangular wave is produced at the output. The pulse width of this
rectangular pulse is controlled by the charging time of capacitor.
This depends on the time constant RC. Thus RC controls the pulse
width. The waveforms are shown in the Fig.
Derivation of Pulse Width:

Thus, we can say that voltage across capacitor will reach 2/3 Vcc in
approximately 1.1 times, time constant i.e. 1.1 RC
Thus the pulse width denoted as W is given by,
W = 1.1 RC
Schematic Diagram:
Generally a schematic diagram
of the Monostable Multivibrator
Using IC 555 circuits is shown
which does not include
comparators, flip-flop etc. It
only shows the external
components to be connected to
the 8 pins of Monostable
Multivibrator Using IC 555.
Thus, the schematic diagram of
Monostable Multivibrator Using
IC 555 is shown in the Fig.
The external components R and C are shown. To avoid accidental
reset, pin 4 is connected to pin 8 which is supply +Vcc. To have the
noise filtering of control voltage, the pin 5 is grounded through a
small capacitor of 0.01 μF.
Applications:
The various applications of monostable circuit are,
•Frequency divider
•Pulse width modulation
•Linear ramp generator
•Pulse position modulation
•Missing pulse detector
•Timer in relay
In the circuit shown in Fig. RA=10KΩ, the output pulse width
tp=10ms.Determine the value of C
Monostable Multivibrator application
• Frequency divider
• Pulse stretcher
Frequency divider
 Frequency divider
The monostable multivibrator can be used as frequency divider
by adjusting the length of the timing cycle tp with respect to
time period T of the trigger input signal applied to pin 2.To use
the monostable multivibrator as a divide-by-2 circuit, the
timing interval tp must be slightly larger than time period T of
the trigger input signal as shown in fig.
By the same concept, to use the monostable multivibrator as a
divide-by-3 circuit, the timing interval tp must be slightly
larger than twice time period T of the trigger input signal. And
so on.
The frequency divider application is possible because the
monostable multivibrator cannot be triggered during the timing
cycle.
In monostable multivibrator circuit is to be used
as a divide-by-2 network,frequency of the
input trigger signal is 2kHz.if c=0.01uf, what is
the value of RA
For a divide-2-circuit, tp should be slightly larger
than T. Let
tp=1.2T
Therefore tp=1.2/2kHz=0.6ms
RA =0.6 m/(1.1 x 0.01 u)=54.5kΩ
Pulse Stretcher
 Pulse Stretcher
The application makes use of the fact that the output pulse width
(timing interval) mono stable multivibrator is of longer duration
than the negative pulse width of the input trigger. As such, the
output pulse width of the monostable multivibrator can be
viewed as a stretched version of the narrow input pulse width,
hence the name pulse stretcher.
Narrow pulse width signals are not suitable for driving an LED
display as the LED may be flashing but not be visible to the eye
because its ON time is infinitesimally small compared to its off
time.The 555 pulse stretcher can be used to remedy this problem.
The above fig shows a basic monostable used as a pulse stretcher
with an LED indicator at the output. The LED will be on during the
timing interval of tp = 1.1 RAC which can be varied by varying the
the value of RA and/or C
Astable Multivibrator Using 555 Timer
Astable multivibrator is also called as Free Running
Multivibrator. It has no stable states and
continuously switches between the two states
without application of any external trigger. The IC
555 can be made to work as an astable
multivibrator with the addition of three external
components: two resistors (R1 and R2) and a
capacitor (C). The schematic of the IC 555 as an
astable multivibrator along with the three external
components is shown below.
Astable Multivibrator Using 555 Timer
• The pins 2 and 6 are connected and hence there is no need
for an external trigger pulse. It will self trigger and act as a
free running multivibrator. The rest of the connections are
as follows: pin 8 is connected to supply voltage (VCC). Pin
3 is the output terminal and hence the output is available at
this pin. Pin 4 is the external reset pin. A momentary low on
this pin will reset the timer. Hence when not in use, pin 4 is
usually tied to VCC.
• The control voltage applied at pin 5 will change the
threshold voltage level. But for normal use, pin 5 is
connected to ground via a capacitor (usually 0.01µF), so the
external noise from the terminal is filtered out. Pin 1 is
ground terminal. The timing circuit that determines the
width of the output pulse is made up of R1, R2 and C.
Operation
• The following schematic depicts the internal circuit of the
IC 555 operating in astable mode. The RC timing circuit
incorporates R1, R2 and C.
Initially, on power-up, the flip-flop is RESET (and hence the output of the
timer is low). As a result, the discharge transistor is driven to saturation (as
it is connected to Q’). The capacitor C of the timing circuit is connected at
Pin 7 of the IC 555 and will discharge through the transistor. The output of
the timer at this point is low. The voltage across the capacitor is nothing
but the trigger voltage. So while discharging, if the capacitor voltage
becomes less than 1/3 VCC, which is the reference voltage to trigger
comparator (comparator 2), the output of the comparator 2 will become
high. This will SET the flip-flop and hence the output of the timer at pin 3
goes to HIGH.
This high output will turn OFF the transistor. As a result, the capacitor C
starts charging through the resistors R1 and R2. Now, the capacitor
voltage is same as the threshold voltage (as pin 6 is connected to the
capacitor resistor junction). While charging, the capacitor voltage
increases exponentially towards VCC and the moment it crosses 2/3 VCC,
which is the reference voltage to threshold comparator (comparator 1), its
output becomes high.
As a result, the flip-flop is RESET. The output of the timer falls to LOW.
This low output will once again turn on the transistor which provides a
discharge path to the capacitor. Hence the capacitor C will discharge
through the resistor R2. And hence the cycle continues.
Thus, when the capacitor is charging, the voltage across the capacitor rises
exponentially and the output voltage at pin 3 is high. Similarly, when the
capacitor is discharging, the voltage across the capacitor falls exponentially
and the output voltage at pin 3 is low. The shape of the output waveform is a
train of rectangular pulses. The waveforms of capacitor voltage and the output
in the astable mode are shown below.

While charging, the capacitor

charges through the
resistors R1 and R2.
Therefore the charging time
constant is (R1 + R2) C as
the total resistance in the
charging path is R1 + R2.
While discharging, the
capacitor discharges through
the resistor R2 only. Hence
the discharge time constant
is R2C.
IC 565 PLL | Pin Diagram | Block Diagram:

IC 565 PLL is available in a 14 pin DIP package and 10 pin metal can package. Fig. 1 shows
14-pin package configuration for IC 565 and Fig. 2.shows the block diagram for IC 565.

IC 565 Pin Diagram:

Fig.1 Pin Diagram of IC 565

IC 565 PLL Block Diagram:

The block diagram of IC 565 PLL consists of phase detector, amplifier, low pass filter and
VCO. As shown in the block diagram the phase locked feedback loop is not internally
connected. Therefore, it is necessary to connect output of VCO (pin 4) to the phase comparator
input (pin 5), externally. In frequency multiplication applications a digital frequency divider is
inserted into the loop i.e. between pin 4 and pin 5.

Fig2. Block Diagram of IC 565

The centre frequency of the PLL is determined by the free-running frequency of the VCO and
it is given as,

where R1 and C1 are an external resistor and a capacitor connected to pins 8 and 9, respectively.
The values of R1 and C1 are adjusted such that the free running frequency will be at the centre
of the input frequency range. The value of R1 is restricted from 2kΩ to 20 kΩ but a capacitor
can have any value. A capacitor C2 connected between pin 7 and the positive supply (pin 10)
forms a first-order low pass filter with an internal resistance of 3.6 kΩ. The value of filter
capacitor C2 should be large enough to eliminate possible oscillations in the VCO voltage.

The lock range and capture range for IC 565 PLL are given by the following equations:

where

and

where C2 is in farads.

From equation 2 we can notice that lock range increases with an increase in input voltage but
decreases with increase in supply voltage. The two inputs (pin 2 and pin 3) to the phase detector
allows direct coupling of an input signal, provided that there is no dc voltage difference
between the pins and, the dc resistances seen from pins 2 and 3 are equal. A reference voltage
at pin 6 is approximately equal to the dc voltage of the demodulated output at pin 7. This
reference voltage may be used as comparator input in applications like frequency shift keying.

Frequency Multiplier using PLL 565:

Fig. 3 shows the block diagram for a frequency multiplier using PLL 565.
 Fig3. Block diagram of frequency multiplier

Here, a divide by N network is inserted between the VCO output (pin 4) and the phase
comparator input (pin 5). Since the output of the divider is locked to the input frequency fi, the
VCO is actually running at a multiple of the input frequency. Therefore, in the locked state, the
VCO output frequency fo is given by,

By selecting proper divider by N network, we can obtain desired multiplication. For

example, to obtain output frequency fo = 6 fi ,a divide by N should be equal to 6.

Fig.4 Typical connection for frequency multiplier

The Fig. 4 shows LM 565 IC used as a frequency multiplier circuit. The IC 7490 is a 4 bit binary
counter. It is configured as a divide by 10 circuit.

Block Diagram of Frequency Synthesizer using PLL:

The Block Diagram of Frequency Synthesizer using PLL that can produce a precise series of
frequencies that are derived from a stable crystal controlled oscillator.

Fig. 3. Block Diagram of frequency synthesizer

The Fig. 3 shows the Frequency Synthesizer Block Diagram. It is similar to frequency
multiplier circuit except that divided by M network is added at the input of phase lock loop.

The frequency of the crystal-controlled oscillator is divided by an integer factor M by divider

network to produce a frequency fosc/M, where fosc is the frequency of the crystal controlled
oscillator.

The VCO frequency fVCO is similarly divided by factor N by divider network to give frequency
equal to fvco/N. When the PLL is locked in on the divided-down oscillator frequency, we will
have fosc/M = fvco/N, so that fvco=(N/M)fosc.

By adjusting divider counts to desired values large number of frequencies can be produced, all
derived from the crystal controlled oscillator.