Vig Sequential Circuits - Part | Complete Course on Digital Electronics for GATE Sanchit Jain + Lesson 12 » May 18, 2022Combinational Circuits O/p = f(i/p) BAA AR irae (9Combinational S When logic gates are connected together to produce a specified out put on certain specified combinations of input variables, with no memory involved, then the resulting circuit is called a combinational circuit. Output depends only on present input. O/p = f(i/p), combinational circuit performs an operation that can be specified logically by a set of Boolean function. A combinational circuit may have n-binary inputs and m-binary outputs.Application, Practical computer circuits normally contain combinational and sequential logic. For e.g. the part of ALU, that does mathematical calculations is constructed using combinational logic.* Other circuits such as half adders, full adders, half subtractors, full subtractors, multiplexers, demultiplexers, encoders and decoders are also made by using combinational logic. A TB ote? ‘sum : D- =D B s a+ re “ > 8 J con / AA c felineneDesign procedure: - 1. Analyse the given problem and identify the number of i/p and o/p variables. 2. Write the truth table based on the specification of the problem. 3. Convert the truth table in minimized Boolean expression using k-map. 4. Draw the logic circuit for the above obtained output expression.BreakAdder An adder is a digital combinational circuit that performs addition of numbers. Are used in the arithmetic logic units or ALU. They are also utilized in other parts of the processor, where they are used to calculate addresses, table indices, increment and decrement operators, and similar operations. Although adders can be constructed for many number representations, such as binary-coded decimal or excess-3, the most common adders operate on binary numbers. In cases where two's complement or ones' complement is being used to represent negative numbers, it is trivial to modify an adder into an adder—subtractor.* Basics of addition: - (A),+ (B),=? BHalf adder + The simplest form of addition is addition of two binary digits, consists of four possible 1 1 O 0O +1 +00 6+10 (+0 * The first three operations produce a sum of two digits, but when both augend and addend bits are equal to 1, the binary sum consists of two digits. The higher significant bit of this result is called a carry.It is a combinational circuit, which perform the arithmetic addition of two one-bit binary numbers is referred to as an half-adder. So, in half adder inputs are adds two single binary bits A and B, and two outputs, sum (5) and carry (C). INPUTS OUTPUTS. Carry | Sum A 1 ‘sun | Heder) rlHlolol> rlolHloloaD Cost of implementation a half adder is one EX-OR gate and one AND gate. A half adder has only two inputs and there is no provision to add a carry coming from the lower order bits when multi bit number addition is performed. For this reason, we have designed a full adder.QA half-adder is also known as: (NET-DEC-2005) (A) AND Circuit (B) NAND Circuit (C) NOR Circuit (D) EX-OR CircuitBreakFull adder . A full adder is a combinational logic circuit that performs the arithmetic sum of three input bits. .. Where A,, B, are the n*” order bits of the number A and B respectively and C, is the carry generated from the addition of (n-1)*" order bits. It consists of three input bits, denoted by A (First operand), B (Second operand), C,,, (Represents carry from the previous lower significant position).ooo | + oon | + ono | + ona | + “HOO | + + + aa] | ++ Two output bits are same as of half adder, which is Sum and Carry,... * When the augend and addend number contain more significant digits, the carry obtained from the addition of two bits is added to the next higher order pair of significant bits. INPUTS OUTPUTS " an B | Cig | Cour | Sum ~ full-Adder Circuit rm B Carry Out Carry In wlelelnlolololol> wlelololHlHlolo wlolHlolHlolHloSum — A Gs Foo & a Lt < : Gi a ° < e e < e\(e\(2\(¢ gR\l 2] 2 |) 2 —|Coe prscor C#}*—1Cm* pader C#-— SUM. SUM, ‘SUM, SUM So Se S: So* There are some scope of improvement in adder like Carry propagation delay Look ahead Carry Generator ser | Z* Can adder be modified to work as subtractor * Adder/subtractor or ripple adder Carry o carry cQAhait adder isimplemented with XOR-and-AND gates. A fulladderisimplemented-with-two-half adders androne OR gate. The-propagation delay of an XOR gate is twice that of arrAND/OR gate. The propagation of an AND/OR gate is 1.2 microseconds. A adder is implemented by using full The total propagation time of thig4-bitbinary adder in microseconds i is (GATE-2015) (2 Marl OO _ v 7 ao 1 . ie BM 6 aw VeBreakFour-bit ripple adder/subtractor The subtraction A - B can be done by taking the 2’s complement of B and adding it to A. The 2’s complement can be obtained by taking the 1’s complement and adding 1 to the least significant pair of bits. The 1's complement can be implemented with inverters, and a 1 can be added to the sum through the input carry.* The circuit for subtracting A - B consists of an adder with inverters placed between each data input B and the corresponding input of the full adder. A3 B3 Ad Bo AY By Ao aiate ~al> a] be ws a. [be reler A B A B A B A B rataaie Cin | Co fl, Cink Co fi, Cin|+ Eh, Cin 7) wr sm om com om Ax CR) — a (Kae * a ane oh AurThe mode input M controls the operation. When M = 0, the circuit is an adder, and when M = 1, the circuit becomes a subtractor. When M =0, we have B @ 0 =B. The full adders receive the value of B, the input carry is 0, and the circuit performs A plus B. When M = 1, we have B @ 1=B’ and Cy= 1. The B inputs are all complemented and a 1 is added through the input carry. The circuit performs the operation A plus the 2’s complement of B. As Bs Az BAY BAB. Rw Re at © ea As] [ATS] PATS] PAT rasaer Cin BL Cinco Bt. Cink] co ft, CinQ Consider an eight-bit ripple-carry adder for computing the sum of A and B, where A and B are integers represented in 2’s complement form. If the decimal value of A is one, the decimal value of B that leads to the longest latency for the sum to stabilize is = (GATE-2016) (2 Marks) Po eae a A 2000 CoO ree VX OS Wor ax VQ Faroese foeQConsider the ALU shown below. y<— >| wd te , Dad =| be & eR, 1 50 If the operands are in 2's complement representation, which of the following operations can be performed by suitably setting the control lines K and C, only (+ and — denote addition and subtraction respectively)? (GATE-2007) (2 Marks) or (A)A+8; and AB, but nota + 5X. (B)A+B,anfA+1)but not A vo 2 (C) A+B, but not A-B, or AHL (D) A+B, and A-B, and K& aon O xX arS~ GsoBreakLook ahead carry adder In parallel adder all bits of augend and addend are available for computation initially, but sum and carry outputs of any stage cannot be produced until the input carry occurs. This leads to delay in the addition process known as carry propagation delay. In any combinational circuit, the signal must propagate through the gates before the correct output sum is available in the output terminals. The total propagation time is equal to the propagation delay of atypical gate * times the number of gate levels i uit: Ke HID MsB LsB As B BY As B : | . a rs ost Gs sa <4 e[# {Cos wader Sel “| SUM a* The carry propagation time is an important attribute of the adder because it limits the speed with which two numbers are added. The solution to delay is to increase the complexity of the equipment in such a way that the carry delay time is reduced. To solve this problem most widely used technique employs the principle of ‘look ahead carry’. This method utilizes logic gates to look at the lower order bits of the augend and addend to see if a higher order carry is to be generated. It uses two functions carry generate G, and carry propagate P, A(A3 Ay Ar Ao) B(B; B, B, By)Cai = G+ PGG is called a carry generate, and it produces a carry of 1 when both A, and B, are 1, regardless of the input carry C, P is called a carry propagate, because it determines whether a carry into stage i will propagate into stage i + 1. ‘We now write the Boolean functions for the carry outputs of each stage and substitute the value of each C, from the previous equations:Gs called a carry generate, and it produces a carry of 1 when both A, and 8, are 1, regardless of the input carry C, P is called a carry propagate, because it determines whether a carry into stage i will propagate into stage i+ 1. We now write the Boolean functions for the carry outputs of each stage and substitute the value of each C, from the previous equations: Cy = G+ Py Cy C, = G, + PyGo+ PyPo Co C,=G, +P,G, + P,P,Gy+ P,P; Py CoSince the Boolean function for each output carry is expressed in sum-of-products form. Each function can be implemented with one level of AND gates followed by an OR gate (or by a two- level NAND). Day, ' G=0 aly oe ut Cy = Gy + Po Cy ; \ 66,2796 2 Cy= 6, +P,G, + P.PiGp+ PP, PoCo Cy = G, + GPs + Gy.P).P3 + Go.P-P,.Ps + CoPo.Py-P2P,+ All output carries are generated after a delay through two levels of gates. Thus, outputs S, through S, have equal propagation delay times.+ All output carries are generated after a delay through two levels of gates. Thus, outputs S, through S; have equal propagation delay times.‘Wunacademy £3 Asked by Nitishsing Maine bna diya sir‘Wunacademy 4+ Asked by Vibhor Please help me with this doubtQ Consider a carry lookahead adder for adding two n-bit integers, t “most two. The time to perform addition using this adder E (a) 0(1) (B) O(Log (n)) (0) 010)Qin a look-ahead carry generator, the carry generates function G, and the carry propagate function P| for inputs A, ‘and Bare given by (GATE-2007) (2 Marks) P.=A@BandG,=AB, : The expressions for the sum bit Si and the carry bit C,,, of the look-ahead carry adder are given by: $;=P,® Gand + PC, , where CQ is the input carry. Consider a two-level logic implementation of the look-ahead carry generator. Assume that all P, and G, are available or the carry generator circuit and that the AND and OR gates can have any number of inputs. The number of AND implement the look-ahead carry generator for a 4-bit adder with S,, S,, S,, Sand C, as (C)6,4 {D) 10, 5QGiven two three-bit numbers a,a,a, and b,b,b, and c, the carry in, the function that represents the carry generate function when these two numbers are added is (GATE-2006) (2 Marks) (A) 4b, +2.40,+294b +2,400,+a0d +a4b0, +adod, (8) ad +44 +aqh0 +aqbd +aqd +aqnh +aabn, (C) a+b, +(a, @b)[a,+d +a, @)(a +h) (0) ab, +80 +a.aab +290, +abb+aabb +abbb,-bit carry lookahead adder, which adds two 4-bit numbers, is designed using AND, OR, NOT, NAND, NOR gates only. Assuming that all the inputs are available in both complemented and uncomplemented forms and the delay of each gate is one-time unit, what is the overall propagation delay of the adder? Assume that the carry network has been implemented using ‘two-level AND-OR logic. (GATE-2004) (2 Marks) (A) 4 time units (B) 6 time units (C) 10 time units (D) 12 time unitsMultiplexer tor) * Multiplexer are special and one of the most widely used combinational circuits. * Main requirement is out of many inputs we have to select one for e.g. telephone or train leaving the station. So multiplexer do not perform any logical operation or comparison, it just acts as a switch or relay.vesrwe Eee iultiple rs . =~ Multip Laptop Sound Card Digital Satelite Cable TV i _—— casey — 4 = Multi Sources Multiplexer as Selector Single Destination ‘Surround Sound System SatetteA multiplexer is a combinational circuit that selects binary information from one of many input lines and directs it to a single output line. ‘A multiplexer is also called a data selector, since it selects one of many inputs and steers the binary information to the output line. ‘The selection of a particular input line is controlled bya set of selection lines. ‘There are 2” input lines and n selection lines whose bit combinations determine which input is to be selected. No of Input line =< 2"Note: * Can never have two i/p connected to out at any time Application * Parallel data to serial data conversion * Used as data selector, as the output of a multiplexer is directed from one of various inputs * Used in implementation of Boolean functions + Used in communication systems, Computer Memory, Telephone Network, Transmission from the Computer System of a Satelliteorcreray —Ds.c86; oe Aaabbae Aaabaae Aaabaae aaaeaae O7DsosoLos020100 ——«CTEBCSCECScacico —«BTBEBSBLaDEzBIB) —ATABASMASAZATAD Roped gata Roger egiterAreBreakA two-to-one-line multiplexer * This multiplexer acts like an electronic switch that selects one of two sources. * The circuit has two data input lines, one output line, and one selection line S.A two-to-one-line multiplexer * When S = 0, the upper AND gate is enabled and |, has a path to the output. * When S = 1, the lower AND gate is enabled and |, has a path to the output. MUX 1 , s V 0 I $ 1 l, _L) (6) Block diagram w : Input | Output | * [5 [- (@) Lopic diagram Characteristic equation: Y = Sq’ Ip + So |,QA multiplexer is a logic circuit that (NET-JUNE-2011) (A) accepts one input and gives several outputs (B) accepts many inputs and gives many output (C) accepts many inputs and gives one output (D) accepts one input and gives one outputBreakCase study of 4 to 1 * The circuit has four data input lines |,, |,, 12, |; one output line Y, and two selection line Sp and Sy.Case study of 4 to1 * Each of the four inputs, Ip through I,, is applied to one input of an AND gate. * Selection lines S, and S, are decoded to select a particular AND gate. + The outputs of the AND gates are applied to a single OR gate that provides the one-line output. Input Output — . Sy So Y 0 0 ly tT 0 1 h - 1 oO 1, 1 1 is Characteristic equation Y= E [(S's S’o bo) + (S's So ba) + (Si S'o 12) + (Si So |3)] (>Q.46 Which one of the following circuits implements the Boolean function given below? (GATE- 2021) flx, y, 2) = my + m, + mz + m, + Mm, + Me, where m, is the i minterm. ° 1 agxt 2 Mux 7 1{3 5,» ye ye 1fo +o io |, ras |, © v—f2 mm [~~ (@ x—j2 Mx x—|35, 5 x35, 5 Tt '"Q Consider a 4-to-1 multiplexer with two select lines S, and S,, given below The minimal sum-of-products form of the Boolean expression for the output F of the multiplexer is (Gate-CS-2014-Set-1) (2 Marks) (A) P’Q + QR’ + PQ’R (B) P’Q + P’QR’ + PQR’ + PQ’R (C) P’QR + P’QR’ + QR’ + POR (D) par’ A-to-1 Multiplexer S,_SoQ Consider a 4-to-1 multiplexer with two select lines S, and S,, given below The minimal sum-of-products form of the Boolean expression for the output F of the multiplexer is (Gate-CS-2014-Set-1) (2 Marks) (A) PQ. + QR’ + PO'R (B) P’Q + P’QR’ + POR’ + PQ’R (C) P’QR + P’OR’ + QR’ + POR (D) par’ Y= [(S'p S’o Io) # (S's So ba) + (Si S’o Ia) + (Sy So Ia] A-to-1 Multiplexer S,_SoQ The Boolean expression for the output ‘f’ of the multiplexer shown below is (GATE-2010) (2 Marks) (A) (P BAGRY (8) PBAGR (c)(P+Q+R) (D)P+Q+R RAATQ The Boolean expression for the output ‘f’ of the multiplexer shown below is (GATE-2010) (2 Marks) (a) (P BAG® Ry (B)PBAGR (c) (P+Q+R)’ (D)P+Q+R i a : Lt ye tsps) 85) # 50) (50H @Q Consider the following multiplexor where |,, |,, |, |, are four data input lines selected by two address line combinations A,Ay = 00, 01, 10, 11 respectively and fis “the output of the multiplexor. EN is the enable input. (Gate-CS-2002) (2 Marks) The function f(x, y, z) implemented by the above circuit is : (A) xyz’ (B) xy +z (C)x+z (D) None of theseQ Consider the following multiplexor where I,, |,, |, |; are four data input lines selected by two address line combinations A,Ay = 00, 01, 10, 11 respectively and fis “the output of the multiplexor. EN is the enable input. (Gate-CS-2002) (2 Marks) The function f(x, y, 2) implemented by the above circuit is : (A) xyz’ (B) xy +z (c)x+z (D) None of these suoaie Y=E [(S'y S'9 Ig) + (S's So ba) + (Ss S’0 Ia) + (St So I3)]Q Consider the circuit in below figure. f implements (GATE-1996) (2 Marks) e 2 dior Lor © Mux 8 SS (A) (ABC)’ + A’BC’ + ABC AB (B)A+B+C ()\ABBOC (D) AB +BC+CAQ Consider the circuit in below figure. f implements (GATE-1996) (2 Marks) co—» (A) (ABC)’ + A’BC’ + ABC Y= [(S's S’o lo) + (S's So ba) + (St S’0 ba) + (S1 So I3)] (B)A+B+C (QADBOc (D) AB +BC+CAMany multiplexerQ Consider the two cascaded 2-to-1 multiplexers as shown in the figure. (GATE-2016) (2 Marks) R O— +0 2104 240-1 +x k—-1 MUX MUX t | P 2 The minimal sum of products form of the output X is (A) PO+POR (B) PQ+OR (C) PO+POR (D) OR+PORQ Consider the two cascaded 2-to-1 multiplexers as shown in the figure. (GATE-2016) (2 Marks) R Y=Sp Ip +S ly “x The minimal sum of products form of the output X is Y= So I + So I (A) PQ+POR (B) PQ+OR (C) PO+POR (D) OR+PORQ Consider the below circuit and find the output function f(x, y, z). (NET-JUNE-2012) Pup. eunca (A) x2! + xy +y’2 (B) x2’ + xy +2’ (C)xz+ xy +y'2’ (D) xz + xy’ +y'zQ Consider the below circuit and find the output function f(x, y, z). (NET-JUNE-2012) B Y=Sp lo+Solht fsbo eunca es Y= Spo’ Ip + Soh (a) x2! + xy +y’2 (B) x2’ + xy + yz’ (C)xz+xy+y'7’ (D) xz + xy’ + y'zQ The following circuit implements a two-input AND gate using two 2-1 multiplexers. (GATE- 2007) (1 Marks) What are the values of X;, X,, X3? (A) X,=b, X,=0, Xj=a (B) X,=b, X,=1, X,=b (C) X,=a, X,=b, Xj=1 (D) X,=a, X,=0, X3=b a F b X1 X2 X3Q The following circuit implements a two-input AND gate using two 2-1 multiplexers. (GATE- 2007) (1 Marks) What are the values of X,, X,, X3? (A) X,=b, X,=0, Xj=a (B) X,=b, X,=1, X,=b (C) X,=a, X,=b, Xj=1 (D) X,=a, X,=0, X3=b s a 7 © Y=S' lo + Sol: Y=Sp" Ip +So hy b X1 X2 X3Q Consider the circuit above. Which one of the following options correctly represents f (x, y, z)? (Gate-CS-2006) (2 Marks) (A) xz’+xy+y’z 9 (B) xz’ +xy+(yz)’ — (C)xz+xy+ (yz) (D) xz + xy’ + y’zQ Consider the circuit above. Which one of the following options correctly represents f (x, y, z)? (Gate-CS-2006) (2 Marks) (A) xz’ +xy+y’z (B) xz’ +xy+(yz)’ — (C)xz+xy+(yz)’ (D) xz + xy’ +y’z o]_ me Y= So Ip + So by ST 4 y Y= So" lo + So hyQ The circuit shown below implements a 2-input NOR gate using two 2-4 MUX (control signal 1 selects the upper input). What are the values of signals x, y and z? (GATE-2005) (2 Marks) (A) 1,0,8 (8) 1,0, (€)0,1,8 [3 c-A7B (0) 0,1, w>oTe 1 )o}a 1 1 0 aypalaBreakNOT GATEInputsAND GATE4 |_|. 3 3 2 Fit Be InpasOR GATEOR GATE Truth Table oO o 0 fz > Oulpul 7 0 0 1 1 1 o 1 f=1 z 1 1BreakMultiplexer Expansion (Implementation of Higher order MUX using lower order MUX) QHow many 1 MUX are required to implement 4 : 1 MUX ? Input Output BlRlolo Rlo|RloQHow many 4: 1 MUX using 16 : 1 MUX ?Q How many 4X1 Mux are required in order to construct 128X1?QHow many 8X1 Mux are required in order to construct 4096X1?Given: mX1 Target: nXx1 No of levels(K) log... No of Mux at it" level (x) | (n/m) Total Mux required TK xi =1 Maximum capacity m*X 1BreakDemultiplexer A demultiplexer (or DeMux) is a device that takes a single input line and routes it to one of several digital output lines. i ; ieee Yo A demultiplexer is also called a data distributor. oo It is conceptually same as Mux just with reverse logic. om es o————— 13* Ademultiplexer of 2" outputs has n select lines, which are used to select which output line to send the input.A DeMux is a combinational circuit, which is used in data communication Serial to parallel conversation Different input/output configuration demultiplexers are available in the form of single integrated circuits (ICs). Demultiplexers are mainly used in Boolean function generators and decoder circuits.1 to 2 DemultiplexerDetox 1 to 2 Demultiplexer So 0, 0% 0 0Break1 to 4 Demultiplexer1 to 4 Demultiplexer eee Se | 4 g-lolo olc|-|o o°c|o|- oc|ojo a) yic|olea co SS Litt ge 3 5BreakDemultiplexer Expansion (Implementation of Higher order DeMux using lower order DeMux) Q1: 2 DeMux are required to implement 1 : 4 DeMux ?Demultiplexer Expansion (Implementation of Higher order DeMux using lower order DeMux) Q1: 2 DeMux are required to implement 1 : 8 DeMux ?Ys ‘ie Yas Yaa Yas Yio Yo Ys ixs De-Multiplexer 1x2 De-Multiplexer Y Ye Ys Ys Ys Ye % Yo xs De-MultiplexerBreakDecoder A decoder is a combinational circuit that decodes binary information from n input lines to a maximum of 2° unique output lines. The decoders are called n -to- m -line decoders, where m < 2°. Their purpose is to generate the 2" (or fewer) minterms of n input variables. Each combination of inputs will assert a unique output. If the n -bit coded information has unused combinations, the decoder may have fewer than 2" outputs. { Os Twi——{ Detoden za eR LT \ l £ Ox, — TTDecoder * Decoders are also combinational circuits logically we can say a DeMux can be converted into a decoder by setting input line as enable line and selection line as input lines.Address Bus - A3 to Aro Data Bus CS = Chip Select1-to-2 Decoder1-to-2 Decoder 1 | 0, | O% o|o | 1 I 0So Sr DecadeBreak2-to-4 DecoderDecoclen qs SKY 2-to-4 Decoder rooofBreakQ Implementation of a full adder with a decoder From the truth table of the full adder, we obtain the functions for the combinational circuit in sum-of-minterms form: S(x, y, 2) = 5 (1, 2, 4, 7) C(x, y, 2) = 3 (3, 5, 6, 7) Opo Op1 ipo Op2 ipt 38 Op3 Ip2 Decoder Op4 Ops Op6 Op7Combinational Logic Implementation * Any combinational circuit with n inputs and m outputs can be implemented with an n -to-2" - line decoder and OR gates. * The procedure for implementing a combinational circuit by means of a decoder and OR gates requires that the Boolean function for the circuit be expressed as a sum of minterms. * Adecoder is then chosen that generates all the minterms of the input variables. The inputs to each OR gate are selected from the decoder outputs according to the list of minterms of each function.onan: SASH as x3 “os ear gnActive High Decoder:- When output is directly from AND gate, we get exact minterms then, it is called active high decoder. In the 2"¢ level here, we use OR-gate to find the function. Active Low Decoder:- In active low decoders, output will be from NAND gates, on the 2” level we again use NAND gate, as we know NAND-NAND implementation is SAME as AND-OR.Q What Boolean function does the circuit below realize? (GATE-2006) (2 Marks) (A) xz + x’2’ (B) xz’ + x’z (C) x’y’ + yz (D) xy + y’2’BreakDecoder ExpansionDecoder Expansion — It Gelato ie f ay LL _ __—-24T x] =h i ‘ Ort | | lQ6-to-64 from 2-to-4 ?Q/7-to-128 from 3-to-8 ?pXq floor(m/p) (n/qk") i=k vs i=1 (p Xk) X qkQ Two 3-to-8-line decoders with enable inputs connected to form a 4-to- 16-line decoder.BreakEncoder * Anencoder is a combinational circuit that encode binary information form one of a 2" input lines and encode it into N output lines, which represent N bit code for the input. * For simple encoders, it is assumed that only one input line is active at a time. * Encoder performs the inverse operation of a decoder.2-to-1 Encoder2-to-1 Encoder y Oo of = i— JoBreak4-to-2 Encoder4-to-2 Encoder Io 1 I L ol|olo* Oo = Ip'ly ‘(lp ® 13) * 0, = Ip‘ly‘(l, @ |3)BreakPriority Encoder In some practical cases more than one input can be high at a time, there we can not use simple encoder In a priority encoder more than one input can be high at a time. A priority encoder is an encoder circuit that includes the priority function. The operation of the priority encoder is such that if two or more inputs are equal to 1 at the same time, the input having the highest priority will take precedence. o = wi t a mady em. pFThey are often used to control interrupt requests by acting on the highest priority interrupt input. The priority encoders output corresponds to the currently active input which has the highest priority. So when an input with a higher priority is present, all other inputs with a lower priority will be ignored. QO = op . &~ fa. FfIp>1>1> ly1, >1,>1,> Ip = mo Op = ly + ly’ by’ | O,=1, +1;Q In the following truth table, V = 1 if and only if the input is valid. (GATE-2013) (2 Marks) What function does the truth table represent? (A) Priority encoder (B) Decoder Inputs Outputs: Do | Di | Dz | Ds | Xo | Xi | V o};}o;o;oO{tx|]x{o 1)/o/;o;o ;o]o0/1 X% 1,o0};o ];o]1 1 x | x«/[1/0/]1/0/1 xi x|x|T 1 1 1 (C) Multiplexer (D) DemultiplexerQ Match the terms in List - | with the options given in List - II: (NET-JULY-2018) List-1 list il (1) Decoder {(i)1 line to 2° ines (2) Multiplexer (ii) lines to 2" ines (3) De multiplexer {iii 2° lines to 4 line {iv) 2" lines to 2-1 lines