UNIT II

COMBINATIONAL CIRCUIT DESIGN

 UNIT II COMBINATIONAL CIRCUIT DESIGN
• Problem formulation and design of combinational circuits
• Code Converters
• Design of Half and Full Adders Half and Full Subtractors
• Binary Parallel Adder
• Carry look ahead Adder
• BCD Adder
• Magnitude Comparator
• Decoder, Encoder ,Priority Encoder.
• Multiplexer, Demultiplexer
• Digital trans-receiver
• 8 bit Arithmetic and logic unit
• Parity Generator/Checker
• Seven Segment display decoder
 COMΒΙΝΑΤΙΟΝAL LOGIC DESIGN

In the combinational logic circuit design process,

we must
• Define the Problem.
• Defines the input variables for representing all
conditions.
• Assign the output variables (be single output or multi-
outputs).
• Write the truth table to represent all combinations of
input and output variables.
 COMΒΙΝΑΤΙΟΝAL LOGIC DESIGN

In the combinational logic circuit design process, we must

• Build up the Boolean expressions in canonical sum of product
(SOP) or canonical product of sum (POS) form.
• The written Boolean expression may be or may not be
minimized form.
• Therefore the equations should be expressed in the minimum
SOP and POS form.
• Finally, implement the logic expressions by electronics circuits
namely AND, NAND, OR, NOR and NOT gates.
 COMΒΙΝΑΤΙΟΝAL LOGIC DESIGN
• Fig. shows the block diagram of a typical combinational logic circuit with
three inputs A0, A1, A2 and one output 0.
 DESIGN PROCEDURE
• In a digital circuit the output is depending on its
inputs Combination.
• The combinational logic circuit is memory less.
• This logic circuit deals with the method of
combining basic gates to get desired solution ie.,
output.
• Combinational logic circuits can be constructed
using logic gates and without feedback.
 Combinational Logic Function

A simple mathematical model of combinational logic

functions is a unit with inputs and outputs as shown
in Fig.
• X is the set of input variables
• Y is the set of output variables
• The output Y0 is a function of Xo, X1, …Xn
• Similarly Y2 ,Y3 ...Yn s are also functions of X0, X1,
X2 .......... to Xn
 Design steps:
The combination logic circuit can be designed following
steps:

1. Select the problem

2. Define input Variables
3. Define output Variables
4. Construct the truth table
5. Write switching functions
6. Simplify switching functions
7. Draw logic diagram
8. Develop logic circuit using gates Combinational
Circuits
• ADDER
 Arithmetic Circuits – Basic Building Blocks

• Combinational logic circuits are used to perform

addition and subtraction operations on binary
numbers.
• Addition and subtraction are the two most commonly
used arithmetic operations.
• Multiplication and division are respectively the
processes of repeated addition and repeated
subtraction.
• The basic building blocks are used to to perform
arithmetic operations on binary numbers.
• These include half-adder, full adder, half-subtractor,
full subtractor and controlled inverter.
 Half-Adder

• A half-adder is an arithmetic circuit block .

• It can be used to add two bits.
• The circuit has two input bits to be added.
• It has two outputs, (one producing the SUM
output and the other producing the CARRY).
Figure 2.1 shows the truth table of a half-adder,
showing
• all possible input combinations and
• the corresponding outputs.
 Figure 2.1
• The Boolean expressions for the SUM and
CARRY outputs are given by the equations
• SUM S = A.B’+A’.B (2.1) (EX-OR Gate)
• CARRY C = A.B (2.2) (AND Gate )
• There is no scope for further simplification.
• The first one representing the SUM (Σ )
output is that of an EX-OR gate,
• The second one representing the CARRY
output is that of an AND gate.
 Full Adder

• A full adder circuit is an arithmetic circuit block

.
• It is used to add three bits.
• It to produce a SUM and a CARRY output.

• It is necessary to add binary numbers with a

large number of bits.
The procedure for adding larger binary
numbers.

• We begin with the addition of LSBs of the two

numbers
• Record the sum under the LSB column and
the carry is forward to the next higher column bits if

any.
• So we required three bits adder because there
were a carry from the previous addition.
 A B Cin SUM Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

Boolean expression for three bit adder:

Sum = A’.B’.Cin+A’.B.C’in+A.B’.C’in+A.B.Cin (7.7)

Cout = A’.B.Cin+A.B’.Cin+A.B.C’in+A.B.Cin (7.8)

Figure 7.7 shows the truth table of a full adder
circuit.
• It shows all possible input combinations and
corresponding outputs.
• First write the Boolean expressions for
• SUM and
• CARRY outputs in terms of input
variables.
Cin = Carry input
Cout = Carry output
• The Boolean expressions for the two output
variables are given
Sum = A’.B’.Cin+A’.B.C’in+A.B’.C’in+A.B.Cin
Cout = A’.B.Cin+A.B’.Cin+A.B.C’in+A.B.Cin

• The next step is to simplify the two

expressions with the help of Boolean
theorem or the Karnaugh mapping
technique.
The expressions for SUM and CARRY outputs can
be rewritten as follows:
S = F(A,B,Cin ) = (1,2,4,7)
C = F(A,B,Cin ) = (3,5,6,7)

Sum = A’.B’.Cin+ A’.B.C’in+A.B’.C’in+A.B.Cin

• S = C’ in(A’.B+A.B’)+ Cin (A.B+A’.B’)
• S = C’in.(AꚚB)+Cin.(AꚚB)’
• S = (AꚚB) Ꚛ Cin
• Similarly, the expression for CARRY output can
be rewritten as follows:
• Cout = B.Cin.(A+A’) + A.B + A.Cin.(B+B’)
= A.B+ A’.B.Cin + A.B.Cin +A.B.Cin+ A.B’.Cin
= A.B+ A.B.Cin + A’.B.Cin+A.B’.Cin
= A.B.(1+Cin) + Cin (A’.B+A.B’ ) (1+Cin = 1)
Cout = A.B+ (AꚚB).Cin (A’.B+A.B’)= (AꚚB)

• Figure shows the logic circuit diagram of the

full adder.
• A full adder can also be build by two half-
adders and an OR gate.
• Similarly, the expression for CARRY output can
be rewritten as follows:
• Cout = B.Cin.(A+A’) + A.B + A.Cin.(B+B’)
= A.B+ A’.B.Cin + A.B.Cin +A.B.Cin+ A.B’.Cin
= A.B+ A.B.Cin + A’.B.Cin+A.B’.Cin
= A.B.(1+Cin) + Cin (A’.B+A.B’ ) (1+Cin = 1)
Cout = A.B+ (AꚚB).Cin (A’.B+A.B’)= (AꚚB)

• Figure shows the logic circuit diagram of the

full adder.
• A full adder can also be build by two half-
adders and an OR gate.
• A single full adder circuit can be used to add one-bit
binary numbers only.
• To add larger number of bits, these adders are
cascaded.
• For example, a four-bit binary adder would require
four full adders ( connected in cascade)
• shown in Fig.
• Figure shows such an arrangement.
• (A3A2A1A0) and (B3B2B1B0) are the two binary numbers
to be added
• A0 and B 0representing LSBs and A3 and B3
representing MSBs of the two numbers.
Figure Four-bit binary adder.
 BINARY Parallel Adder

• Two or more full-adders are connected to form

parallel binary adders.
• A single full-adder is capable of adding two 1-bit
numbers with an input carry.
• To add binary numbers with more than one bit, you
must use additional full-adders.
• When one binary number is added to another, each
column generates a sum bit and a carry bit (Carry
bit is feed to the next left column )
• It is illustrated here with 2-bit numbers.
• To add two binary numbers, a full-adder (FA) is
required for each bit in the binary numbers.
• So for 2-bit numbers, two adders are needed;
• for 4-bit numbers, four adders are needed and so on.
• The carry output of each adder is connected to the
carry input of the next higher-order adder
• It is shown in Figure 6–7 for a 2-bit binary adder.
Note
• either a half-adder can be used for the least
significant position or the carry input of a full-adder
can be made 0 (grounded) because there is no carry
input to the least significant bit position.
FIGURE Block diagram of a basic 2-bit parallel binary adder using
two full-adders.
• In Figure , the least significant bits (LSB) of the
two numbers are represented by A1 and B1.
• The next higher-order bits are represented by
A2 and B2.
• The three sum bits are S1, S2, and S3(Cout).

Notice that the output carry from the left-most

full-adder becomes the most significant bit
(MSB) in the sum, c3.
 Four-Bit Parallel Adders

• A group of four bits is called a nibble.

• A basic 4-bit parallel adder is implemented with
four full-adder. (shown in Figure ).
• The LSBs (A1 and B1) being added in the right-most
full-adder;
• The higher-order bits MSBs ( A3 AND B3) are added
in the left-most full-adder.
• The carry output of each adder is connected to the
carry input of the next higher-order adder as
indicated.
• These carries are called as internal carries.
FIGURE 6–9 A 4-bit parallel adder
 Truth table for a 4-Bit Parallel Adder
TABLE
Cn-1 An Bn Sn Cn

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1
• Table : truth table for a 4-bit adder.
Truth tables may be called function tables
or functional truth tables.
• The subscript n represents the adder bits and
can be 1, 2, 3, or 4 for the 4-bit adder.
• Cn-1 is the carry from the previous adder.
• Carries C1, C2, and C3 are generated
internally. C0 is an external carry input and C4
is an output.
 The Look-Ahead Carry Adder
• The speed of an addition operation is limited by the
time required for the carries to propagate,
(or ripple, through all the stages of a parallel
adder.)
• look-ahead carry addition is one method to speeding
up the addition process by eliminating this ripple carry
delay.
• The look-ahead carry adder anticipates the output
carry of each stage.
• based on the inputs, produces the output carry by
either carry generation (Cg) or carry propagation (Cp).
• Carry generation occurs when an output carry
is produced (generated) internally by the full-
adder.
• A carry is generated only when both input bits
are 1s.
• The generated carry, Cg, is expressed as the
AND function of the two input bits, A and B.
• Cg= A.B
• The conditions for
• carry generation and
• carry propagation
are illustrated in Figure 6–15.
• The three arrowheads symbolize ripple
(propagation).
FIGURE Illustration of conditions for carry generation and carry
propagation
• The output carry of a full-adder can be expressed in
terms of both the generated carry (Cg) and the
propagated carry (Cp).
• The output carry (Cout) is a 1 if the generated carry is
a 1 OR if the propagated carry is a 1 AND the input
carry (Cin) is 1.
• That is we get an output carry of 1 if it is generated
by the full-adder (A = 1 AND B = 1) or if the adder
propagates the input carry (A = 1 OR B = 1) AND Cin =
1.
• Cout = 1 if Cg =1 {A = 1 AND B = 1 } or Cp = 1
This relationship is expressed as
• Cout = Cg.Cp.Cin Equation 6–7
• For each full-adder, the output carry is
dependent on the generated carry (Cg), the
propagated carry (Cp), and its input carry
(Cin).
• Now let’s see how this concept can be applied
to a parallel adder.
• Individual stages are shown in Figure for a 4-
bit example.
• The input carry to each stage is the output
carry of the previous stage.
• The Cg and Cp functions for each stage.
• And are immediately available as soon as the
input bits A and B and the input carry to the
LSB adder are applied.
• Because they are dependent only on these
bits.
FIGURE Carry generation and carry propagation in terms of the
input bits to a 4-bit adder.
Example: 4-bit full-adder stage.
Full-adder 1:
• Cout1 = Cg1 + Cp1.Cin1
Full-adder 2:
Cin2 = Cout1
• Cout2 = Cg2 + Cp2Cin2
• = Cg2 + Cp2Cout1
• = Cg2 + Cp2(Cg1 + Cp1.Cin1)
• = Cg2 + Cp2Cg1 + Cp2.Cp1.Cin1
Full-adder 3:
Cin3 = Cout2
• Cout3 = Cg3 + Cp3.Cin3
• = Cg3 + Cp3Cout2
• = Cg3 + Cp3(Cg2 + Cp2.Cg1 + Cp2.Cp1.Cin1)
• = Cg3 + Cp3.Cg2 + Cp3.Cp2.Cg1 + Cp3.Cp2.Cp1.Cin1
Full-adder 4:
Cin4 = Cout3
• Cout4 = Cg4 + Cp4.Cin4
= Cg4 + Cp4.Cout3
= Cg4 + Cp4(Cg3 + Cp3.Cg2 + Cp3.Cp2.Cg1 +
Cp3.Cp2.Cp1.Cin1)
= Cg4 + Cp4.Cg3 + Cp4.Cp3.Cg2 +
Cp4.Cp3.Cp2.Cg1
+ Cp4Cp3.Cp2.Cp1.Cin1
Note
• In each of these expressions, the output carry for
each full-adder stage is dependent only on the initial
input carry (Cin1),
• the Cg and Cp functions of that stage, and the Cg and
Cp functions of the preceding stages.
• Since each of the Cg and Cp functions can be
expressed in terms of the A and B inputs to the full-
adders, all the output carries are immediately
available (except for gate delays),
• and you do not have to wait for a carry to ripple
through all the stages before a final result is achieved.
• Thus, the look-ahead carry technique speeds
up the addition process.
• The Cout equations are implemented with
logic gates and connected to the full-adders
to create a 4-bit look-ahead carry adder, as
shown in Figure 6–17.
 BCD Adder
• A BCD adder is used to perform the addition of
BCD numbers.
• four-bit binary represents a BCD digit.
• Ie., 0000, 0001, …… , 1001, the equivalent of
decimal numbers 0, 1, ….. , 9.
• When we add two BCD digits and we assume
that there is an input carry .
• The highest binary number we can get is the
equivalent of decimal number 19 (9+9+1).
• This binary number is going to be (10011)2.
• If we do BCD addition, we would expect the
answer to be (0001 1001)BCD.
• And if we restrict the output bits to the
minimum required, the answer in BCD would be
(11001)BCD.
• Table 7.1 lists the possible results in binary and
the expected results in BCD for a four-bit binary
adder to perform the addition of two BCD digits.
• The sum of the two BCD digits remains equal to
or less than 9, the four-bit adder produces the
correct BCD output.
• The binary sum and the BCD sum are the same up
to sum value 9 or less than 9.
• When the sum is greater than 9 that the two
results are different.
• It can also be seen from the table that, for a
decimal sum greater than 9 (or the equivalent
binary sum greater than 1001),
• if we add 0110 to the binary sum, we can get the
correct BCD sum and the desired carry output
• The Boolean expression that can apply the
necessary correction is written as
• C = K+Z3Z2+Z3Z1 ---------2.2
• Equation (2.2 )shows that the following
correction needs to be applied whenever
K = 1.
• This takes care of the last four entries.
• Also, a correction needs to be applied
whenever both Z3 and Z2 are ‘1’.
• This takes care of the next four entries from
the bottom, corresponding to a decimal sum
equal to 12, 13, 14 and 15.
• For the remaining two entries corresponding
to a decimal sum equal to 10 and 11, a
correction is applied for both Z3 and Z1, being
‘1’.
• While hardware-implementing, 0110 can be
added to the binary sum output with the help
of a second four-bit binary adder.
• The correction logic as dictated by the
Boolean expression (2.2) should ensure that
(0110) gets added only when the above
expression is satisfied.
• Otherwise, the sum output of the first binary
adder should be passed on as such to the final
output, which can be accomplished by adding
(0000) in the second adder.
• Figure 7.21 shows the logic arrangement of a
BCD adder capable of adding two BCD digits
with the help of two four-bit binary adders
and some additional combinational logic.
• This BCD adder can be used to add two single-
digit BCD numbers only.
• However, a cascade arrangement of single-
digit BCD adder can be used to perform the
addition of multiple-digit BCD numbers.
Example :
• For n-digit BCD adder would require n such
stages in cascade.
• As an illustration, Fig. 7.22 shows the block
diagram of a circuit for the addition of two
three-digit BCD numbers.
Three-digit BCD numbers
• The first BCD adder, labelled LSD (Least Significant Digit),
handles the least significant BCD digits.
• It produces the sum output (S3 S2 S1 S0), which is the BCD
code for the least significant digit of the sum.
• It also produces an output carry that is fed as an input
carry to the next higher adjacent BCD adder.
• This BCD adder produces the sum output (S7 S6 S5 S4),
which is the BCD code for the second digit of the sum, and
a carry output.
• This output carry serves as an input carry for the BCD
adder representing the most significant digits.
• The sum outputs (S11 S10 S9 S8) represent the BCD code for
the MSD of the sum.
 Multiplexers (Data Selectors)

• A multiplexer or MUX, also called a data selector, is

a combinational circuit with more than one input
line, one output line and more than one selection
line.
• A multiplexer (MUX) is a device that allows
digital/analog information from several sources
to be routed onto a single line for transmission
over that line to a common destination.
• The basic multiplexer has several data-input lines
and a single output line with data-select inputs.
• Data -select Inputs selects any one of the inputs to
be switched to the output line.
• If there are n selection lines, then the number
of maximum possible input lines is 2n and
• The multiplexer is known as 2n-to-1
multiplexer or 2n ×1 multiplexer.
• logic symbol for a 4-input multiplexer (MUX) is
shown in Figure 2–3.
• There are two data-select lines any one of the
four data-input lines can be selected.
FIGURE 2–3 Logic symbol for a 1-of-4 data
selector/ 1-of-4 multiplexer
 1-of-4 multiplexer
• In Figure 2–3, a 2-bit code on the data-select (S) inputs
will allow the data on the selected data input to pass
through to the data output.
• If a binary 0 (S1 = 0 and S0 = 0) is applied to the data-
select lines, the data on input D0 appear on the data-
output line.
• If a binary 1 (S1 = 0 and S0 = 1) is applied to the data-
select lines, the data on input D1 appear on the data
output.
• If a binary 2 (S1 = 1 and S0 = 0) is applied, the data
on D2 appear on the output.
• If a binary 3 (S1 = 1 and S0 = 1) is applied, the data on
A summary of 1-of-4 multiplexer operation is
given in Table
1-of-4 multiplexer Logic Circuit

• The logic circuitry required to perform this

multiplexing operation.
• The data output is equal to the state of the
selected data input.
• Derive a logic expression for the output in
terms of the data input and the select inputs.
 1-of-4 multiplexer
• The data output is equal to D0 only
if S1 = 0 and S0 = 0: Y = D0. S1. S0.
• The data output is equal to D1 only
if S1 = 0 and S0 = 1: Y = D1.S1.S0.
• The data output is equal to D2 only
if S1 = 1 and S0 = 0: Y = D2.S1.S0.
• The data output is equal to D3 only
if S1 = 1 and S0 = 1: Y = D3.S1.S0.
• These terms are ORed, the total expression for the data
output is

• Y = D0.S1.S0 + D1.S1.S0 + D2.S1.S0 + D3.S1.S0

 1-of-4 multiplexer

• The implementation of this equation requires

four 3-input AND gates, a 4-input OR gate,
and two inverters to generate the
complements of S1 and S0, as shown in Figure
2–4.
FIG 2–4 Logic diagram for a 4-i/p MUX. 1 of 4 MUX
1 of 4 MUX
 1 of 16 16-to-1 multiplexer
Example
• Design a 16-to-1 multiplexer using two 8-to-1 multiplexers having
an active LOW ENABLE input.
• The eight input lines would have 28 = 256 possible
combinations.
• However, in the case of an octal-to-binary encoder,
only eight of these 256 combinations would have any
meaning.
•The remaining combinations of input variables are
‘don’t care’ input combinations.
• Also, only one of the input line set a time is in logic ‘1’
state.
16-to-1 multiplexer
 DeMUltipleXer (DEMUX)
• A demultiplexer (DEMUX) basically reverses
the multiplexing function.
• It takes digital information from one line and
distributes it to a given number of output
lines.
• For this reason, the demultiplexer is also
known as a data distributor.
• Decoders can also be used as demultiplexers.
Figure 2–5 1 line to 5 line DEMUX
 Demultiplexer

• Figure 2–5 shows a 1-line-to-4-line

demultiplexer (DEMUX) circuit.
• The data-input Line goes to all of the AND
gates.
• The two data-select lines enable only one gate
at a time.
• The data appearing on the data-input line
will pass through the selected gate to the
associated data-output line.
Figure 1 to 4 de multiplexer
•Figure 8.18(a) shows the circuit
representation of a 1-to-4 demultiplexer.
•Figure 8.18(b) shows the truth table of
the demultiplexer when the input line is
held HIGH.
•A decoder, as mentioned earlier, is a
combinational circuit that decodes the
information on n input lines to a
maximum of 2n unique output lines.
Figure 2 1 line-to-4-line DEMUX
 Magnitude Comparator

•A magnitude comparator is a combinational circuit

that compares two given numbers and determines
whether one is equal to, less than or greater than
the other.
•The output is in the form of three binary variables
representing the conditions
A = B,
A > B and
A<B,
if A and B are the two numbers being compared.

•Depending upon the relative magnitude of the two

numbers, the relevant output changes state.
 Magnitude Comparator
• If the two numbers are four-bit binary
numbers and are designated as
•(A3 A2 A1 A0) and (B3 B2 B1 B0) the
two numbers will be equal if all pairs of
significant digits are equal, that is,
•A3 = B3, A2= B2 A1= B1 and A0=
B0.
 Magnitude Comparator
•In order to determine whether A is
greater than or less than B we inspect
the relative magnitude of pairs of
significant digits, starting from the most
significant position.
•The comparison is done by
successively comparing the next
adjacent lower pair of digits if the digits
of the pair under examination are
equal.
 Magnitude Comparator

•The comparison continues until a pair

of unequal digits is reached.

•In the pair of unequal digits,

if Ai = 1 and Bi = 0, then A > B,

and
if Ai = 0 and Bi = 1 then A < B.
•
 Magnitude Comparator

If X, Y and Z are three variables respectively

representing the X = (A = B), Y = (A > B) and
Z = ( A < B ) conditions, then the
Boolean expression representing these
conditions are given by the equations.

X = X3.X2.X1.X0 where Xi = Ai. Bi + A’i.B’i

( 25)

Y = A3.B’3 +X3.A2.B’2 +X3.X2.A1.B’1+X3.X2.X1.A0. B’0

( 26)

Z = A’3.B3 +X3.A’2.B2 +X3.X2.A’1.B1+X3.X2.X1.A’0.B0

( 27)
 Magnitude Comparator

•Let us examine equation (7.25).

X3 will be ‘1’ only when both A3 and B3 are equal.
Similarly, conditions for x2, x1 and x0 to be ‘1’
respectively are equal A2 and B2, equal A1 and
B1 and equal A0 and B0.
ANDing of x3, x2, x1 and x0 ensures that X will
be ‘1’ when x3, x2, x1 and x0 are in the logic ‘1’
state.
Thus, X = 1 means that A = B.
•On similar lines, it can be visualized that equations

(7.26) and(7.27) respectively represent

A > B and
A < B conditions.
Figure 7.36 shows the logic diagram of a four-bit magnitude comparator.
 Magnitude comparators

•Magnitude comparators are available in IC

form.
Example:
IC 7485 is a four-bit magnitude comparator
of the TTL logic family.
IC 4585 is a similar device in the CMOS
family.
7485 and 4585 have the same pin
connection diagram and functional table.
 Encoders
• An encoder is a multiplexer without
its single output line.
•It is a combinational logic function
that has
2n (or fewer) input lines and n output
lines,
which correspond to n selection lines
in a
multiplexer.
•The n output lines generate the binary
 Encoders

Example :
•octal-to-binary encoder.
•It have eight input lines, each representing
an octal digit, and
•three output lines representing the three-
bit binary equivalent.
The truth table for encoder is shown
In the truth table,
• D0 to D7 represent octal digits 0 to 7.
• A, B and C represent the binary digits.
 Table 8.8 Truth table of an
encoder
INPUTS OUTPUTS
D0 D1 D2 D3 D4 D5 D6 D7 A B C
1 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 1 0 0
0 0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 0 1 0 1 1 0

0 0 0 0 0 0 0 1 1 1 1
Encoders Hardware
Implementation
•Figure below shows the hardware
implementation of the octal-to-binary encoder
described by the truth table in above Table 8.8.

• This circuit has produces an all 0s output

sequence when all input lines are in logic ‘0’
state.
• This can be overcome by having an additional
line to indicate an all 0s input sequence.
Hardware implementation
 Priority Encoder

A priority encoder is a practical form of

an encoder.
• In this type encoder, a priority function
is assigned to each input.
• when more than one input is
simultaneously active, the input with
the highest priority is encoded.
• We will illustrate the concept of priority
encoding with the help of an example.
 Priority Encoder
Example :
•the octal to-binary encoder:
•an input priority for higher-order digits.
•Let us also assume that input lines D2,
D4 and D7 are all simultaneously in logic
‘1’ state.
• In that case, only D7 will be encoded
and the output will be 111.
•The truth table of such a priority
encoder will then be modified to what is
shown in Table 8.9.
 Priority Encoder

•Looking at the last row of the table, it

implies that, if D7 = 1, then, irrespective
of the logic status of other inputs, the
output is 111 as D7 will only be encoded.
•As another example, Fig. 8.16 shows the
logic symbol and truth table of a 10-line
decimal to four-line BCD encoder
providing priority encoding for higher-
order digits, with digit 9 having the
highest priority
 Priority Encoder
In the functional table shown.
• The input line with highest priority
having a LOW on it is encoded
irrespective of the logic status of the
other input lines.
 Table 8.9 Priority encoder.

INPUTS OUTPUTS
D0 D1 D2 D3 D4 D5 D6 D7 A B C
1 0 0 0 0 0 0 0 0 0 0
X 1 0 0 0 0 0 0 0 0 1
X X 1 0 0 0 0 0 0 1 0
X X X 1 0 0 0 0 0 1 1
X X X X 1 0 0 0 1 0 0
X X X X X 1 0 0 1 0 1
X X X X X X 1 0 1 1 0
X X X X X X X 1 1 1 1
Figure 10-line decimal to four-line
BCD priority encoder
output : low level input : low
level
 10-line decimal to four-line BCD priority
encoder
INPUTS OUTPUTS
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D C B A

X X X X X X X X X 0 0 1 1 0
X X X X X X X X 0 1 0 1 1 1
X X X X X X X 0 1 1 1 0 0 0
X X X X X X 0 1 1 1 1 0 0 1
X X X X X 0 1 1 1 1 0 1 1 0
X X X X 0 1 1 1 1 1 1 0 1 1
X X X 0 1 1 1 1 1 1 1 1 0 0
X X 0 1 1 1 1 1 1 1 1 1 0 1
X 0 1 1 1 1 1 1 1 1 1 1 1 0
0 1 1 1 1 1 1 1 1 1 1 1 1 1
 Decoders

• Decoder is a special case of a

demultiplexer without the input line.
• A demultiplexer is a combinational logic circuit
with an input line, 2n output lines and n select
lines.
• It passes the information present on the input
line to any of the output lines.
• The output line that gets the information present
on the input line is decided by the bit status of
the selection lines. A
•Figure 8.19 shows the circuit
representation of 2-to-4, 3-to-8 and
4-to-
16 line decoders.
•If there are some unused or ‘don’t
care’ combinations in the n-bit code,
then there will be fewer than 2n output
lines.

• If there are three input lines, it can

have a maximum of eight unique output lines
Figure 8.19 of 2-to-4, 3-to-8 and 4-to-16
line decoders
• If, in the three-bit input code, the only used
three-bit combinations are 000, 001, 010, 100,
110 and 111 (011 and 101 being either
unused or don’t care combinations),
• Then this decoder will have only six output
lines.
• In general, if n and m are respectively the
numbers of input and output lines,
• then m ≤ 2n.
•A decoder can generate a maximum of 2n
possible minterms with an n-bit binary
code.
• In order to illustrate further the operation
of a decoder, consider the logic circuit
diagram in Fig. 8.20.
•This logic circuit, implements a 3-to-8 line
decoder function.
•This decoder has three inputs designated
as A, B and C and eight outputs designated
as D0, D1, D2, D3, D4, D5, D6 and D7.
3-to-8 line decoder Fig. 8.20
TRUTH TABLE
•From the truth table given along with the logic
diagram it is clear that, for any given input
combination, only one of the eight outputs is in
logic ‘1’ state.
•Thus, each output produces a certain minterm that
corresponds to the binary number currently present
at the input.
•In the present case, D0, D1, D2, D3,D4, D5, D6 and D7
respectively represent the following minterms:

D0→ A’.B’.C’ .D1 → A’.B’.C. D2 → A’.B.C’.D3 → A’.B.C

D4→ A’.B’.C’.D5 → A.B’.C. D6 → A.B.C’.D7 → A.B.C

 Binary Coded Decimal (BCD)

• BCD is the encoding scheme each of the

decimal numbers(0-9) is represented by its
equivalent binary pattern(which is generally of
4-bits).
 Seven segment

• Seven Segment display is an electronic device

which consists of seven Light Emitting Diodes
(LEDs) arranged in a some definite pattern
(common cathode or common anode type),
which is used to display Hexadecimal
numerals(in this case decimal numbers, as
input is BCD i.e., 0-9).
 Seven segment

• Two types of seven segment LED display:

• Common Cathode Type: In this type of display all
cathodes of the seven LEDs are connected together
to the ground or -Vcc(hence, common cathode) and
LED displays digits when some ‘HIGH’ signal is
supplied to the individual anodes.
• Common Anode Type: In this type of display all the
anodes of the seven LEDs are connected to battery
or +Vcc and LED displays digits when some ‘LOW’
signal is supplied to the individual cathodes.
 Seven segment
• seven segment display does not work by
directly supplying voltage to different segments
of LEDs. First, our decimal number is changed
to its BCD equivalent signal then BCD to seven
segment decoder converts that signals to the
form which is fed to seven segment display.
This BCD to seven segment decoder has four
input lines (A, B, C and D) and 7 output lines (a,
b, c, d, e, f and g), this output is given to seven
segment LED display which displays the
decimal number depending upon inputs.
• segment LED display
 .

Seven segment
 Truth Table for a 7-segment display

Individual Segments Truth Table for a 7-segment displa

Display
a b c d e f g

× × × × × × 0
× × 1
× × × × × 2
× × × × × 3
× × × × 4
× × × × × 5
× × × × × × 6
× × × 7
Individual Segments
Display
a b c d e f g

× × × × × × × 8
× × × × × × 9
× × × × × × A
× × × × × b
× × × × C
× × × × × d
× × × × × E
× × × × F
Seven segment
 Seven segment

• Note –
• For Common Anode type seven segment LED display, we
only have to interchange all ‘0s’ and ‘1s’ in the output
side i.e., (for a, b, c, d, e, f, and g replace all ‘1’ by ‘0’ and
vice versa) and solve using K-map.
• Output for first combination of inputs (A, B, C and D) in
Truth Table corresponds to ‘0’ and last combination
corresponds to ‘9’. Similarly rest corresponds from 2 to 8
from top to bottom.
• BCD numbers only range from 0 to 9,thus rest inputs
from 10-F are invalid inputs.
• Common Cathode and Common Anode Format
Seven segment K-Maps:
#for a:
 Seven segment
• #for b:
• #for c:
• #for d:
• #for e:
• #for f:
• #for g:
• Display Decoder Example
 Parity Generator And Parity Checker Circuits

• Majority of modern communication is Digital

in nature i.e., it is a combination of 1’s and 0’s.
The digital data is transmitted either through
wires (in case of wired communication) or
wireless. Even in an advanced mode of
communication, there will be errors while
transmitting data (due to noise).
 Parity Generator And Parity Checker Circuits

• The simplest of errors is corruption of a bit

i.e., a 1 may be transmitted as a 0 or vice-
versa. To confirm whether the received data is
the intended data or not, we should be able to
detect errors at the receiver. In this tutorial,
we will learn about Parity Bit, Even Parity, Odd
Parity, Parity Generator and Parity Checker
with a practical example and practical circuit
 Parity Generator And Parity Checker Circuits

• What Is Parity Bit?

• A parity bit is a basic way to check for errors in
digital communications and data storage, used
to make sure data stays accurate. It’s an extra
binary digit added to a string of binary code. In
digital systems, when binary data is
transmitted and processed, data may be
subjected to noise so that such noise can alter
0s (of data bits) to 1s and 1s to 0s.
 Parity Generator And Parity Checker Circuits

• Hence, a Parity Bit is added to the word containing

data in order to make number of 1s either even or
odd. The message containing the data bits along
with parity bit is transmitted from transmitter to
the receiver. At the receiving end, the number of
1s in the message is counted and if it doesn’t
match with the transmitted one, it means there is
an error in the data. Thus, the Parity Bit it is used
to detect errors, during the transmission of binary
data.
 Parity Generator And Parity Checker Circuits

• Even Parity And Odd Parity

• The sum of the data bits and parity bits can be even or odd.
• Even Parity:
• The parity bit is adjusted so that the total number of 1s in the code,
including the parity bit, is even. If there are already an even number
of 1s, the parity bit is 0. If there are an odd number of 1s, the parity
bit is 1.
• Odd Parity:
• The parity bit is adjusted to make the total number of 1s odd. If there
are already an odd number of 1s, the parity bit is 0. If it’s even, the
parity bit is set to 1. Such error detecting and correction can be
implemented by using Ex-OR gates (since Ex-OR gate produce zero
output when there are even number of inputs).
 Parity Generator And Parity Checker Circuits

• To produce two bits sum, one Ex-OR gate is

sufficient whereas for adding three bits, two
Ex-OR gates are required as shown in below
figure.
 Parity Generator And Parity Checker Circuits

• What Is A Parity Generator?

• Parity Generator in digital electronics is a combinational circuit
that accepts an n-1 bit data and generates the additional bit
that is to be transmitted with the bit stream. This additional or
extra bit is called as a Parity Bit.
• In even parity bit scheme, the parity bit is ‘0’ if there are even
number of 1s in the data stream and the parity bit is ‘1’ if
there are odd number of 1s in the data stream.
• In odd parity bit scheme, the parity bit is ‘1’ if there are even
number of 1s in the data stream and the parity bit is ‘0’ if
there are odd number of 1s in the data stream. Let us discuss
both even and odd parity generators.
 Parity Generator And Parity Checker Circuits

• Even Parity Checker Truth Table

• The figure below shows the 3 bit truth table of
even parity generator in which 1 is placed as
parity bit in order to make all 1s as even when
the number of 1s in the truth table is odd.
 Parity Generator And Parity Checker Circuits

• The K-map simplification for 3-bit message

even parity generator is
 Parity Generator And Parity Checker Circuits

• From the above parity checker truth table, the simplified expression of the parity bit can be written as

From the above parity checker truth table, the simplified expression of the parity bit
can be written as
 Parity Generator And Parity Checker Circuits
• To generate the even parity bit for a 4-bit data, three
Ex-OR gates are required to add the 4-bits and their
sum will be the parity bit.
 Parity Generator And Parity Checker Circuits

• What Is A Parity Checker?

• Parity Checker is a logic circuit that checks for
possible errors in the transmission. This circuit
can be an even parity checker or odd parity
checker depending on the type of parity
generated at the transmission end. When this
circuit is used as even parity checker, the
number of input bits must always be even.
 Parity Generator And Parity Checker Circuits

• ven Parity Checker

• Consider that three input message along with even
parity bit is generated at the transmitting end. These 4
bits are applied as input to the parity checker circuit,
which checks the possibility of error on the data. Since
the data is transmitted with even parity, four bits
received at circuit must have an even number of 1s.
• If any error occurs, the received message consists of
odd number of 1s. The output of the parity checker is
denoted by PEC (Parity Error Check).
 Parity Generator And Parity Checker Circuits
• Even Parity Checker Truth Table
• The below table shows the truth table for the Even Parity Checker in which
PEC = 1 if the error occurs, i.e., the four bits received have odd number of 1s
and PEC = 0 if no error occurs, i.e., if the 4-bit message has even number of 1s.
 Parity Generator And Parity Checker Circuits
• The above truth table can be simplified using K-map as shown
below.
Parity Generator And Parity Checker Circuits
 Parity Generator And Parity Checker Circuits
• The above logic expression for the even parity checker can be
implemented by using three Ex-OR gates as shown in figure. If the
received message consists of five bits, then one more Ex-OR gate is
required for the even parity checking.
Parity Generator And Parity Checker Circuits