NPTEL Online Certification Course

NOC22-CS110: Multi-Core Computer Architecture -

Storage and Interconnects
Assignment-3: Detailed Solution
Indian Institute of Technology Guwahati

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1. Which one of the following is the most optimum way to reduce the cache miss penalty?

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A) Larger block size
(B) Multi-level caching

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(C) Larger cache size

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(D) Higher Associativity

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A miss penalty refers to the extra time required to bring the data into the cache from the
main memory whenever there is a miss in the cache. Multilevel caches are one way to
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improve cache performance by reducing the miss penalty.
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2. Compulsory misses in a cache can be reduced by _
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(A) increasing associativity

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(B) increasing the number of sets in the cache

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(C) increasing cache block size

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(D) increasing read ports

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Cache misses at the first encounter of a block are called "compulsory misses." When we
have a larger block, the probability of a cache hit will increase, thereby reducing
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compulsory misses.
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3. A computer system has 16 MB byte addressable main memory and 64 KB 4-way set
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associative cache memory with a block size of 256 bytes. Consider the following physical
addresses.
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A1=0x42C84A, A2=0x5E485A
Which one of the following statements is FALSE?
(A) A1 and A2 are mapped to the same set.
(B) A1 and A2 have different tag values.
(C) A1 and A2 are mapped to a different set.
(D) A1 and A2 have different block offset
 NPTEL Online Certification Course
NOC22-CS110: Multi-Core Computer Architecture -
Storage and Interconnects
Assignment-3: Detailed Solution
Indian Institute of Technology Guwahati

No. of sets = Cache Size / (Block size * Associativity)

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= 64 KB/ 256 B * 4

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= 2^6 * 2^10 / 2^8 * 2^2

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= 2^6

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No. of bits representing Set Index = 6

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No. of bits representing Block Offset = 8 (since Block Size is 256 B)

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No. of bits representing Physical Address = 24 bits (since Main memory Size = 16MB)
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No. of bits representing Tag = 24 - 6 - 8 = 10
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A1 = 0x42C8A4 = 0100001011 001000 01001010

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A4 = 0x5E48A5 = 0101111001 001000 01011010

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4. For a cache memory of a given capacity, as block size reduces, there is

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(A) a decrease in both compulsory misses and conflict misses.

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(B) a decrease in compulsory misses and an increase in conflict misses.

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(C) an increase in both compulsory misses and conflict misses.

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(D) an increase in compulsory misses and a decrease in conflict misses.

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Without changing the cache capacity and by reducing the block size only, compulsory misses
would be increased as only a small amount of data (small block) can be brought to the cache in
one cache miss. Since less data is brought and if the program shows spatial locality there will be
frequent cache misses. When block size reduces, it will accommodate more cache blocks in the
cache. This will spread the mapping more widely and reduce conflict misses.

5. Avoiding address translation from virtual to physical before cache indexing will __
 NPTEL Online Certification Course
NOC22-CS110: Multi-Core Computer Architecture -
Storage and Interconnects
Assignment-3: Detailed Solution
Indian Institute of Technology Guwahati
(A) increase hit time
(B) decrease hit time

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(C) increase miss rate

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(D) increase miss penalty

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Address translation is the process of converting virtual addresses into physical addresses.

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To access the cache before indexing and tag comparison, it has to perform address
translation, which increases the hit time. Therefore, avoiding address translation will

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reduce hit time.

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6. Which of the following is TRUE for inclusive cache?

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(A) L1 and L2 caches will not have any data in common
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(B) contents of L2 cache is a subset of contents L1 cache

(C) contents of L1 cache is a subset of contents of L2 cache

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(D) every data item present in L2 is present in L1 also

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If L1 cache is a subset of L2, it is called inclusive cache. Since L2 cache is larger than
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L1, L2 cannot be a subset of L1 cache.

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7. Assume an L1 cache with a hit rate of 70% and an L2 cache with a local miss rate of 6%.
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If there are 1000 memory access initiated by CPU, then the number of access that will
find a hit in the L2 cache is ___________.
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(A) 940
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(B 700
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(C) 18
(D) 282

Number of access that will miss in L1 cache = (Miss rate_L1 * # memory access to L1)

= 0.3*1000 = 300
 NPTEL Online Certification Course
NOC22-CS110: Multi-Core Computer Architecture -
Storage and Interconnects
Assignment-3: Detailed Solution
Indian Institute of Technology Guwahati
Hence, there are 300 memory accesses to the L2 cache.

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Number of misses in L2 cache = (Miss rate_L2 * # memory access to L2)

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= 0.06*300 = 18.

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Number of memory accesses that will hit in L2 = 300-18=282

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8. A cache has a hit time of 10 ns and hit rate of 60%. An optimization was made to
increase hit rate to 70% but the hit time was increased to 15 ns. The optimization resulted

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in a 10% reduction in average memory access time. Assume that the miss penalty is
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unaffected by the optimization. The miss penalty of the cache (in ns) is _____.
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(A) 115
(B 110
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(C) 90
(D) 100
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Ans: 100
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Hit time_old = 10 ns
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Hit rate_old = 0.6

Hit time_opt = 15 ns
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Hit rate_opt = 0.7

AMAT_opt = 0.9 AMAT_old
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AMAT = Hit time + Miss rate * Miss penalty_L1

AMAT_opt/AMAT_old = 0.9

0.9 = (15 + (0.3 * x) / (10 + (0.4 * x))

x = 100
Miss Penalty_L1 = 100 ns
 NPTEL Online Certification Course
NOC22-CS110: Multi-Core Computer Architecture -
Storage and Interconnects
Assignment-3: Detailed Solution
Indian Institute of Technology Guwahati

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9. Consider a memory system with L1 and L2 caches. From the CPU, there are 300 requests

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to the L1 cache. Among those requests, 260 are hit at L1. If there are 8 misses in the L2
cache, then the local miss rate at the L2 cache (rounded to one decimal place) is

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________.

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Correct answer: 0.2

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No of misses at L1 = No of requests at L2 = 300-260 = 40
No of misses at L2 = 8 no
Local miss rate at L2 = number of misses at L2 / total number of requests at L2
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= 8/40 = 0.2
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10. The average memory access time for a memory hierarchy system with one level of cache
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and the main memory is 5 ns. The hit time and miss penalty of the cache are 2 ns and 100
ns, respectively. The hit rate of the cache (round off to two decimal places) is ______.
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Ans: 0.97
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AMAT = Hit time + Miss rate * Miss penalty_L1

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Putting the values in the formula we get,

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5 = 2 + (1- Hit_rate) * 100

Hit_rate = 0.97
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