Computer Organization

Fall 2021
Lecture 6
Basic Computer

Instruction Cycle
 PROCESSOR REGISTERS
Registers in the Basic Computer

11 0
PC
Memory
11 0
4096 x 16
AR
15 0
IR CPU
15 0 15 0
TR DR
7 0 7 0 15 0
OUTR INPR AC

List of Registers
DR 16 Data Register Holds memory operand
AR 12 Address Register Holds address for memory
AC 16 Accumulator Processor register
IR 16 Instruction Register Holds instruction code
PC 12 Program Counter Holds address of instruction
TR 16 Temporary Register Holds temporary data
INPR 8 Input Register Holds input character
OUTR 8 Output Register Holds output character
 Common Bus System
S2
S1 Bus
S0
Memory unit 7
4096 x 16
Address
Write Read
AR 1
• The connection between
LD INR CLR
PC 2
register is done through
LD INR CLR

DR 3 bus which saves the

LD INR CLR
E
circuitry.
ALU AC 4

LD INR CLR

INPR
IR 5
LD
TR 6
LD INR CLR
OUTR
Clock
LD
16-bit common bus
 COMMON BUS SYSTEM

Read
INPR
Memory Write
4096 x 16

Address E ALU

AC

L I C

L I C L

L I C DR IR L I C

PC TR

AR OUTR LD

L I C

7 1 2 3 4 5 6

16-bit Common Bus

 Common Bus System
 Three control lines, S2, S1, and S0 control which register the bus selects as its input
S2 S1 S0 Register
0 0 0 x
0 0 1 AR
0 1 0 PC
0 1 1 DR
1 0 0 AC
1 0 1 IR
1 1 0 TR
1 1 1 Memory

 Either one of the registers will have its load signal activated, or the memory will have its
read signal activated
 determine where the data from the bus gets loaded

 The 12-bit registers, AR and PC, have 0’s loaded onto the bus in the high order 4-bit
positions

 When the 8-bit register OUTR is loaded from the bus, the data comes from the low order 8
bits on the bus.
 Common Bus System

 For your information, the content of any register can be applied onto the bus and
an operation can be done in the adder and logic unit during the same clock cycle

 At the end of the cycle the content of the bus into is transferred to the destination
register, and the output of the adder and logic unit into the AC

 For example, the two microoperations

DR←AC and AC←DR (Exchange)

can be executed at the same time

 This is done by:

 Common Bus System

 place the contents of AC on the bus (S2S1S0=100)

 activate the LD (load) input of DR

 Transfer the contents of the DR through the adder and logic unit into AC

 activate the LD (load) input of AC

 This is done through the same clock cycle.

 The two transfers occur upon the arrival of the clock pulse transition at the end of
the clock cycle.
Basic Computer

Instruction
Instruction Cycle
Cycle
 AC-based ISA
 The simplest way to organize a computer
❑ One processor register : AC(Accumulator)
➢ The operation is performed with the memory operand and the content of AC

❑ Memory :4096 x 16
➢ Store each instruction code(program) and operand (data) in 16-bit memory word

❑ Instruction code format with two parts : Op. Code + Address

➢ Op. Code : specify 16 possible operations(3 bit)

➢ Address : specify the address of an operand(12 bit)

➢ Mode : specify how to find the operand in memory (1 bit)

15 14 12 11 0
I Opcode Address

Addressing
mode
 Instruction Processing

 Instruction processing cannot occur in a single clock cycle – it is too complicated !

 Must fetch the instruction from memory and load the instruction register, IR.
 Must decode the Operation Code to determine whether data must be fetched and
whether we fetch data directly, or indirectly

 Must fetch required data, if any, from memory into CPU

 OR, must store data from CPU into memory

 OR, must obtain data from Input

 OR, must place data for Output

 Must process the data according to instruction logic

 Thus, the instruction cycle consists of a controlled sequence of microoperations

 INSTRUCTION CYCLE

 In Basic Computer, a machine instruction is executed in the following cycle:

1. Fetch an instruction from memory
2. Decode the instruction and calculate effective address (EA)
3. Execute the instruction

 After an instruction is executed, the cycle starts

again at step 1, for the next instruction

 Note: Every different processor has its own

(different) instruction cycle
 Instruction fetch
 Instruction Fetch : T0, T1
T0 : AR  PC
T1 : IR  M [ AR], PC  PC + 1
 It means to get the instruction from the memory and
T1=1
place it in IR s2 0 1
T0=1 1 1
s1
Bus
0 1
 It takes two times T0,T1 s0

Memory
Memory unit
unit 7

 The PC is assumed to hold the address of the next Address

Read

instruction to be executed.
AR 1
 The PC is transferred to AR which is connected to the LD

Address Bus of memory. PC 2

INR

 The AR provides the selection input to the address bus

IR 5
multiplexer to enable RAM-CPU data transfers LD

Clock

 The data stored at the selected address is transferred

Common bus

onto the Bus and then to the IR in the CPU.

 Instruction Fetch
 T0 =1 T0 : AR  PC
T1 : IR  M [ AR], PC  PC + 1
1) Place the content of PC onto the bus by making
the bus selection inputs S2S1S0=010 T1=1
s2 0 1
T0=1
2)Transfer the content of the bus to AR by s1
Bus
1 1
0 1
enabling the LD input ofAR. s0

Memory
Memory unit
unit 7
 T1 =1 Address

Read
1) Enable the read input memory
2) Place the content of memory onto the bus by
AR 1
making S2S 1S 0= 111 LD

3)Transfer the content of the bus to IR by enable

the LD input of IR PC 2
INR

4) Increment PC by enabling the INR input of PC

IR 5

LD

Clock

Common bus
 Instruction Decode
 The operation code in IR is decoded to determine the type of instruction

 The indirect bit is transferred to flip-flop I

 The address part of the instruction is transferred to AR

T2 : {D0,...,D7}  DEC( IR(12-14) ),AR  IR(0-11), I  IR(15)

Note the reference to a The AR may be directly

DECoder unit to explicitly connected to the IR
access the IR bits indicated address bits indicated

NOTE:
All instructions share the steps T0, T1 and T2.
IT3: AR  M[AR] However, depending on what each specific
instruction requires, the control logic for
higher time steps is more complicated,
I’T3: Nothing requiring more inputs.
Thank you