RAJ KUMAR GOEL INSTITUTE OF

TECHNOLOGY , Ghaziabad
Computer Organization And Architecture
BCS-302

Unit: III

COA

Dr. Vinish Kumar

B Tech :3th Sem Professor
CSE(AI&ML)
 Course Outcomes
Course outcome: After completion of this course students will be
able to:

Study of the basic structure and operation of a

CO 1 K1, K2
digital computer system.
Analysis of the design of arithmetic & logic unit
CO 2 and understanding of the fixed point and floating- K2, K4
point arithmetic operations.
Implementation of control unit techniques and the
CO 3 K3
concept of Pipelining
Understanding the hierarchical memory system,
CO 4 K2
cache memories and virtual memory
Understanding the different ways of
CO 5 communicating with I/O devices and standard I/O K2, K4
interfaces
 CO 3

Implementation of control unit techniques and

the concept of Pipelining
 INTRODUCTION
INTRODUCTION
• Every different processor type has its own design and it contains:-
– Many registers
– Multiple arithmetic units, for both integer and floating point calculations
– The ability to pipeline several consecutive instructions to speed execution
– Etc.
• Program
– A sequence of (machine) instructions
• (Machine) Instruction
– A group of bits that tell the computer to perform a specific operation (a sequence
of micro-operation)
• The instructions of a program, along with any needed data are stored in memory
• The CPU reads the next instruction from memory
• It is placed in an Instruction Register (IR)
• Control circuitry in control unit then translates the instruction into the sequence of
microoperations necessary to implement it
 INSTRUCTION FORMAT
• A computer instruction is often divided into two parts
– An opcode (Operation Code) that specifies the operation for that instruction
– An address that specifies the registers and/or locations in memory to use for that
operation
• In the Basic Computer, since the memory contains 4096 (= 212) words, we needs 12
bit to specify which memory address this instruction will use .
• In the Basic Computer, bit 15 of the instruction specifies the addressing mode (0:
direct addressing, 1: indirect addressing).
• Since the memory words, and hence the instructions, are 16 bits long, that leaves 3
bits for the instruction’s opcode.

Instruction Format
15 14 12 11 0
I Opcode Address

Addressing
mode
 ADDRESSING MODES
• The address field of an instruction can represent either
– Direct address: the address in memory of the data to use (the address of the
operand), or
– Indirect address: the address in memory of the address in memory of the data to use

Direct addressing Indirect addressing

22 0 ADD 457 35 1 ADD 300

300 1350

457 Operand
1350 Operand

+ +
AC AC

• Effective Address (EA)

– The address, that can be directly used without modification to access an operand for
a computation-type instruction, or as the target address for a branch-type instruction
 PROCESSOR REGISTERS
• A processor has many registers to hold instructions, addresses, data, etc
• Program Counter (PC) that holds the memory address of the next instruction to get
– Since the memory in the Basic Computer only has 4096 locations, the PC only needs 12 bits
• Address Register (AR) In a direct or indirect addressing, the processor needs to keep
track of what locations in memory it is addressing and its is kept in Address Register
(AR).
– The AR is a 12 bit register in the Basic Computer
• Data Register (DR )When an operand is found, using either direct or indirect
addressing, it is placed in the Data Register (DR).
- The processor then uses this value as data for its operation
• Accumulator (AC) it is the general purpose register.
• Temporary Register (TR) used to store intermediate results or other temporary data.
• Input Register (INPR) holds an 8 bit character gotten from an input device
• Output Register (OUTR) holds an 8 bit character to be send to an output device.
– Input devices are considered to send 8 bits of character data to the processor
– The processor can send 8 bits of character data to output devices
 BASIC COMPUTER REGISTERS

Registers in the Basic Computer

11 0
PC
Memory
11 0
4096 x 16
AR
15 0
IR CPU
15 0 15 0
TR DR
7 0 7 0 15 0
OUTR INPR AC

List of BC Registers
DR 16 Data Register Holds memory operand
AR 12 Address Register Holds address for memory
AC 16 Accumulator Processor register
IR 16 Instruction Register Holds instruction code
PC 12 Program Counter Holds address of instruction
TR 16 Temporary Register Holds temporary data
INPR 8 Input Register Holds input character
OUTR 8 Output Register Holds output character
 COMMON BUS SYSTEM
The registers in the Basic Computer are connected using a bus
S2
S1 Bus
S0
Memory unit 7
4096 x 16
Address
Write Read
AR 1

LD INR CLR
PC 2

LD INR CLR

DR 3

LD INR CLR
E
ALU AC 4
LD INR CLR

INPR
IR 5
LD
TR 6
LD INR CLR
OUTR
Clock
LD
16-bit common bus
 COMMON BUS SYSTEM
Read
INPR
Memory Write
4096 x 16
Address E ALU

AC

L I C

L I C L

L I C DR IR L I C

PC TR

AR OUTR LD

L I C

7 1 2 3 4 5 6

16-bit Common Bus

 COMMON BUS SYSTEM
• Three control lines, S2, S1, and S0 control which register the bus selects as its input

S2 S1 S0 Register
0 0 0 x
0 0 1 AR
0 1 0 PC
0 1 1 DR
1 0 0 AC
1 0 1 IR
1 1 0 TR
1 1 1 Memory

• Either one of the registers will have its load signal activated, or the memory will
have its read signal activated
– Will determine where the data from the bus gets loaded
• The 12-bit registers, AR and PC, have 0’s loaded onto the bus in the high order 4 bit
positions
• When the 8-bit register OUTR is loaded from the bus, the data comes from the low
order 8 bits on the bus
 BASIC COMPUTER INSTRUCTIONS
• Basic Computer Instruction Format

Memory-Reference Instructions (OP-code = 000 ~ 110)

15 14 12 11 0
I Opcode Address

Register-Reference Instructions (OP-code = 111, I = 0)

15 12 11 0
0 1 1 1 Register operation

Input-Output Instructions (OP-code =111, I = 1)

15 12 11 0
1 1 1 1 I/O operation

Instructions
BASIC COMPUTER INSTRUCTIONS

Hex Code
Symbol I=0 I=1 Description
AND 0xxx 8xxx AND memory word to AC
ADD 1xxx 9xxx Add memory word to AC
LDA 2xxx Axxx Load AC from memory
STA 3xxx Bxxx Store content of AC into memory
BUN 4xxx Cxxx Branch unconditionally
BSA 5xxx Dxxx Branch and save return address
ISZ 6xxx Exxx Increment and skip if zero

CLA 7800 Clear AC

CLE 7400 Clear E
CMA 7200 Complement AC
CME 7100 Complement E
CIR 7080 Circulate right AC and E
CIL 7040 Circulate left AC and E
INC 7020 Increment AC
SPA 7010 Skip next instr. if AC is positive
SNA 7008 Skip next instr. if AC is negative
SZA 7004 Skip next instr. if AC is zero
SZE 7002 Skip next instr. if E is zero
HLT 7001 Halt computer

INP F800 Input character to AC

OUT F400 Output character from AC
SKI F200 Skip on input flag
SKO F100 Skip on output flag
ION F080 Interrupt on
IOF F040 Interrupt off
 INSTRUCTION SET COMPLETENESS
A computer should have a set of instructions so that the user can construct
machine language programs to evaluate any function that is known to be computable.
Instruction Types
Functional Instructions
- Arithmetic, logic, and shift instructions
- ADD, CMA, INC, CIR, CIL, AND, CLA
Transfer Instructions
- Data transfers between the main memory
and the processor registers
- LDA, STA
Control Instructions
- Program sequencing and control
- BUN, BSA, ISZ
Input/Output Instructions
- Input and output
- INP, OUT

Instructions
 INSTRUCTION CYCLE

• In Basic Computer, a machine instruction is executed in the following

cycle:
1. Fetch an instruction from memory
2. Decode the instruction
3. Read the effective address from memory if the instruction has an
indirect address
4. Execute the instruction

• After an instruction is executed, the cycle starts again at step 1, for the
next instruction

• Note: Every different processor has its own (different)

instruction cycle
DETERMINE THE TYPE OF INSTRUCTION
Start
SC 

T0
AR  PC
T1
IR  M[AR], PC  PC + 1
T2
Decode Opcode in IR(12-14),
AR  IR(0-11), I  IR(15)

(Register or I/O) = 1 = 0 (Memory-reference)

D7

(I/O) = 1 = 0 (register) (indirect) = 1 = 0 (direct)

I I

T3 T3 T3 T3
Execute Execute AR  M[AR] Nothing
input-output register-reference
instruction instruction
SC  0 SC  0 Execute T4
memory-reference
instruction
SC  0

D'7IT3: AR M[AR]
D'7I'T3: Nothing
D7I'T3: Execute a register-reference instr.
D7IT3: Execute an input-output instr.
 REGISTER REFERENCE INSTRUCTIONS
Register Reference Instructions are identified when
- D7 = 1, I = 0
- Register Ref. Instr. is specified in b0 ~ b11 of IR
- Execution starts with timing signal T3

r = D7 IT3 => Register Reference Instruction

Bi = IR(i) , i=0,1,2,...,11

r: SC  0
CLA rB11: AC  0
CLE rB10: E0
CMA rB9: AC  AC’
CME rB8: E  E’
CIR rB7: AC  shr AC, AC(15)  E, E  AC(0)
CIL rB6: AC  shl AC, AC(0)  E, E  AC(15)
INC rB5: AC  AC + 1
SPA rB4: if (AC(15) = 0) then (PC  PC+1)
SNA rB3: if (AC(15) = 1) then (PC  PC+1)
SZA rB2: if (AC = 0) then (PC  PC+1)
SZE rB1: if (E = 0) then (PC  PC+1)
HLT rB0: S  0 (S is a start-stop flip-flop)
 MEMORY REFERENCE INSTRUCTIONS

Operation
Symbol Symbolic Description
Decoder
AND D0 AC  AC  M[AR]
ADD D1 AC  AC + M[AR], E  Cout
LDA D2 AC  M[AR]
STA D3 M[AR]  AC
BUN D4 PC  AR
BSA D5 M[AR]  PC, PC  AR + 1
ISZ D6 M[AR]  M[AR] + 1, if M[AR] + 1 = 0 then PC  PC+1

- The effective address of the instruction is in AR and was placed there during timing signal
T2 when I = 0, or during timing signal T3 when I = 1
- Memory cycle is assumed to be short enough to complete in a CPU cycle
- The execution of MR instruction starts with T4
AND to AC
D0T4: DR  M[AR] Read operand
D0T5: AC  AC  DR, SC  0 AND with AC
ADD to AC
D1T4: DR  M[AR] Read operand
D1T5: AC  AC + DR, E  Cout, SC  0 Add to AC and store carry in E
 MEMORY REFERENCE INSTRUCTIONS
LDA: Load to AC
D2T4: DR  M[AR]
D2T5: AC  DR, SC  0
STA: Store AC
D3T4: M[AR]  AC, SC  0
BUN: Branch Unconditionally
D4T4: PC  AR, SC  0
BSA: Branch and Save Return Address
M[AR]  PC, PC  AR + 1

Memory, PC, AR at time T4 Memory, PC after execution

20 0 BSA 135 20 0 BSA 135
PC = 21 Next instruction 21 Next instruction

AR = 135 135 21
136 Subroutine PC = 136 Subroutine

1 BUN 135 1 BUN 135

Memory Memory
 MEMORY REFERENCE INSTRUCTIONS

BSA:
D5T4: M[AR]  PC, AR  AR + 1
D5T5: PC  AR, SC  0

ISZ: Increment and Skip-if-Zero

D6T4: DR  M[AR]
D6T5: DR  DR + 1
D6T4: M[AR]  DR, if (DR = 0) then (PC  PC + 1), SC  0
FLOWCHART FOR MEMORY REFERENCE INSTRUCTIONS

Memory-reference instruction

AND ADD LDA STA

D0 T 4 D1 T 4 D2 T 4 D 3T 4
DR  M[AR] DR  M[AR] DR  M[AR] M[AR]  AC
SC  0

D0 T 5 D1 T 5 D2 T 5
AC  AC  DR AC  AC + DR AC  DR
SC  0 E  Cout SC  0
SC  0

BUN BSA ISZ

D4 T 4 D5 T 4 D6 T 4
PC  AR M[AR]  PC DR  M[AR]
SC  0 AR  AR + 1

D5 T 5 D6 T 5

PC  AR DR  DR + 1
SC  0
D6 T 6
M[AR]  DR
If (DR = 0)
then (PC  PC + 1)
SC  0
 INPUT-OUTPUT AND INTERRUPT

A Terminal with a keyboard and a Printer

• Input-Output Configuration
Input-output Serial Computer
terminal communication registers and
interface
flip-flops
Receiver
Printer interface OUTR FGO

AC

Transmitter
Keyboard interface INPR FGI
INPR Input register - 8 bits
OUTR Output register - 8 bits Serial Communications Path
FGI Input flag - 1 bit Parallel Communications Path
FGO Output flag - 1 bit
IEN Interrupt enable - 1 bit
 INPUT-OUTPUT AND INTERRUPT

• - The terminal sends and receives serial information

• - The serial info. from the keyboard is shifted into INPR

- The serial info. for the printer is stored in the OUTR

• - INPR and OUTR communicate with the terminal

• serially and with the AC in parallel.

• - The flags are needed to synchronize the timing

• difference between I/O device and the computer
PROGRAM CONTROLLED DATA TRANSFER
-- CPU -- -- I/O Device --
/* Input */ /* Initially FGI = 0 */ loop: If FGI = 1 goto loop
loop: If FGI = 0 goto loop INPR  new data, FGI  1
AC  INPR, FGI  0

/* Output */ /* Initially FGO = 1 */ loop: If FGO = 1 goto loop

loop: If FGO = 0 goto loop consume OUTR, FGO  1
OUTR  AC, FGO  0

FGI=0 FGO=1
Start Input Start Output

FGI  0
AC  Data
yes yes
FGI=0
FGO=0
no
no
AC  INPR
OUTR  AC

yes More FGO  0

Character
yes More
no Character
END no
END
 INPUT-OUTPUT INSTRUCTIONS

D7IT3 = p
IR(i) = Bi, i = 6, …, 11

p: SC  0 Clear SC
INP pB11: AC(0-7)  INPR, FGI  0 Input char. to AC
OUT pB10: OUTR  AC(0-7), FGO  0 Output char. from AC
SKI pB9: if(FGI = 1) then (PC  PC + 1) Skip on input flag
SKO pB8: if(FGO = 1) then (PC  PC + 1) Skip on output flag
ION pB7: IEN  1 Interrupt enable on
IOF pB6: IEN  0 Interrupt enable off
 The Central Processing Unit (CPU)
• The CPU has four main components:
1. The Control Unit (along with the IR) interprets the machine language instruction
and issues the control signals to make the CPU execute that instruction.
2. The ALU (Arithmetic Logic Unit) that does the arithmetic and logic.
3. The Register Set (Register File) that stores temporary results related to the
computations. There are also Special Purpose Registers used by the Control
Unit.

4. An internal bus structure for communication.

The function of the control unit is to decode the binary machine word in the
IR (Instruction Register) and issue appropriate control signals. These cause the
computer to execute its program.
 Two Options for the Control Unit
Control unit (CU) of a processor translates from machine instructions to the
control signals for the micro operations that implement them.
Control units are implemented in one of two ways:-
• Hardwired Control
CU is made up of sequential and combinational circuits to generate the control
signals.
Or
The control signals are generated as an output of a set of basic logic gates, the
input of which derives from the binary bits in the Instruction Register.
• Microprogrammed Control
A control memory on the processor contains microprograms that activate the
necessary control signals.
Or
The control signals are generated by a microprogram that is stored in Control
Read Only Memory.
The microcontroller fetches a control word from the CROM and places it into the
MBR, from which control signals are emitted.
Hardwired Controller Block Diagram
 Controller specification for the Fetch Sequence
• Address of next instruction is in PC
• Content of PC loaded into MAR
• Address (MAR) is placed on address bus
• Control unit issues READ command
• Result (data from memory) appears on data bus
• Data from data bus copied into MDR
• PC incremented by 1 (in parallel with data fetch from memory)
• Data (instruction) moved from MDR to IR
• MDR is now free for further data fetches
 TIMING AND CONTROL

Control unit of Basic Computer

Instruction register (IR)

15 14 13 12 11 - 0 Other inputs

3x8
decoder
7 6543 210
D0
I Combinational
D7 Control Control
logic signals

T15
T0

15 14 . . . . 2 1 0
4 x 16
decoder

4-bit Increment (INR)

sequence Clear (CLR)
counter
(SC) Clock
 Methods for systematic design of hardwired control
logic

• Sequence counter method: To design controller of moderate

complexity
• Delay element method: Depends on the use of clocked delay
elements for generating the sequence of control signals
• State table method: Employs the algorithmic approach to sequential
circuit design using classical state table method
• PLA method:
 Sequence counter method

• Step 1: Identify the distinct phases in the flowchart. Employ log p number
of flip flops to handle p number distinct phases
Start R 1

Modulo –K
End S counter
Reset
0

Clock

Reset

…..
Step 2: Identify the maximum number of distinct steps, k, in each of
the phases .Employ a mod k counter to generate control signals for I/k Decoder
each of the k steps
Step 3 : design a combinational logic circuit to generate the
sequence of control signals to control the micro operations of each
phase ……

c1c2 ck
 Delay element method

Control unit based on delay element method for

the fetch cycle Ci,j

Begin
C01: MAR PC; (d1=t1-t0)

t0 Delay block Di
D1
C02: MDR M(MAR),
t1
c03: PC PC+1 ; (d2=t2-t1) Ci+1,j’
D2
t2
C04: IR MDR; (d3=t3-t2)
D3
t3 C05: F 0; E 1; (d4=t4-t3)

D4
t4

Execute
 State table method

• The state Si (i=1,2…) has been marked above

each block of the flowchart.
• This the state of the controller which
generates the control signals to control the
micro operations in the data path
Ij C’i

Combinational logic

FFs
 Hard-wired Control Unit
Advantages :
1. Minimizes the average number of clock cycles needed per instruction
2. High efficiency in terms of operation speed
3. Occupies a relatively small area (typically 10%) of the CPU chip area
4. Is to minimize cost of the circuit
Disadvantages :
1. Complex sequencing & micro-operation logic
2. Difficult to design and test
3. Inflexible design
4. Large design turn around time for complex design
5. Difficult to add new instructions
 Micro programmed Control
Micro programmed Control : A control unit whose binary control variable is
stored in the memory (Control Memory) is called as micro programmed control.
Micro programme Consists of microinstructions.
Microinstruction : - Contains a control word and a sequencing word
Control Word - All the control information required for one clock cycle
Sequencing Word - Information needed to decide the next microinstruction
address.
- Vocabulary to write a microprogram.
Control Memory(Control Storage: CS)
- Storage in the microprogrammed control unit to store the microprogram
Writeable Control Memory(Writeable Control Storage:WCS)
- CS whose contents can be modified
-> Allows the microprogram can be changed
-> Instruction set can be changed or modified
Dynamic Microprogramming
- Computer system whose control unit is implemented with a microprogram in
WCS
- Microprogram can be changed by a systems programmer or a user
 Micro programmed Control
The concept of micro programmed control, employ the following steps:
1. Any instruction to be executed on a CPU can be broken down into a set of
sequential micro operations – each specifying a RTL operation on the data path.
The set of micro operations to be executed on the RTL components at any time
step is referred as microinstructions.

2. The sequence of control signals necessary to execute the sequential

microinstructions stored in ROM called control ROM

3. To implement an instruction on the data path , the control signals stored in the
ROM can be accessed

4. The control signals read from the ROM are used to control the micro operations
associated with a microinstruction to be executed at any time step

5. The address of the next micro instruction is generated

6. The steps 3,4 and 5 are repeated till the set of sequential microinstructions
associated with the instruction is executed
 Micro programmed Control

Starting
IR address
generator

Clock P C

Control
store CW

Figure 7.16. Basic organization of a microprogrammed control unit.

Micro programmed Control
Control
inputs Status signals from datapath

Next-address
generator

Sequencer

Control address
register

Control address

Address

Control
memory
(R OM)

Data

Control data register

(optional)

Microinstruction

Next-address Control Control signals

information outputs to datapath
 Micro programmed Control Unit
Advantages :
1. Control Unit Design Becomes Easier.
2. Control Function are implemented in software
3. More Flexible
Disadvantages :
1. Slow as compared to Hardwired
2. Costly due to the control memory
 Difference Between Hardwired
& Micro programmed
Characteristics Hardwired Microprogrammed

Speed Fast Slow

Implementation Hardware Software

Flexibility No Flexible More Flexible

Ability to handle large/complex Instructions Somewhat difficult Easier

Design Process Difficult for more Operations Easy

Memory No Memory Used Control Memory Used

Chip Area Efficiency Uses Least Area Uses More Area

 Microinstructions
• A straightforward way to structure microinstructions is to assign
one bit position to each control signal.
• However, this is very inefficient.
• The length can be reduced: most signals are not needed
simultaneously, and many signals are mutually exclusive.
• All mutually exclusive signals are placed in the same group in
binary coding i.e Grouping Technique.
• Grouping Technique: it is used to reduce the number of bits in
the microinstruction .
• The micro-programmed control unit can be classified into two
types based on the type of Control Word stored in the Control
Memory, viz., Horizontal micro-programmed control unit and
Vertical micro-programmed control unit.

46 Control signals can be grouped in 7 different Groups.

 Grouping Technique
• Grouping Technique: There are two techniques used for
grouping
1. Horizontal organization : Each bit directly controls each micro-operation
or each control point i.e., 1 bit/CS. Here ‘n’ control signals require n bit
encoding.
Horizontal implies a long microinstruction word
Advantages: Can control a variety of components operating in parallel.
--> Advantage of efficient hardware utilization
Disadvantages: Control word bits are not fully utilized
--> CS becomes large --> Costly
2. Vertical organization : A microinstruction format that is not horizontal
Vertical implies a short microinstruction word . The control signals are
represented in the encoded binary format. Here ‘n’ control signals require
log2n bit encoding.
Encoded Microinstruction fields
--> Needs decoding circuits for one or two levels of decoding
Difference between Horizontal and Vertical micro-programmed Control Unit:

S.NO Horizontal µ-programmed CU Vertical µ-programmed CU

1 It supports longer control word. It supports shorter control word.
It allows a higher degree of
parallelism. If degree is n, then n It allows a low degree of parallelism i.e.,
2
Control Signals are enabled at a the degree of parallelism is either 0 or 1.
time.
Additional hardware in the form of
3 No additional hardware is required. decoders is required to generate control
signals.
It is faster than a Vertical micro- It is slower than a Horizontal micro-
4
programmed control unit. programmed control unit.

A horizontal micro-programmed A vertical micro-programmed control unit

control unit uses horizontal micro- uses vertical micro-instruction, where a
5 instruction, where every bit in the code is used for each action to be
control field attaches to a control performed and the decoder translates this
line. code into individual control signals.
 RISC Instructions
A microprocessor is a processing unit on a single chip. It is an integrated circuit that
performs the core functions of a computer CPU. It is a multipurpose programmable
silicon chip constructed using Metal Oxide Semiconductor (MOS) technology which
is clock-driven and register-based. It accepts binary data as input and provides output
after processing it as per the specification of instructions stored in the memory. These
microprocessors are capable of processing 128 bits at a time at the speed of one
billion instructions per second.
Characteristics of a microprocessor:
Instruction Set –
The set of complete instructions that the microprocessor executes is termed the
instruction set.
Word Length –
The number of bits processed in a single instruction is called word length or word
size. Greater the word size, the larger the processing power of the CPU.
System Clock Speed –
Clock speed determines how fast a single instruction can be executed in a processor.
The microprocessor’s pace is controlled by the System Clock. Clock speeds are
generally measured in millions of cycles per second (MHz) and thousand million
cycles per second (GHz). Clock speed is considered to be a very important aspect of
predicting the performance of a processor.
 RISC Instructions
Classification of Microprocessors:
Besides the classification based on the word length, the classification is also based on
the architecture i.e. Instruction Set of the microprocessor. These are categorized into
RISC and CISC.
RISC:
It stands for Reduced Instruction Set Computer. It is a type of microprocessor
architecture that uses a small set of instructions of uniform length. These are simple
instructions that are generally executed in one clock cycle. RISC chips are relatively
simple to design and inexpensive. The setback of this design is that the computer has
to repeatedly perform simple operations to execute a larger program having a large
number of processing operations.
Examples: SPARC, POWER PC, etc.
CISC:
It stands for Complex Instruction Set Computer. These processors offer the users,
hundreds of instructions of variable sizes. CISC architecture includes a complete set
of special-purpose circuits that carry out these instructions at a very high speed.
These instructions interact with memory by using complex addressing modes. CISC
processors reduce the program size and hence lesser number of memory cycles are
required to execute the programs. This increases the overall speed of execution.
Examples: Intel architecture, AMD
 RISC Instructions
Advantages of RISC Processor
•The RISC processor's performance is better due to the simple and
limited number of the instruction set.
•It requires several transistors that make it cheaper to design.
•RISC allows the instruction to use free space on a microprocessor
because of its simplicity.
•RISC processor is simpler than a CISC processor because of its
simple and quick design, and it can complete its work in one clock
cycle.
Disadvantages of RISC Processor
•The RISC processor's performance may vary according to the
code executed because subsequent instructions may depend on the
previous instruction for their execution in a cycle.
•Programmers and compilers often use complex instructions.
•RISC processors require very fast memory to save various
instructions that require a large collection of cache memory to
respond to the instruction in a short time.
 RISC Instructions

RISC Architecture CISC Architecture

 Difference between the RISC and CISC Processors
S.No RISC CISC
1 It is a Reduced Instruction Set Computer. It is a Complex Instruction Set Computer.
It emphasizes on software to optimize the It emphasizes on hardware to optimize the instruction
2
instruction set. set.
It is a hard wired unit of programming in the RISC
3 Microprogramming unit in CISC Processor.
Processor.
It requires multiple register sets to store the
4 It requires a single register set to store the instruction.
instruction.
5 RISC has simple decoding of instruction. CISC has complex decoding of instruction.

6 Uses of the pipeline are simple in RISC. Uses of the pipeline are difficult in CISC.

It uses a limited number of instruction that It uses a large number of instruction that requires more
7
requires less time to execute the instructions. time to execute the instructions.
It uses LOAD and STORE that are independent
It uses LOAD and STORE instruction in the memory-
8 instructions in the register-to-register a program's
to-memory interaction of a program.
interaction.
9 RISC has more transistors on memory registers. CISC has transistors to store complex instructions.

10 The execution time of RISC is very short. The execution time of CISC is longer.
RISC architecture can be used with high-end
CISC architecture can be used with low-end
11 applications like telecommunication, image
applications like home automation, security system, etc.
processing, video processing, etc.
12 It has fixed format instruction. It has variable format instruction.
The program written for RISC architecture needs Program written for CISC architecture tends to take less
13
to take more space in memory. space in memory.
 Pipelining
To improve the performance of a CPU we have two options:
1) Improve the hardware by introducing faster circuits.
2) Arrange the hardware such that more than one operation can be performed at
the same time.
Since there is a limit on the speed of hardware and the cost of faster circuits is
quite high, we have to adopt the 2nd option.

Pipelining is a process of arrangement of hardware elements of the CPU such that

its overall performance is increased. Simultaneous execution of more than one
instruction takes place in a pipelined processor.
Or
Pipelining refers to a technique of decomposing a sequential process into sub-
operations, with each sub-operation being executed in a dedicated segment that
operates concurrently with all other segments.

The most important characteristic of a pipeline technique is that several

computations can be in progress in distinct segments at the same time. The
overlapping of computation is made possible by associating a register with each
segment in the pipeline. The registers provide isolation between each segment so
that each can operate on distinct data simultaneously
 Pipelining
Design of a basic pipeline
•In a pipelined processor, a pipeline has two ends, the input end and the output
end. Between these ends, there are multiple stages/segments such that the output of
one stage is connected to the input of the next stage and each stage performs a
specific operation.
•Interface registers are used to hold the intermediate output between two stages.
These interface registers are also called latch or buffer.
•All the stages in the pipeline along with the interface registers are controlled by a
common clock.
Non-overlapped execution:
Stage / Cycle 1 2 3 4 5 6 7 8
S1 I1 I2
S2 I1 I2
S3 I1 I2
S4 I1 I2
Total time = 8 Cycle
•Stage / Cycle 1 2 3 4 5
S1 I 1 I2
S2 I1 I2
S3 I1 I2
S4 I1 I2
Total time = 5 Cycle
 Pipelining
Pipeline Stages RISC processor has 5 stage instruction pipeline to execute all the
instructions in the RISC instruction set. Following are the 5 stages of the RISC
pipeline with their respective operations:
Stage 1 (Instruction Fetch) In this stage the CPU reads instructions from the
address in the memory whose value is present in the program counter.
Stage 2 (Instruction Decode) In this stage, instruction is decoded and the register
file is accessed to get the values from the registers used in the instruction.
Stage 3 (Instruction Execute) In this stage, ALU operations are performed.
Stage 4 (Memory Access) In this stage, memory operands are read and written
from/to the memory that is present in the instruction.
Stage 5 (Write Back) In this stage, computed/fetched value is written back to the
register present in the instructions.
 Pipelining
Performance of a pipelined processor
Consider a ‘k’ segment pipeline with
Clock cycle time as ‘Tp’.
Let there be ‘n’ tasks to be completed in the pipelined processor.

Now, the first instruction is going to take ‘k’ cycles to come out of the pipeline
but the other ‘n – 1’ instructions will take only ‘1’ cycle each,
i.e, a total of ‘n – 1’ cycles.
So, time taken to execute ‘n’ instructions in a pipelined processor:
ETpipeline = k + n – 1 cycles = (k + n – 1) Tp

In the same case, for a non-pipelined processor, the execution time of ‘n’
instructions will be:
ETnon-pipeline = n * k * Tp
 Pipelining
So, speedup (S) of the pipelined processor over the non-pipelined processor, when
‘n’ tasks are executed on the same processor is:
S = Performance of pipelined processor / Performance of non-pipelined
processor
As the performance of a processor is inversely proportional to the execution time,
we have,
S = ETnon-pipeline / Etpipeline
S = [n * k * Tp] / [(k + n – 1) * Tp]
S = [n * k] / [k + n – 1]When the number of tasks ‘n’ is significantly larger than k,
that is, n >> k
S = n * k / n S = kwhere ‘k’ are the number of stages in the pipeline.

Efficiency = Given speed up / Max speed up = S / Smax We know that Smax = k

So, Efficiency = S / k

Throughput = Number of instructions / Total time to complete the instructions

So, Throughput = n / (k + n – 1) * Tp