Micrprocessor Notes 2023
Micrprocessor Notes 2023
Intel 8085
Intel 8085 is an 8-bit, NMOS microprocessor designed by Intel in 1977.
Intel 8085 is used in mobile phones, microwave ovens, washing machines etc.
The below diagram shows the block diagram of Intel 8085:
ALU
The Arithmetic and Logic Unit, ALU performs the arithmetic and logical operations:
o Addition
o Subtraction
o Logical AND
o Logical OR
o Logical EXCLUSIVE OR
o Complement (Logical NOT)
o Increment (add 1)
o Decrement (subtract 1)
o Left shift, Rotate left, Rotate right
o Clear, etc.
o It is used to generate timing and control signals which are necessary for the
execution of instructions.
o It is used to control data flow between CPU and peripherals (including memory).
o It is used to provide status, control and timing signals which are required for the
operation of memory and I/O devices.
o It is used to control the entire operations of the microprocessor and peripherals
connected to it.
Thus we can see that the control unit of the CPU acts as the brain of the computer
system.
Registers
Registers are used for temporary storage and manipulation of data and instructions by
the microprocessor. Data remain in the registers till they are sent to the I/O devices or
memory. Intel 8085 microprocessor has the following registers:
In addition to the above mentioned registers the 8085 microprocessor contains a set of
five flip-flops which serve as flags (or status flags).
A flag is a flip-flop which indicates some conditions which arises after the execution of
an arithmetic or logical instruction.
If a flip-flop for a particular flag is set, then it indicates 1. When it is reset, it indicates 0.
Pin Configuration
Fig: Pin diagram of Intel 8085 microprocessor
o A8 ? A15 (Output): These are address bus and are used for the most significant
bits of the memory address or 8-bits of I/O address.
o AD0 ? AD7 (Input/output): These are time multiplexed address/data bus i.e.
they serve dual purpose. They are used for the least significant 8 bits of the
memory address or I/O address during the first cycle. Again they are used for
data during 2nd and 3rd clock cycles.
Control and Status Signals
o ALE (Output): ALE stands for Address Latch Enable signal. ALE goes high during
first clock cycle of a machine cycle and enables the lower 8-bits of the address to
be latched either into the memory or external latch.
o IO/M (Output): It is a status signal which distinguishes whether the address is
for memory or I/O device.
o S0, S1 (Output): These are status signals sent by the microprocessors to
distinguish the various types of operation given in table below:
S1 S0 Operations
0 0 HALT
0 1 WRITE
1 0 READ
1 1 FETCH
o HOLD (INPUT): HOLD indicates that another device is requesting for the use of
the address and data bus.
o HLDA (OUTPUT): HLDA is a signal for HOLD acknowledgement which indicates
that the HOLD request has been received. After the removal of this request the
HLDA goes low.
o INTR (Input): INTR is an Interrupt Request Signal. Among interrupts it has the
lowest priority. The INTR is enabled or disabled by software.
o INTA (Output): INTA is an interrupt acknowledgement sent by the
microprocessor after INTR is received.
o RST 5.5, 6.5, 7.5 and TRAP (Inputs): These all are interrupts. When any
interrupt is recognized the next instruction is executed from a fixed location in
the memory as given below:
TRAP 0024
RST 7.5, RST 6.5 and RST 5.5 are the restart interrupts which cause an internal restart to
be automatically inserted.
The TRAP has the highest priority among interrupts. The order of priority of interrupts is
as follows:
Reset Signals
o RESET IN (Input): It resets the program counter (PC) to 0. It also resets interrupt
enable and HLDA flip-flops. The CPU is held in reset condition till RESET is not
applied.
o RESET OUT (Output): RESET OUT indicates that the CPU is being reset.
Clock Signals
o SID (Input): SID is data line for serial input. The data on this line is loaded into
the seventh bit of the accumulator when RIM instruction is executed.
o SOD (Output): SOD is a data line for serial output. The seventh bit of the
accumulator is output on SOD line when SIM instruction is executed.
Power Supply
8085 Instructions
An instruction of computer is a command given to the computer to perform a specified
operation on given data. Some instructions of Intel 8085 microprocessor are: MOV, MVI,
LDA, STA, ADD, SUB, RAL, INR, MVI, etc.
The 1st part of an instruction which specifies the task to be performed by the computer
is called Opcode.
The 2nd part of the instruction is the data to be operated on, and it is called Operand.
The Operand (or data) given in the instruction may be in various forms such as 8-bit or
16-bit data, 8-bit or 16-bit address, internal registers or a register or memory location.
According to the word size, the Intel 8085 instructions are classified into the
following three types:
All the above two examples are only one byte long. All one-byte instructions contain
information regarding operands in the opcode itself.
2. Two-byte instruction: In a two byte instruction the first byte of the instruction is its
opcode and the second byte is either data or address.
Example:
The first byte 06 is the opcode for MVI B and second byte 05 is the data which is to be
moved to register B.
3. Three-byte instruction: The first byte of the instruction is its opcode and the second
and third bytes are either 16-bit data or 16-bit address.
Example:
The first byte 21 is the opcode for the instruction LXI H. The second 00 is 8 LSBs of the
data (2400H), which is loaded into register L. The third byte 24 is 8 MSBs of the data
(2400H), which is loaded into register H.
Instruction Cycle
The time required to fetch an instruction and necessary data from memory and to
execute it, is called an instruction cycle. Or the total time required to execute an
instruction is given by:
IC = FC + EC
Where,
IC = Instruction Cycle
FC = Fetch Cycle
EC = Execute Cycle
In the beginning of the fetch cycle, the content of the program counter (PC), which is
the address of the memory location where opcode is available, is sent to the memory.
The memory puts the opcode on the data bus so as to transfer it to the CPU.
The whole operation of fetching an opcode takes three clock cycles. A slow memory
may take more time.
The opcode fetched from the memory goes to the data register, DR and then to
instruction register, IR. From the IR it goes to the decoder circuitry which decodes the
instruction. Decoder circuitry is within the microprocessor.
In some situations, an execute cycle may involve one or more read or write cycles or
both.
Read Cycle: If an instruction contains data or operand address which are in the
memory, the CPU has to perform some read operations to get the desired data. In case
of a read cycle the instruction received from the memory are data or operand address
instead of an opcode.
Write Cycle: In write cycle data are sent from the CPU to the memory or an output
device.
The necessary steps carried out to perform the operation of accessing either memory or
input output device, constitute a machine cycle. In other words, necessary steps carried
out to perform a fetch, a read or a write operation constitutes a machine cycle.
One sub-division of an operation performed in one clock cycle is called a state or T-
state. In short, one clock cycle of the system clock is referred to as a state.
Timing Diagram
The necessary steps carried out in a machine cycle can be represented graphically. Such
a graphical representation is called timing diagram. The timing diagram for opcode
fetch, memory read, memory write, I/O read and I/O write will be discussed below:
Timing Diagram for Opcode Fetch Cycle:
Timing Diagram for Memory Read
Timing Diagram for Memory Write
IO/M (low active): A high or 1 on this signal indicates I/O operation while a low or 0
indicates memory operation.
The below table, shows the status of different control signal for different operation: