MIDAS  CPD Digital Design  12 Week Course


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2021 Sept  Dec
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Finite State Machines 1 (FSM1)
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Richard Gahan

richard.gahan@tudublin.ie

September 23, 2021

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Contents

1 Finite State Machines - FSM 2

1.1 Denition of FSM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2 Bubble Arrow and Flowchart Depiction of FSM . . . . . . . . . . . . . . . 3
1.3 Abstract Models of FSMs . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.3.1 Mealy Model of FSM . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.3.2 Moore Model of FSM . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.3.3 FSMs  General Output Structure . . . . . . . . . . . . . . . . . . 6
1.4 Flowchart Models of FSMs . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.5 Applying FSM techniques to common Digital Design problems . . . . . . 9
1.5.1 Design of a 2 bit up-counter using FSM techniques . . . . . . . . . 9
State assignment and Logic Derivation . . . . . . . . . . . . . . . . 11
1.5.2 Design of a Sequence Detect using FSM techniques . . . . . . . . . 14
State Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Q0 Flip-Flop Logic Derivation . . . . . . . . . . . . . . . . . . . . . 17
State Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Logic Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.5.3 State Assignment to Flip-Flop values . . . . . . . . . . . . . . . . . 19
Binary State Assignment to Flip-Flop values . . . . . . . . . . . . 19
One-Hot State Assignment to Flip-Flop values . . . . . . . . . . . 19
Grey code State Assignment to Flip-Flop values . . . . . . . . . . . 19
1.5.4 Design of a Sequence Detect 2 bits at a time . . . . . . . . . . . . . 20
1.6 Reset Methods of Digital Circuits . . . . . . . . . . . . . . . . . . . . . . . 25
1.7 TestQuestions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
1.7.1 TestQuestion1 3 bit Counter . . . . . . . . . . . . . . . . . . . . . 26
1.7.2 TestQuestion2 UART Receive . . . . . . . . . . . . . . . . . . . . 27
1.7.3 TestQuestion3 Detecting Two Sequences at the same time . . . . 28
1.7.4 TestQuestion4 Extracting VLAN Tag from Ethernet Frame . . . . 29
1.7.5 TestQuestion5 Writing to Conguration Register . . . . . . . . . 30
1.7.6 TestQuestion6 UART Transmitter . . . . . . . . . . . . . . . . . . 32

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Section 1

Finite State Machines - FSM

1.1 Denition of FSM

FSM stands for Finite State Machine. An FSM is a model of behaviour composed of:
ˆ A nite number of states
ˆ Transitions between those states
ˆ And actions i.e. outputs

A nite state machine is an abstract model of a machine with a primitive internal mem-
ory 1 .

Many dierent styles are used to document the behaviour of FSMs  in fact nearly every
company has their own method! But clarity is a necessity of all of them. We shall look at
a two dierent documentation styles:
ˆ Flowcharts.
ˆ Bubble Arrow diagrams.
We shall use owcharts to depict FSMs as it is simpler to use and is less error prone.

1
https://en.wikipedia.org/wiki/Finite-state_machine

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1.2 Bubble Arrow and Flowchart Depiction of FSM

Figure 1.1: Bubble Arrow and Flowchart Depiction of FSMs

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1.3 Abstract Models of FSMs

A generalised model of the structure of FSMs as implemented in digital logic is shown in
gure 1.2.

Figure 1.2: General FSM Model

This diagram shows that there are state ip-ops whose output is fed back and combined
with the inputs to generate the next state of the ip-ops. In this way the FSM can
remember what has occurred previously and transition to a new state based on current
state and input values.
The outputs can be generated from a combination of input signals, the current state and
output logic and sequential elements.

Note the names of the various pieces of the FSM:

ˆ Next State Decode Logic

ˆ Current State Logic (i.e. Flip-Flops typically)

ˆ Output Decode Logic

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1.3.1 Mealy Model of FSM

In the Digital Design literature FSMs are sometimes divided into Mealy and Moore Ma-
chines. These are just sub-groups of the generalised model of FSMs presented above.
These terms developed in the early development of FSMs and are mentioned in most
digital design textbooks and so are important to be aware of.

Figure 1.3: Mealy FSM Model

The Mealy machine is distinguished by its outputs being generated from its current state
and its inputs.

1.3.2 Moore Model of FSM

The Moore machine is distinguished by its outputs being generated from its current state
only - the inputs are not brought into the output decode logic. Generally Engineers use
mealy machines to design synchronous systems and do not restrict themselves to moore
machines.

Figure 1.4: Moore FSM Model

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1.3.3 FSMs  General Output Structure

The outputs of FSMs can come directly from:

1. The state ip-ops (Moore outputs),

2. Combinations of the inputs and the current state of the FSM (Mealy outputs) or

3. Registering2 a Mealy or Moore generated signal and using that as an output signal.

These 3 ways of generating outputs are shown on gure 1.5.

Figure 1.5: Outputs FSM Model

2
i.e. Putting it through a ip-op

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1.4 Flowchart Models of FSMs

The elements we use to draw owcharts of FSMs are shown in gure 1.6.

Figure 1.6: FSM Elements

Flowcharts use 3 basic elements to describe the behaviour of FSMs. These are
1. State Descriptors  usually shown as rectangular boxes. They show the STATE of
the FSM.
2. Decision diamonds. These show the questions asked and decisions made in moving
from one state to the next.
3. Output generation bubbles. These show the outputs generated and when and how
they occur.
A state Descriptor looks like a rectangular box with the name of the state written inside.
The name of the state should be meaningful to what the state represents. In a digital
system the state is implemented by assigning a unique value for the state to the state
ip-ops. This is called State Assignment.
The state assignment value represents the state of the FSM and in this case the state
called StateName is represented by the two ip-ops having values Q1=1 and Q0=0.

A decision diamond looks like a diamond with an input line (on top) and two output lines
(both sides).
In this example the signal attn(H) is being evaluated. If it is a 1 the left option is taken,
else the right option. The arrow into the diamond shows where the ow has come from.
The (H) sux means that the signal is asserted high. This means that when attn is "on"
it is high. Dierent norms may be used to confer this meaning. attn(H) or attH or just
attn where the default is that a signal is asserted high. If attn is asserted low then it is
written as attn(L) or attnL where the capital L indicates asserted low.

An output generation bubble looks like a rectangle with rounded corners. The output can
be generated from the state and inputs using combinational logic © or the output is
registered i.e. from a ip-op ®. All outputs must have either © or ® preceding them.

Note:
ˆ A registered output will assert on the next clock tick after the assignment is made
in the FSM owchart

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ˆ A combinational output will occur on the current clock tick in which the assignment
is made on the owchart.

The rst output here shows the combinational signal out1(H) being assigned the value 1.
The second output shows the registered signal out2(H) being assigned the value 1.

With these basic elements complex Finite State Machines may be drawn and implemented.
See Figure 1.7.

Figure 1.7: FSM Example1

Do TestQuestion in section 1.7.1 on page 26 now.

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1.5 Applying FSM techniques to common Digital Design prob-

lems
1.5.1 Design of a 2 bit up-counter using FSM techniques
Consider the design a synchronous digital circuit which has 2 outputs which take on the
values given in the sequence below i.e. it is a counter. When it gets to 11 it should return
to 00 and start again.

00 -> 01 -> 10 -> 11

Let the outputs be called CNT[1:0] and they should be glitchless. The circuit has a resetH
input  which when asserted asynchronously resets the digital circuit to a known initial
state
Draw a nite state machine which implements this digital system. From the FSM draw
out the logic for the solution using D-type ip ops and combinational logic elements only.
Do not minimize any of the logic.
A block diagram is shown below.

Figure 1.8: 2 Bit Up Counter

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Solution
Since we have only a 2 bit counter  we have only 4 states. In this case then we only
need two bits to represent the 4 states AND the state ip ops can be used as the output
CNT[1:0]. We let the two ip ops be called Q1 and Q0. We can let Q1 represent CNT[1]
and Q0 represent CNT[0]
We can draw a owchart of the solution as follows

Figure 1.9: 2 Bit Up Counter FSM Flowchart

State0  We assume for now that the FSM is put into this initial state due to the assertion
of the resetH signal. This is not shown explicitly in the FSM owchart here. We needed
4 states to solve the problem. This means that 2 ip ops are needed  since 2 ip ops
can have 4 states i.e. Q0,Q1 = 00 or 01 or 10 or 11.

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State assignment and Logic Derivation

In order to design the logic to implement this ow chart we must assign values to the ip
ops. The values assigned are given above since the counter must count in the specied
sequence. Then we can read from the owchart3 the conditions under which the D of each
Flip Flop must be a 1 so that on the next rising edge the Q is a 1.

The Logic Schematic is derived from the Flowchart as follows:

Taking the Q0 ip op rst:

1. Look for states when it has a value of 1.

2. It is a 1 in state1 and state3.

3. Taking state1 rst. Identify all paths that transition into state1. There is only one
path i.e. from state0.

4. Write an equation that species each path into state1, i.e. write a logic equation
which determines when the D of the Q0 ip op should be a 1 such that on the next
rising edge the Q0 value will be a 1.

5. Looking at path1  when the current state is state0 then the next state is state1 and
Q0 must be a 1 in state state1. Thus when in state state0 the D of the Q0 ip op
must assert (i.e. be a 1) so that on the next rising edge Q0 is a 1 and thus . . .

6. path1 => DQ0 must be assigned a 1 when the FSM is in state0 i.e. when Q1=0
and Q0=0 i.e. DQ0 = !Q1 . !Q0 where ! Means NOT.

7. Taking state3. Identify all paths that transition into state3. There is only one path
i.e. from state2.

8. Write an equation that species each path into state3, i.e. write a logic equation
which determines when the D of the Q0 ip op should be a 1 such that on the next
rising edge the Q0 value will be a 1.

9. Looking at path2  when the current state is state2 then the next state is state3 and
Q0 must be a 1 in state state3. Thus when in state state2 the D of the Q0 ip op
must assert (i.e. be a 1) so that on the next rising edge Q0 is a 1 and thus

10. path2 => DQ0 must be assigned a 1 when the FSM is in state2 i.e. when Q1=1
and Q0=0 i.e. DQ0 = Q1 . !Q0 where ! Means NOT.

11. Thus the full equation for DQ0 is

DQ0 = (!Q1.!Q0) + (Q1.!Q0)
Similarly
DQ1 = (!Q1.Q0) + (Q1.!Q0)

3
Also called IFDs i.e. Information Flow Diagrams

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Thus we can draw the schematic as

Figure 1.10: 2 Bit Up Counter Derived Schematic

This does not take account of the reset function yet. The question states that the circuit
should be reset asynchronously i.e. the two ip-ops must be forced to 00 regardless of
the existence of the clock signal. Thus we must use ip-ops with an asynchronous reset
function on them.

Figure 1.11: 2 Bit Up Counter Derived Schematic with Asynchronous Reset

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Draw a timing diagram to convince yourselves that the circuit does indeed implement the
2 bit up counter.

Figure 1.12: Timing Diagram to Complete

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1.5.2 Design of a Sequence Detect using FSM techniques

Design a synchronous digital circuit which monitors an input signal called rxSerD and on
the rising edge of the CLK samples the input.
On four successive samples, if the value on the rxSerD signal is 0110 two output pulses
of exactly one tick duration should be generated. The rst output called out1H should
assert during the 4th data bit on rxSerD if rxSerD is a 0. The second output called out2H
should be glitchless (i.e. it must not have any hazards on it!).
The circuit has a resetH input  which when asserted asynchronously resets the digital
circuit to a known initial state.
A timing diagram which species what we want to occur is shown in gure 1.13

tick0 tick1 tick2 tick3 tick4 tick5 tick6 tick7 tick8 tick9

Clock
rxSerD
out1H
out2H
Figure 1.13: Timing Diagram1

Draw a nite state machine which implements this digital system. From the FSM draw
out the logic for the solution using D-type ip ops and combinational logic elements only.
Do not minimize any of the logic.

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An FSM which solves this is shown in gure 1.14

Figure 1.14: 0110 Sequence Detect FSM

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The following is the reasoning for the design of this solution:

1. We assume for now that the FSM is put into the INIT state due to the assertion of
the resetH signal. This is not shown explicitly in the FSM owchart here.

2. When in state INIT  test the value on the input signal rxSerD and if it is a 0 then
transition to state SN0 else stay in state INIT.

3. State SN0(Seen 0) i.e. this is the rst 0 of the sequence 0110. State SN0 remembers
that we have seen the rst 0 of the 0110 sequence. This is the purpose of state SN0.

4. When in state SN0  test the value on the input signal rxSerD and if it is a 1 then
transition to state SN01 else stay in state SN0  this is still the rst 0 of the 00110
sequence.

5. When in state SN01  test the value on the input signal rxSerD and if it is a 1
then transition to state SN011 else go to state SN0  this is still the rst 0 of the
010110 sequence.

6. When in state SN011  test the value on the input signal rxSerD and if it is a 0
then transition to state SN0 and assert the outputs out1H and out2H for 1 tick each.
Else If rxSerD is a 1 go back to the INIT state and do not assert the output.
We transition to the S0 state from SN011 if rxSerD is a 0 since we now have detected
0110 and the last 0 could be the shared 0 of a new sequence i.e. we could be about
to detect the sequence 0110110.

State Assignment

In order to design the logic to implement this ow chart we must assign values of the
ip-ops to the states above.
If we let the state assignment be as follows(where Q1 and Q0 are state ip ops):

State Q1,Q0
INIT 00
SN0 01
SN01 10
SN011 11

Table 1.1: 0110 FSM - Binary State Encoding

This is clearly a binary state assignment.

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Q0 Flip-Flop Logic Derivation

Taking the Q0 ip op

1. Look for states when it has a value of 1.

2. It is a 1 in state SN0 and state SN011.

3. Taking the SN0 state rst. Identify all paths that transition into state SN0 (and
don't forget that sn0 can transition back to itself!!). These are labeled as path1,
path2, path3 and path4 in the diagram.

4. Write an equation that species each path into SN0, i.e. write a logic equation which
determines when the D0 pin of the Q0 ip op should be a 1 such that on the next
rising edge the Q0 value will be a 1.

5. Consider path1  when the current state is INIT and rxSerD is a 0 then the next
state is SN0 and Q0 must be a 1 in state SN0. Thus when in state INIT and when
rxSerD is a 0 the D of the Q0 ip op must assert (i.e. be a 1) so that on the next
rising edge Q0 is a 1 and thus

6. path1 => DQ0(SN0.path1)=INIT.rxSerD  similarly

7. path2 => DQ0(SN0.path2)=SN0.!rxSerD

8. path3 => DQ0(SN0.path3)=SN01.!rxSerD

9. path4 => DQ0(SN0.path4)=SN011.!rxSerD

10. These 4 conditions force the Q0 ip op to a 1 for transitions to state SN0. These
must be or'ed together for the full equation for DQ0 since these are independent
conditions. Thus:

11. DQ0(SN0)=INIT.!rxSerD + SN0.!rxSerD + SN01.!rxSerD + SN011.!rxSerD

12. But remember these are only for Q0 in state SN0. We must also force Q0 to a 1
when in state SN011. This is shown as path5 in the ow chart.

13. path5 => DQ0(sn011)=SN01.rxSerD

So the full equation for DQ0 is:

14. DQ0(SN0+SN011)=INIT.!rxSerD + SN0.!rxSerD + SN01.!rxSerD + SN011.!rxSerD

+ SN01.rxSerD

State Decode

Each state must be decoded to produce a signal which asserts when the FSM is in that
state. In state INIT the initH signal is asserted. Similarly for the other state decode
signals.
mminitH=Q1H.Q0H = Q1L.Q0L
mmsn0H=Q1H.Q0H = Q1L.Q0H
msn01H=Q1H.Q0H = Q1H.Q0L
sn011H=Q1H.Q0H = Q1H.Q0H
mm

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Logic Schematic

The Schematic for this is shown in gure 1.15

Figure 1.15: 0110 FSM Logic Schematic

The logic to implement the outputs is derived directly from the FSM.
out1H = sn011H.rxSerD
out2H = has the same conditions as out1H but put through a ip-op.
Can you derive the next state logic for the Q1 Flip-Flop.

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1.5.3 State Assignment to Flip-Flop values

Binary State Assignment to Flip-Flop values

The FSM in gure 1.7 has 4 states and this requires a minimum of 2 ip-ops to enumerate.
The state assignment has been given as

State Q1,Q0
Init 00
Sn0 01
Sn01 10
Sn011 11

Table 1.2: Binary State Encoding

This is clearly a binary state assignment.

One-Hot State Assignment to Flip-Flop values

The FSM in gure 1.7 has 4 states and a one-hot state assignment assigns a ip op for
every state of the FSM. One and only one of the ip ops are on for each state.
A one-hot state assignment for the above FSM might be given as:

State Q3,Q2,Q1,Q0
Init 0001
Sn0 0010
Sn01 0100
Sn011 1000

Table 1.3: One-Hot State Encoding

Can you think of any advantages of such a state assignment?

Grey code State Assignment to Flip-Flop values

The state assignment could be been given as

State Q1,Q0
Init 00
Sn0 01
Sn01 11
Sn011 10

Table 1.4: Grey Code State Encoding

This is clearly a dierent assignment to a binary state assignment. This is grey code 
where only one bit changes at a time as states transition to other states.
Grey Code state assignment has some advantages under rather special circumstances. We
shall look at the special circumstances later.
Look closely at the FSM in gure 1.11 and the state to state transitions. Is there always
only one bit transitioning in all cases if the state assignment is as given in table 1.4.

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1.5.4 Design of a Sequence Detect 2 bits at a time

A fast serial wire is sampled at 1GHz. Two samples at a time are presented to a sequence
detect block at 500Mhz. The two bit bus is called din[1:0]. High speed techniques are
required to convert the signal for a single bit serial port at 1Ghz to a two bit interface at
500Mhz - at which speed we can run the fastest FPGAs.

Figure 1.16: 10101 2 bits at a time Block Diagram

We wish to design a synchronous digital circuit which monitors this two bit input bus and
if the value on the din[1:0] signal is 10101 an output pulse of exactly one tick duration
should be generated. Let the output be called out1H and it should be glitchless (i.e. it
must not have any hazards on it!). The circuit has a resetL input  which when asserted
asynchronously resets the digital circuit to a known initial state.
We wish to draw a nite state machine which implements this digital system and from
the FSM to draw out the logic for the solution using D-type ip ops and combinational
logic elements only. The logic schematic is not to be minimised.

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An FSM which solves this problem is given in gure 1.17.

Figure 1.17: 10101 Sequence Detect on din[1:0] FSM Flowchart

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The next step is to do the state assignment i.e. assign values to the state ip-ops for
each state. Since there are 5 states in this system we could use 3 ip-ops and assign a
binary code to the ip-ops.
Since 3 ip ops are needed as a minimum we can have 8 states i.e.

Q2,Q1,Q0 = 000 or 001 or 010 or 011 or 100 or 101 or 110 or 111.

We could use more than three ip ops but we can say that at least 3 are necessary.
A binary code state assignment is not always necessary or indeed the best choice  any
state assignment we care to make is acceptable. For example  we can have 5 ip-ops to
hold the state.
We could call them Q4,Q3,Q2,Q1,Q0. We can let the state assignment be as follows:

State Q4 Q3 Q2 Q1 Q0
Init 00001
Sn1 00010
Sn10 00100
Sn101 01000
Sn1010 10000

Table 1.5: One-Hot State Encoding

This is called a one-hot state assignment.

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DQ0 Logic Derivation.

To design the logic for the Q0 Flip-Flop we must identify all paths that lead to Q0 being
a 1 i.e. all paths into the INIT state. These are identied in gure 1.18 . Five dierent
paths have been identied.

Figure 1.18: FSM Flowchart Paths to INIT State

From this we can write an equation for DQ0 i.e. the D pin of the Q0 ip-op i.e. Path1
path2 path3 path4 path5

DQ0 = Init.!DIN[0].!DIN[1] + SN1.!DIN[0].!DIN[1] + SN101.!DIN[0].!DIN[1]

+ SN10.!DIN[0].!DIN[1] + SN1010.!DIN[0].!DIN[1]

Which we can rewrite as:

DQ0 = Q0.!DIN[0].!DIN[1] + Q1.!DIN[0].!DIN[1] + Q3.!DIN[0].!DIN[1]

+ Q2.!DIN[0].!DIN[1] + Q4.!DIN[0].!DIN[1]

Since we know that only Q0H will ever assert in state INIT, only Q1H will ever assert in
SN1 etc. We can group terms to get
DQ0 = (Q0 + Q1 + Q3 + Q2 + Q4).!DIN[0].!DIN[1]

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The logic schematic for DQ0 and Q0 is as follows: Notice that resetL is tied to the !PR
pin of the ipop.

Figure 1.19: Schematic for Q0

Can you complete the logic derivation for this design i.e. Q1, Q2, Q3, Q4 and output
out1?

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1.6 Reset Methods of Digital Circuits

An asynchronous reset is when the reset signal causes the ip-op to be reset immediately
without waiting for the clock signal. The reset signal is connected directly to either the
clear or the preset pin of the ip-op.
A synchronous reset is when the reset signal causes the ip-op to go to the reset state
after the next clock edge.
A transaction reset is when the reset signal inhibits the start of any new read or writes
(say) to memory but do not stop a transaction in the middle. This is sometimes necessary
to ensure a write transaction to memory completes before the system powers down.

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1.7 TestQuestions
1.7.1 TestQuestion1 3 bit Counter
Design an FSM to implement a three bit counter which generates the count sequence

000->010->101->011->111

and then re-starts again at 000.

The three bit counter outputs are called cnt[2:0]. When the count value is 111 the counter
should assert a terminal count signal call tcH which asserts high during that state.

1. Design and draw the FSM. Assign state Flip-Flops and values to each state.

2. Derive the logic to implement the design.

3. Then draw a timing diagram showing the FSM going through all its states and
generating all outputs. Check that the logic you have derived works correctly with
respect to the timing diagram.

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1.7.2 TestQuestion2 UART Receive

Design a UART Receiver as specied in the context diagram in gure 1.20

Figure 1.20: UART Receiver Context Diagram

and the timing diagram in gure 1.21

Figure 1.21: UART Receiver Timing Diagram

This UART is a simple device:-

1. The start bit is a 0 on digIn for one clock tick

2. The stop bit is a 1 on digIn for one clock tick

3. There are always exactly 8 data bits between the valid start and stop bits.

There are many ways to design this simple UART. Each designer will solve this in slightly
dierent ways.

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1.7.3 TestQuestion3 Detecting Two Sequences at the same time

Design a digital system using an FSM which:

1. Generates an output pulse called outA as a 1 if the sequences 1011 or 0010 are
detected on the serial input signal called xIn on four successive clock edges.

2. The output signal outA must be guaranteed never to glitch i.e. to have either
dynamic or static hazards.

3. The FSM should have the minimum number of states.

4. Overlapping sequences should also be detected.

A timing diagram in Figure 1.22 shows expected behavior for an example input sequence:

Figure 1.22: 1011 or 0010 Examples Sequences

The FSM must be drawn neatly and clearly with all signals named.

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1.7.4 TestQuestion4 Extracting VLAN Tag from Ethernet Frame

Design a VLAN ID tag extraction FSM - shown in Figure 1.23 - which parses4 an Ether-
net/802.3 frame header, byte by byte, and if the frame contains a VID it is extracted
and put onto the output bus called vid[11:0] for one clock tick according to the specica-
tions given below.
An Ethernet/802.3 Tagged MAC frame ss shown in Figure 1.23. In this depiction time
moves from right to left and top to bottom.

1. The rst 6 bytes of the frame contains the destination address  DA[47:0]
2. The next 6 bytes of the frame are the source address  SA[47:0]
3. The next two bytes are the Length/Type of the frame.
If byte 13 is 0x81 and byte 14 is 0x00 then the VLAN ID or VID is contained in the
following two bytes otherwise this frame does not contain a VID.
4. For the Tag Extract Digital Block as shown in Figure 1.23 also.
sof(H) asserts for one clock tick only when the rst byte of the frame is presented
on rx[7:0]. Subsequent bytes come on every subsequent clock tick without gaps.
There are at least 64 bytes in every frame.
5. The signal tagDetectH asserts for one clock tick when vid[11:0] has a valid value.
6. All output signals should be registered.

Figure 1.23: Ethernet Frame Structure and Tag Extract Block

The FSM must be drawn neatly and clearly with all signals named.

4
Steps Through

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1.7.5 TestQuestion5 Writing to Conguration Register

An Integrated Circuit Device has 5 on-chip conguration registers. Each register has 4
data bits. Writes to the conguration registers occur over a single wire serial interface. A
byte may be sent to the IC over the serial interface using an asynchronous protocol - start
bit(a 0) followed by 8 data bits and a stop bit(a 1).
The 1st 4 bits of the serial byte constitute the address of the conguration register to
which the 2nd 4 bits of the serial byte should be written to. SerAdr[0] is rst bit received
o wire after start bit and serDat[0] is 5th bit received.

Figure 1.24: Conguration Registers

The context diagram for this block is shown in Figure 1.25

Figure 1.25: Conguration Register Block Context Diagram

1. Design an FSM and associated logic to implement the CongRegWriter block. The
design extracts the 4 bit address and the 4 bits of data from the serial wire and
asserts a signal called wrRegH for 1 clock tick when they are updated so that the
appropriate register in the register bank can be written. The 4 bit address is put
onto serAdr[3:0] and the 4 bits of data is put onto serDat[3:0].

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2. Design the logic for your FSM. Assign a binary code to the states of any FSM in
your design. Implement an asynchronous reset when a signal called resetH asserts
to reset all ip-ops in the system.

3. Draw a timing diagram showing all the signals in the context diagram and any FSM
states in your design. On the timing diagram show address 316 written with data
B16 .

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1.7.6 TestQuestion6 UART Transmitter

Design a digital system to implement the system shown in gure 1.26 and interface timing
shown in gure 1.27.
Write a verilog module and testbench which implements your design and tests its.

Figure 1.26: UART Transmitter Context Diagram

Figure 1.27: UART Transmitter Timing Diagram

1. This system has a start bit, 8 data bits and 2 stop bits.

2. The byte to be transmitted is copied into the transmitter block on cycle1 because
the block is empty/free but the 2nd byte oered on cycle3 is not copied immediately
because the block is busy sending out the rst byte.
Your design should determine when is a good time to copy byte i.e. when will the
second byteCopied signal assert in your design?

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3. All specications are somewhat ambiguous. In your design - make assumptions

where necessary to complete this design.

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