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Irgbc 20 FD 2

1) The document describes test circuits and waveforms for measuring various electrical characteristics of power transistors, such as turn-on and turn-off energies, switching times, and reverse recovery parameters. 2) Figure 18a shows a test circuit that applies voltages and currents to a device under test (DUT) transistor to measure characteristics like Eon, Eoff, td(on), tr, td(off), and tf. 3) Figures 18b-18d define the waveforms used to calculate these parameters, such as using the integral of Vce and ic to determine turn-on and turn-off energies.

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49 views1 page

Irgbc 20 FD 2

1) The document describes test circuits and waveforms for measuring various electrical characteristics of power transistors, such as turn-on and turn-off energies, switching times, and reverse recovery parameters. 2) Figure 18a shows a test circuit that applies voltages and currents to a device under test (DUT) transistor to measure characteristics like Eon, Eoff, td(on), tr, td(off), and tf. 3) Figures 18b-18d define the waveforms used to calculate these parameters, such as using the integral of Vce and ic to determine turn-on and turn-off energies.

Uploaded by

QuickerMan
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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IRGBC20FD2

90% Vge
+Vge

Vce
Same type
device as
D.U.T.
90% Ic
10% Vce
Ic Ic
5% Ic
430µF
80%
of Vce td(off) tf
D.U.T.

∫
t1+5µS
Eoff = Vce ic dt
t1

Fig. 18a - Test Circuit for Measurement of


ILM, Eon, Eoff(diode) , trr, Qrr, Irr, td(on), tr, td(off), tf t1 t2
Fig. 18b - Test Waveforms for Circuit of Fig. 18a, Defining
Eoff, td(off), tf

∫
trr
GATE VOLTAGE D.U.T. trr
Qrr = id dt
Ic
tx
10% +Vg
+Vg
tx
10% Irr
10% Vcc
Vcc
DUT VOLTAGE
Vce
AND CURRENT Vpk
Irr
10% Ic
Vcc Ipk
90% Ic
Ic
DIODE RECOVERY
WAVEFORMS
5% Vce
td(on) tr

∫
t2

∫
Eon = Vce ie dt t4
t1 Erec = Vd id dt
t3
t1 t2 DIODE REVERSE
RECOVERY ENERGY

t3 t4

Fig. 18c - Test Waveforms for Circuit of Fig. 18a, Fig. 18d - Test Waveforms for Circuit of Fig. 18a,
Defining E on, td(on), tr Defining E rec, trr, Qrr, Irr

Refer to Section D for the following:


Appendix D: Section D - page D-6
Fig. 18e - Macro Waveforms for Test Circuit of Fig. 18a
Fig. 19 - Clamped Inductive Load Test Circuit
Fig. 20 - Pulsed Collector Current Test Circuit

Package Outline 1 - JEDEC Outline TO-220AB Section D - page D-12

C-100

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