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Code For All Blocks

The document describes code for an instruction memory module that stores instructions, an ALU module that performs arithmetic and logical operations, and a register file module that contains registers and interfaces with the instruction memory and ALU modules. It defines the inputs, outputs, and behavior of each module through always blocks and case statements. The modules work together to fetch and execute instructions stored in the instruction memory by accessing operands from the register file and writing results back to registers.

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Sabir Alie
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61 views4 pages

Code For All Blocks

The document describes code for an instruction memory module that stores instructions, an ALU module that performs arithmetic and logical operations, and a register file module that contains registers and interfaces with the instruction memory and ALU modules. It defines the inputs, outputs, and behavior of each module through always blocks and case statements. The modules work together to fetch and execute instructions stored in the instruction memory by accessing operands from the register file and writing results back to registers.

Uploaded by

Sabir Alie
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Code for all blocks

module InstructionMemory(addr,out_ins);
input [31:0] addr;
output [31:0] out_ins;
reg [63:0] instruction_memory[0:6];
reg [63:0] current_ins;
reg [31:0] current_addr;
reg [31:0] req_ins;
assign out_ins =req_ins;
integer i=0;
initial
begin
instruction_memory[0] <=
64'b0000000000000001001110001000000000000000001010110001010100010011;

//2nd instruction : add x10, x10, x25


instruction_memory[1] <= 64'b
00000000000000010011100010000000000000011001010100000101001001000000000000001100101
01000001010011001110011;

//3rd instruction : lw x9, 0(x10)


instruction_memory[2] <= 64'b
0000000000000001001110001000010000000000000001010011010010000011;
//4th instruction : bne x9, x24, Exit // go to Exit if save[i] != k
instruction_memory[3] <= 64'b
0000000000000001001110001000100000000001100001001001011001100011;

//5th instruction : addi x22, x22, 1 // i = i + 1


instruction_memory[4] <=
64'b0000000000000001001110001000110000000000000110110000101100010011;

//6th instruction : beq x0, x0, Loop // go to Loop


instruction_memory[5] <=
64'b0000000000000001001110001001000000000000000000000000011011100011;

//7th instruction Exit


instruction_memory[6] <=
64'b0000000000000001001110001001010000000000000000000000000000000000;
end
always@ (*)
begin
// ins_final={addr,instruction_memory[addr]};
for(i = 0; i <7; i = i+1)
begin
current_ins=instruction_memory[i];
current_addr = current_ins[63:32];
if(current_addr==addr)
begin
req_ins <=current_ins[31:0];
i=7;
end
end
end
endmodule

module ALU_16_bit(A,B,Op,R);
//inputs,outputs and internal variables declared here
input [31:0] A,B;
input [3:0] Op;
output [31:0] R;//R is result
wire [31:0] Reg1,Reg2;
reg [31:0] Reg3;
//Assign A and B to internal variables for doing operations
assign Reg1 = A;
assign Reg2 = B;
//Assign the output
assign R=Reg3;
//Always block with inputs in the sensitivity list.
always @(Op or Reg1 or Reg2)
begin
case (Op)
1 : Reg3 = Reg1 + Reg2; //addition
2 : Reg3 = Reg1 - Reg2; //subtraction
3 : Reg3 = ~Reg1; //NOT gate
4 : Reg3 = ~(Reg1 & Reg2); //NAND gate
5 : Reg3 = ~(Reg1 | Reg2); //NOR gate
6 : Reg3 = Reg1 & Reg2; //AND gate
7 : Reg3 = Reg1 | Reg2; //OR gate
8 : Reg3 = Reg1 ^ Reg2; //XOR gate
9 : Reg3 = Reg1 * Reg2; //Multiplication
10: Reg3 = Reg1 / Reg2; //divsion
11: Reg3 = ~Reg1; //first complement
12: Reg3 = (~Reg1)+1; //two's complement
13: Reg3 = Reg1<<1; //Logical Shift left
14: Reg3 = Reg1>>1; //Logical Shift Right
15: Reg3 = {Reg1[14:0],Reg1[15]}; //Rotate without carry
endcase
end
endmodule

`timescale 1ns / 1ps // clock defined


module regfile32bit (
input clk,
input load,clear,
input [3:0] opcode_in,
output [31:0] a_data,
output [31:0] ins_out_in,
input [31:0] carry_in,
output [31:0] b_data,c_data);
reg [31:0] Registers [0:15];
wire [31:0] alu_output;
reg rd,rs1,rs2;
wire [4:0] b_addr,c_addr,a_addr;

reg [31:0] address_input_im=32'b00000000000000010011100010000000;


//reg [31:0] ins_out_in;

InstructionMemory3 InstructionMemory3_inst
(.addr(address_input_im),.out_ins(ins_out_in));

assign b_addr=ins_out_in[19:15];
assign c_addr=ins_out_in[24:20];
assign a_addr=ins_out_in[11:7];

integer i;
initial
begin
Registers[0] <= 32'b00000000000000000000000000000000;
Registers[1] <= 32'b00000000000000000000000000000000;
Registers[2] <= 32'b00000000000000000000000000000001;
Registers[3] <= 32'b00000000000000000000000000000000;
Registers[4] <= 32'b00000000000000000000000000000000;
Registers[5] <= 32'b00000000000000000000000000000000;
Registers[6] <= 32'b00000000000000000000000000000000;
Registers[7] <= 32'b00000000000000000000000000000000;
Registers[8] <= 32'b00000000000000000000000000000000;
Registers[9] <= 32'b00000000000000000000000000000000;
Registers[10] <= 32'b00000000000000000000000000000000;
Registers[11] <= 32'b00000000000000000000000000000000;
Registers[12] <= 32'b00000000000000000000000000000000;
Registers[13] <= 32'b00000000000000000000000000000000;
Registers[14] <= 32'b00000000000000000000000000000000;
Registers[15] <= 32'b00000000000000000000000000000000;
Registers[16] <= 32'b00000000000000000000000000000000;
Registers[17] <= 32'b00000000000000000000000000000000;
Registers[18] <= 32'b00000000000000000000000000000000;
Registers[19] <= 32'b00000000000000000000000000000000;
Registers[20] <= 32'b00000000000000000000000000000000;
Registers[21] <= 32'b00000000000000000000000000000000;
Registers[22] <= 32'b00000000000000000000000000001010;
Registers[23] <= 32'b00000000000000000000000000000000;
Registers[24] <= 32'b00000000000000000000000000000000;
Registers[25] <= 32'b00000000000000000000000000000000;

end

begin
//integer b_addr_1,c_ddr_1;
// assign b_addr_1=b_addr;
//assign c_addr_1=c_addr;
assign b_data = 31'b1010;
assign c_data =31'b1;

end

ALU_16_bit alu_result_inst
(.A(b_data),
.B(c_data),
//.C(carry_in),
.Op(opcode_in),
.R(a_data) );
always @(posedge clk)
begin
if(load==1)
begin
Registers[a_addr]=a_data;
end
if (clear==1)
for (i = 2; i < 15; i = i + 1)
begin
Registers[i]=0;
end
end
// always @(negedge clk)
endmodule

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