Faculty of Engineering

DEPARTMENT of ELECTRICAL AND ELECTRONIC ENGINEERING

EENG (INFE) 115 Instructor:
Introduction to Logic Design G. YEMİŞCİOĞLU
Final EXAMINATION Duration: 120 minutes
June 12, 2017 Number of Questions: 4
Good Luck

STUDENT’S

NUMBER
NAME
SOLUTIONS
SURNAME
GROUP NO.

Question Achieved Points

1 30

2 30

3 30

4 30

TOTAL 120

Read the following instructions carefully:

1. Calculators are not allowed.
2. Switch off mobile phones and do not borrow any stationery from your friends.
3. In your solutions, show all details you claim credit for.
EENG (INFE) 115 Introduction to Logic Design – Final Examination

Question 1:

Design a combinational circuit that accepts a four-bit number (A,B,C,D) and

generates an output which is equal to the sum of the binary numbers formed by the
input (AB) and (CD).
(30 pts)

AB + CD = ??

Inputs Outputs
A B C D x y z
0 0 0 0 0 0 0
0 0 0 1 0 0 1
0 0 1 0 0 1 0
0 0 1 1 0 1 1
0 1 0 0 0 0 1
0 1 0 1 0 1 0
0 1 1 0 0 1 1
0 1 1 1 1 0 0
1 0 0 0 0 1 0
1 0 0 1 0 1 1
1 0 1 0 1 0 0
1 0 1 1 1 0 1
1 1 0 0 0 1 1
1 1 0 1 1 0 0
1 1 1 0 1 0 1
1 1 1 1 1 1 0

x (A,B,C,D) = Σ(7, 10, 11, 13, 14, 15)

y (A,B,C,D) = Σ(2, 3, 5, 6, 8, 9, 12, 15)
z (A,B,C,D) = Σ(1, 3, 4, 6, 9, 11, 12, 14)

G. YEMİŞCİOĞLU
2 |Page
June 12, 2017
EENG (INFE) 115 Introduction to Logic Design – Final Examination

x’sK-MAP y’sK-MAP

CD CD
AB 00 01 11 10 AB 00 01 11 10

00 0 0 0 0 00 0 0 1 1

01 0 0 1 0 01 0 1 0 1

11 0 1 1 1 11 1 0 1 0

10 0 0 1 1 10 1 1 0 0

x = AC + ABD + BCD y = AC’D’ + AB’C’ + A’B’C + A’CD’ + A’BC’D + ABCD

y = AC’D’ + A’CD’ + AB’C’ + A’B’C + A’BC’D + ABCD
y = D’ (AC’ + A’C) + B’ (AC’ + A’C) + BD (A’C’ + AC)
y = D’ (A ⊕ C) + B’ (A ⊕ C) + BD (A ⊕ C)’

z’sK-MAP
A B C D
CD
AB 00 01 11 10

00 0 1 1 0

x
01 1 0 0 1

11 1 0 0 1

10 0 1 1 0

z = BD’ + B’D

G. YEMİŞCİOĞLU
3 |Page
June 12, 2017
EENG (INFE) 115 Introduction to Logic Design – Final Examination

Question 2:

a) Implement a 1-bit full adder circuit by using 4 x 1 Multiplexer and an inverter.

b) Construct 4-bit ripple carry adder using 1-bit full adder implemented in (a).
c) Implement a 4-bit BCD adder using (b) to add two BCD digits. Make sure that
the circuit also detects invalid BCD digits and generates the correct BCD
output sum.

(30 pts)

a) (10 pts)
A B Cin Cout Mux 1 IN Sum Mux 2 IN
0 0 0 0 0
0 Cin
0 0 1 0 1
0 1 0 0 1
Cin Cin’
0 1 1 1 0
1 0 0 0 1
Cin Cin’
1 0 1 1 0
1 1 0 1 0
1 Cin
1 1 1 1 1

A B

Cin
4x1 A B
Sum
MUX

1-Bit
Cout Cin
Adder
0
4x1
Cout
MUX Sum
1

b) (5 pts)
A3 B3 A2 B2 A1 B1 A0 B0

0
1-Bit Cout3 1-Bit Cout1 1-Bit Cout0 1-Bit
Cout4 Cin
Adder Adder Adder Adder
1

S3 S2 S1 S0

G. YEMİŞCİOĞLU
4 |Page
June 12, 2017
EENG (INFE) 115 Introduction to Logic Design – Final Examination

c) (15 pts)
Z3 Z2 Z1 Z0 Error
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 0
0 1 1 0 0
0 1 1 1 0
1 0 0 0 0
1 0 0 1 0
1 0 1 0 1
1 0 1 1 1
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1

Error’s K-MAP
Z1Z0
Z3Z2 00 01 11 10

00 0 0 0 0
Err = Z3Z2 + Z3Z1
01 0 0 0 0 Output Carry = Cout + Z3Z2 + Z3Z1
11 1 1 1 1

10 0 0 1 1

A3 A2 A1 A0 B2 B1 B3 B0

Cout Cin
4-bit Adder

Z3 Z2 Z1 Z0

Output
Carry

4-bit Adder

S3 S2 S1 S0

G. YEMİŞCİOĞLU
5 |Page
June 12, 2017
EENG (INFE) 115 Introduction to Logic Design – Final Examination

Question 3:

Sequential circuit shown below has two flip-flops A and B and one input x. It
consists of a combinatorial logic connected to the flip-flops, as shown in Figure
below. Analyse the circuit:

a) Derive the next state equations.

b) Derive the state table of the sequential circuit.
c) Draw the corresponding state diagram.

(30 pts)

SET A
J Q

A’
x K CLR Q

I0 2-to-1 B
SET
MUX Y J Q
I1
S
B’
K CLR Q
CLK

a) (10 pts)
JA = A.x’ + B.x’ KA = x’ JB = A’.x’ + (A.B)’x KB = x
JB = A’.x’ + (A’ + B’)x
JB = A’.x’ + A’x + B’.x
JB = A’(x’ + x) + B’.x
JB =A’ + B’.x
A(t+1) = JA.A’ + KA’.A B(t+1) = JB.B’ + KB’.B
A(t+1) = (A.x’ + B.x’)A’ + (x’)’A B(t+1) = (A’+B’.x)B’ + B.x’
A(t+1) = A’.A.x’ + A’.B.x’ + Ax B(t+1) = A’B’ + B’.B’x + B.x’
A(t+1) = A’.B.x’ + Ax B(t+1) = A’B’ + B’x + Bx’
B(t+1) = A’B’ + B XOR x

G. YEMİŞCİOĞLU
6 |Page
June 12, 2017
EENG (INFE) 115 Introduction to Logic Design – Final Examination

b) (10 pts)
Present Input Next
A B x A B
0 0 0 0 1
0 0 1 0 1
0 1 0 1 1
0 1 1 0 0
1 0 0 0 0
1 0 1 1 1
1 1 0 0 1
1 1 1 1 0

c) (10 pts)
0,1

00 01
1

0 0 0
1

10 11

G. YEMİŞCİOĞLU
7 |Page
June 12, 2017
EENG (INFE) 115 Introduction to Logic Design – Final Examination

Question 4:

Design a 2-bit counter using JK-Flip flops with one input. When the input is 0, the
counter counts down, with the repeated sequence (11-10-01-00). When the input
is 1, the counter counts repeated random sequence (00-01-11-10).

a) Draw a state diagram for the sequential circuit.

b) Derive the state table for the sequential circuit.
c) Derive the simplified flip flops input equations.
d) Draw the logic circuit diagram of a 2-bit counter.

(30 pts)

a) (7.5 pts)
0

1 1

0 0 0
11 10 01 00

1 1
b) (7.5 pts)
Step1: Characteristic and Excitation Table of JK-Flip Flop
Characteristic Excitation
J K Q Q(t) Q(t+1) J K
0 0 Q 0 0 0 X
0 1 0 0 1 1 X
1 0 1 1 0 X 1
1 1 Q’ 1 1 X 0

G. YEMİŞCİOĞLU
8 |Page
June 12, 2017
EENG (INFE) 115 Introduction to Logic Design – Final Examination

Step2: Stata Table

Present State Input Next State Flip-Flops Inputs
A B x A B JA KA JB KB
0 0 0 1 1 1 X 1 X
0 0 1 0 1 0 X 1 X
0 1 0 0 0 0 X X 1
0 1 1 1 1 1 X X 0
1 0 0 0 1 X 1 1 X
1 0 1 0 0 X 1 0 X
1 1 0 1 0 X 0 X 1
1 1 1 1 0 X 0 X 1

c) (7.5 pts)
JA’s K-MAP KA’s K-MAP
Bx Bx
A 00 01 11 10 A 00 01 11 10

0 1 0 1 0 0 X X X X

1 X X X X 1 1 1 0 0

JA = B’x’ + Bx KA = B’

JB’s K-MAP KB’s K-MAP

Bx Bx
A 00 01 11 10 00 01 11 10

0 1 1 X X 0 X X 0 1

1 1 0 X X 1 X X 1 1

JB = A’ + x’ KB = A + x’

d) (7.5 pts)

SET A SET
B
J Q J Q

A’ B’
x K CLR Q K CLR Q

CLK

G. YEMİŞCİOĞLU
9 |Page
June 12, 2017