Electronic Materials and Technologies

Solved exercises - MOS

Exercise 1

Two  MOS  capacitors  made  on  a  p-­‐type  silicon  substrate,  doped  with  NA  =  5x1016  acc./cm3,  are  connected  in  
parallel  as  shown  in  the  figure.    

The  gates  of  the  two  capacitors  are  made  of  n+  polySi,  and  the  equivalent  oxide  charge  density  is  Qeq=5x1010  
q/cm2.  Assume  the  workfunction  difference  between  n+  polySi  and  silicon  to  be  Φms=-­‐0.95V.  The  gate  oxide  
thickness   is   60nm   for   capacitor   A   and   30nm   for   capacitor   B.   The   two   capacitors   have   the   same   gate   area  of  
100x100  µm2.  It  is  requested  to:  

a) calculate  the  threshold  voltages  VTA  and  VTB  of  the  two  capacitors;  
b) calculate   the   capacitance   at   high   frequency   of   the   parallel   of   the   two   capacitors   at   an   applied  
voltage  of  2V;  
c) determine   the   type   of   ions   and   the   dose   to   be   implanted   at   the   surface   in   order   to   shift   the  
threshold  voltage  of  capacitor  B  to  VTB=1V.  

 Solution:  

a)  From  the  substrate  doping  concentration  it  is  possible  to  calculate:  

  !" !!
2!! = 2 ∙ !" =0.78V    
! !!

that  is  common  to  both  capacitors,  whereas  the  second  contribution  to  the  ideal  threshold  voltage  depends  
on  the  specific  thickness.  Starting  from  capacitor  A:  
!!"
!!"!! = = 5.67×10!!  F/cm2  
!!"!!

2 ∙ !!" ∙ ! ∙ !!
!! = = 2.23  ! !.!  
!!"!!

!!"!!" = 2!! + !! 2!! = 2.75  !  

Also  the  flat-­‐band  voltage  depends  on  the  oxide  thickness  because  of  the  oxide  charge  term:    

!∙!!"
!!"!! = !!" − =-­‐1.09  V  
!!"!!

Finally,  the  threshold  voltage  of  capacitor  A  is:  

!!" = !!"!!" + !!"!! = 1.66!  

Similarly  we  can  calculate  the  threshold  voltage  of  capacitor  B:  
!!"
!!"!! = = 1.13×10!!  F/cm2  
!!"!!

2 ∙ !!" ∙ ! ∙ !!
!! = = 1.12  ! !.!  
!!"!!

!!"!!" = 2!! + !! 2!! = 1.77  !  

!∙!!"
!!"!! = !!" − =-­‐1.02  V  
!!"!!

Finally,  the  threshold  voltage  of  capacitor  B  is:  

!!" = !!"!!" + !!"!! = 0.75!  

b)  The  applied  gate  voltage  of  2V  is  higher  than  both  the  calculated  threshold  voltages,  so  both  capacitors  
are  in  strong  inversion  conditions  and  their  capacitances  at  high  frequency  are  the  minimum  ones,  to  be  
calculated  as  the  series  of  the  oxide  capacitance  and  the  minimum  semiconductor  capacitance,  the  latter  
being  the  same  for  both  capacitors  because  it  just  depends  on  the  substrate  doping  concentration.    

The  maximum  depletion  width  is:    

2 ∙ !!" ∙ 2!!
!!"# = = 0.14  !"  
! ∙ !!

and  the  semiconductor  capacitance:  

!!"
!!" = = 7.1×10!!  !/!" !  
!!"#

Then:  

!!"!! ∙ !!"
!! = = 3.1×10!!  !/!" !  
!!"!! + !!"

and  

!!!!! ∙ !!"
!! = = 4.4×10!!  !/!" !  
!!"!! + !!"

The  absolute  capacitances  are  obtained  by  multiplying  by  the  gate  areas  (AG=10-­‐4  cm2):    

!! = 3.1  !"  and  !! = 4.4  !"  

Finally,  the  total  capacitance  is  the  sum  of  the  two:  

!!"! = !! + !! = 7.5  !"  

c)  In  order  to  shift  the  threshold  voltage  of  capacitor  B  from  0.75V  to  1V  (positive  shift),  a  surface  ion  
implantation  with  Boron  (negative  fixed  charge)  is  required  at  a  dose  that  can  be  obtained  from  the  
following  equation:  

! ∙ !! ∆!!" ∙ !!"!!
∆!!" = ⟹ !! = = 1.7×10!!  !". !/!" !  
!!"!! !

Exercise 2

On   a   MOS   capacitor   made   on   a   p-­‐type   silicon   substrate   and   having   a   gate   area   of   100x100   µm2,   a   high-­‐
frequency   capacitance-­‐voltage   measurement   is   performed.   In   particular,   the   maximum   capacitance   is  
Cmax=10pF  and  the  minimum  capacitance  is  Cmin=3pF.  It  is  requested  to:  

a) calculate  the  gate  oxide  thickness  and  the  substrate  doping  concentration;  
b) assuming   the   equivalent   oxide   charge   density   to   be   Qeq=5x1010   q/cm2   and   the   workfunction  
difference  between  gate  and  substrate  to  be  Φms=-­‐0.9V,  calculate  the  threshold  voltage  VTH  of  the  
MOS  capacitor.  
c) A   MOS   transistor   fabricated   with   the   same   technology   has   an   aspect   ratio   W/L=20/2.   Calculate   the  
intrinsic  conductivity  kn  and  the  Body  effect  coefficient  γn  of  the  MOSFET.  To  this  purpose,  assume  
the  electron  mobility  in  the  channel  to  be  50%  of  the  electron  mobility  in  the  bulk;    
d) calculate  the  drain  current  flowing  in  the  MOSFET  at  the  bias  point  with  VGS=2V,  VDS=1V  and    VBS=-­‐
1.5V.  

Solution:  

a)  From  the  maximum  capacitance,  the  oxide  thickness  is  readily  obtained:    

  !!" = !!"# = 10!!  !/!" !    

!!

 
!!"  
!!" = = 34  !"    
!!"
 
 

From  the  maximum  and  the  minimum  capacitance,  the  semiconductor  capacitance  is  calculated:  

!!"# ∙ !!" !!"# ∙ !!"#

!!"# = ⟹ !!" = = 4.3  !"  
!!"# + !!" !!"# − !!"#

From  CSi,  the  maximum  depletion  width  is  calculated:    

!!" ∙ !!
!!"# = = 0.23  !"  
!!"

The  value  of  the  substrate  doping  concentration  is  related  to  the  value  of  wmax:  
 2 ∙ !!" ∙ 2!!
!!"# =  
! ∙ !!

A  two-­‐equations  system  can  be  written  and  solved  iteratively:    

!" !!
!! = ∙ !"
! !!
 
4 ∙ !!" ∙ !!
!! = !
! ∙ !!"#

Iteration  step   NA  (cm-­‐3)   ϕF(V)  

0     0.350  
1   1.654x1016   0.360  
2   1.704x1016   0.361  
3   1.708x1016   0.361  
 

So  we  have  2ϕF=0.72V  and  NA=1.7x1016  cm-­‐3  

b)  The  calculation  of  the  threshold  voltage  is  straightforward:  

2 ∙ !!" ∙ ! ∙ !!
!! = = 0.74  ! !.!  
!!"

!!"!!" = 2!! + !! 2!! = 1.35  !  

!∙!!"
!!" = !!" − =-­‐0.98  V  
!!"

!!" = !!"!!" + !!" = 0.37!  

c) The  Body  effect  coefficient  has  already  been  calculated  at  point  b.    
To  calculate  the  intrinsic  conductivity,  the  electron  mobility  must  be  calculated:  

  !!
!! = !!"# + !  
!  
1+ !
!!
1268
!! = 92 + !.!" = 1188  !" ! /! ∙ !  
1.7 ∙ 10!"
1+
1.3 ∙ 10!"

The  mobility  at  the  surface  is  taken  as  50%  of  the  value  in  the  bulk:  

!!!!"#$ = 0.5 ∙ !! = 594  !" ! /! ∙ !  

Finally:  

!! = !!" ∙ !!!!"#$ = 59.4  !"/! !  

d) The  threshold  voltage  at  the  given  bias  point  must  be  calculated  (with  Body  effect):  
 Δ!!" = !! ∙ 2!! − !!" − 2!! = 0.47!  
 
∗
!!" = !!" + Δ!!" = 0.84!  

   
∗
At  the  given  bias  point  the  MOSFET  operates  in  the  linear  region  because  !!" < !!" − !!"  

So,  the  drain  current  can  be  calculated  as:  

!
! ∗
!!"
!! = !! ∙ ∙ !!" −!!" ∙ !!" − = 392  !"  
! 2

Exercise 3

A   MOS   capacitor   (see   cross   section   in   the   figure)   is   made   on   a   p-­‐type   silicon   substrate   having   <100>   crystal  
orientation  and  uniformly  doped  with  1016  at.  B/cm3.    

The  gate  lengths  are  L1=100µm  and  L2=150µm  for  the  poly  and  the  aluminium  gate  regions,  respectively;  
for  both  regions,  the  gate  width  is  W=  250  µm.  For  the  device  fabrication,  the  following  process  sequence  
should  be  considered:    

1.   first  gate  oxide  growth  :  wet  atmosphere,  time    t1  =  30min,  temperature  T=925°C;  
2.   in  situ  doped  n+  poly-­‐Si  deposition  and  patterning;        
3.   second  gate  oxide  growth  :  dry  atmosphere,  time  t2=4h,  temperature  T=950°C  (with  negligible    
effects  on  the  poly  layer  and  on  the  oxide  layer  under  the  poly);    
4.   deposition  of  100  nm  of  TEOS  oxide;  
5.   contact  opening  on  top  of  poly  
6.     aluminium  deposition.    
 

Questions:  

a)   calculate  the  oxide  thicknesses  under  the  poly  and  the  aluminium  gates;  
b)   calculate  the  maximum  space  charge  region  width;  
c)   calculate  the  threshold  voltages  for  the  two  portions  of  the  MOS  capacitor,  assuming  that:    
-­‐  the  work-­‐function  differences  are  φms=  -­‐1.05  V  for  poly  and  φms=  -­‐0.9  V  for  aluminium;    
-­‐  the  equivalent  oxide  charge  density  is  Qeq=  1×1010  q/cm2  for  both  regions;  
d)    draw  a  semi-­‐quantitative  C-­‐V  characteristic  at  high  frequency  of  the  total  capacitance  between  the  gate  
and  substrate  electrodes  in  the  voltage  range  between  -­‐5V  and  +5V,  specifying  all  important  points;  
e)   design  an  additional  process  step  such  as  to  adjust  the  threshold  voltage  of  the  aluminium  gate  
capacitor  to  the  same  value  as  that  of  the  poly  gate  capacitor.      
 

Solution:  

a) The  two  oxide  thicknesses  can  be  calculated  in  a  straightforward  way,  after  determining  the  relevant  
coefficients  from  the  exponential  equations,  as  summarized  in  the  following  table:  

Oxidation    B  (µm2/h)    B/A  (µm/h)   A  (µm)  

Wet  925°C   2.03x10-­‐1   2.35  x10-­‐1   8.66x10-­‐1  
Dry  950°C   6.66  x10-­‐3   2.16  x10-­‐2   3.08  x10-­‐1  
 

The  general  equation  to  calculate  oxide  thickness  is:  

 
! !+!
!! = 1+ − 1    
2 !! /4!

The  term  !  is  dependent  on  initial  oxide  thickness  Xi.  For  the  first  oxidation  no  initial  oxide  is  present,  so  
! = 0.  Applying  the  equation,  the  oxide  thickness  is  therefore:  

 
0.866 0.5
!! = 1+ − 1 = 0.105!"    
2 0.866! /4 ∙ 0.203

For  the  second  oxidation,  there  is  an  initial  oxide  and  the  corresponding  τ can  be  determined  from:  
2

  !!! !! 0.105! 0.105

!! = + = + = 6.49ℎ    
!! (! ) 0.00666 0.0216
! !
Applying  the  equation,  the  oxide  thickness  is  therefore:  

 
0.308 4 + 6.49
!! = 1+ − 1 = 0.152!"    
2 0.308! /4 ∙ 0.00666

To  this  value,  100  nm  of  TEOS  deposited  oxide  should  be  added,  thus  yielding  a  total  oxide  thickness  of  
0.252  µm  for  the  aluminium  gate  capacitor.  

   

b)  The  value  of  the  maximum  space  charge  region  width  wmax  can  be  calculated  by:  

2 ∙ !!" ∙ 2!!
!!"# =  
! ∙ !!
where:       !" !!
2!! = 2 ∙ !" =0.69V    
! !!

It  is  found  that  wmax=0.295  µm.  

c)  Starting  from  the  poly  gate  capacitor,  named  number  1,  and  having  an  oxide  thickness  tox1=0.105µm:  
!!"
!!"!! = = 3.3×10!!  F/cm2  
!!"!!

2 ∙ !!" ∙ ! ∙ !!
!! = = 1.71  ! !.!  
!!"!!

!!!!!" = 2!! + !! 2!! = 2.13  !  

Also  the  flat-­‐band  voltage  depends  on  the  oxide  thickness  because  of  the  oxide  charge  term:    

!∙!!"
!!"!! = !!" − =-­‐1.1  V  
!!"!!

Finally,  the  threshold  voltage  of  capacitor  1  is:  

!!! = !!!!!" + !!"!! = 1.03!  

Passing  to  the  aluminium  gate  capacitor,  named  number  2,  and  having  an  oxide  thickness  tox2=0.252µm:  
!!"
!!"!! = = 1.37×10!!  F/cm2  
!!"!!

2 ∙ !!" ∙ ! ∙ !!
!! = = 4.13  ! !.!  
!!"!!

!!!!!" = 2!! + !! 2!! = 4.14  !  

!∙!!"
!!"!! = !!" − =-­‐1.02  V  
!!"!!

Finally,  the  threshold  voltage  of  capacitor  2  is:  

!!! = !!!!!" + !!!!! = 3.12!  

d) Let’s  start  with  the  calculation  of  all  the  important  capacitance  values  for  the  two  capacitors  separately.  
The  maximum  values  in  accumulation  are  obtained  by  multiplying  the  oxide  capacitances  by  the  gate  
areas:  
!!! = ! ∙ !! = 250×10!!   ∙ 100×10!! = 2.5×10!!    cm2;    
!!! = ! ∙ !! = 250×10!!   ∙ 150×10!! = 3.75×10!!  cm2.  
 
!!!!"# = !!"!! ∙ !!! = 8.25  !"  
!!!!"# = !!"!! ∙ !!! = 5.14  !"  
 

The  semiconductor  capacitance  at  maximum  depletion  width,  common  to  both  structures,  is:  
 !!"
!!"!!"# = = 3.39×10!!  !/!" !  
!!"#
Then:  

!!"!! ∙!!"
             !!!!"# = = 1.67×10!!  !/!" !  
!!"!! !!!"

and  
!!"!! ∙ !!"
!!!!"# = = 9.76×10!!  !/!" !  
!!"!! + !!"

Thus  obtaining:  

!!!!"# = !!!!"# ∙ !!! = 4.18  !"  

!!!!"# = !!!!"# ∙ !!! = 3.66  !"  

Finally,  another  value  that  might  be  useful  to  calculate  is  the  flat-­‐band  capacitance  (Cfb),  i.e.,  the  
capacitance  at  the  flat-­‐band  voltage,  that  depends  on  the  so-­‐called  Debye  Length  (LD):  

!!" ∙ ! ∙ !
!! = = 0.04  !"  
! ! ∙ !!

So  we  have:  
!!"
!!"!!" = = 2.49×10!!  !/!" !  
!!

Then:  
!!"!! ∙!!"!!"
             !!!!" = = 2.91×10!!  !/!" !  
!!"!! !!!"!!"

and  
!!"!! ∙ !!"!!"
!!!!" = = 1.30×10!!  !/!" !  
!!"!! + !!"!!"

Thus  obtaining:  

!!"! = !!!!" ∙ !!! = 7.28  !"  

!!"! = !!!!" ∙ !!! = 4.87  !"  
 
The  corresponding  C-­‐V  curves  for  single  capacitors  and  their  parallel  are  schematically  shown  in  the  
following  picture.  
  

e)  In  order  to  shift  the  threshold  voltage  of  capacitor  2  from  3.12V  to  1.03V  (negative  shift),  a  surface  ion  
implantation  with  Phosphorus  (positive  fixed  charge)  is  required  at  a  dose  that  can  be  obtained  from  the  
following  equation:  

! ∙ !! ∆!!! ∙ !!"!!
∆!!! = ⟹ !! = = 1.79×10!!  !". !/!" !  
!!"!! !