CENG400 Midterm Fall 2015
CENG400 Midterm Fall 2015
School of Engineering
Department of Computer and Communication Engineering
Fall 2015 – 2016
Instructors: Dr. Zaher Merhi, Dr. Ali Ghwouyel, Dr. Ayman Khalil, Dr. Ali Bazzi, Dr.
Abdelmehsen Ahmad, Dr. Ousama Tahan, Dr. Reda Shbib
Time: 75 minutes
There are three Questions in the booklet each has several parts, please answer all parts of the 3
questions to the best of your ability.
Marking Scheme:
Page 1 of 10
Question 1: CPU Performance (25 Points)
b) Computer A has an overall CPI of 1.3 and can be run at a clock rate of 600 MHz.
Computer B has a CPI of 2.5 and can be run at a clock rate of 750 MHz. We have a
particular program we wish to run. When compiled for computer A, this program has
exactly 100000 instructions. How many instructions would the program need to have
when compiled for Computer B, in order for the two computers to have exactly the same
execution time for this program? (7 Points)
Page 2 of 10
c) Consider two different processors P1 and P2 executing the same instruction set. P1 has a 3
GHz clock rate and a CPI of 1.5. P2 has a 2.5 GHz clock rate and a CPI of 1.0.
i. Which processor has the highest performance expressed in instructions per
second? (3 points)
ii. If the processors each execute a program in 10 seconds, find the number of cycles
and the number of instructions. (3 points)
iii. We are trying to reduce the execution time by 30% but this leads to an increase of
20% in the CPI. What clock rate should we have for each of the two processors to
get this time reduction? ( 7 points)
Page 3 of 10
Question 2: Single Cycle Data Path (40 points)
a) Consider the data path below for a single cycle 32-bits MIPS processor
Assume that we are executing the following instruction
- lw $t0, 48($t1)
- Note that the PC and the content of registers $t0 and $t1 are found in bottom left
corner of the figure below
4
2
1
$t0 = 0x00018AC7
3
$t1 = 0x000016F0
PC = 0x000014BA0
(Before executing LW)
Page 4 of 10
1) Fill the table below with the content of the lines indicated by the number on the figure (12
Points). Write down all bits.
1
2
3
4
5
6
Processor IF ID EX MEM WB
Single 200ns 300ns 200ns 400ns 300ns
5-Stage 200 ns 300ns 200ns 400ns 300ns
Pipeline
10-Stage 100ns 100ns 150ns 150ns 100ns 100ns 200ns 200ns 150ns 150ns
Pipeline
For the 10-stage pipeline the IF stage is divided into two stages and so are the rest of the
stages.
2. What is the speedup attained in the 5-stage pipeline and 10-stage pipeline
implementation in comparison with the single cycle implementation if you have
100 instructions to execute (assume no stalls will ever occur). (6 points)
Page 5 of 10
c) We need to implement the following new instruction: JAL Label (check MIPS instruction sheet)
This instruction has two functionalities that should be done in the same clock cycle
Add Extra Hardware Below
Page 6 of 10
Write down assumptions here:
ii. Fill down the controls and the instruction bellow specify new controls in the appropriate
fields (4 Points)
Page 7 of 10
Question 4 – MIPS (35 Points)
b) What is the value of $t2 after the following instructions, if the value of register $t0 is
0x55555555 and $t1 is 0x12345678? (5 points)
d) (20 points) Write a MIPS programs that performs string swap. String swap works as
follows: consider 2 strings, the first string will be copied to the second string replacing all its
content and the second string will be copied to the first string replacing also all its content. It
is not an issue that strings are not of equal size since they are terminated by the /0.
Consider the following example:
String 1 = “ I love MIPS /0”
String 2 = “ I love CENG400 /0”
The result will be
String 1 = “ I love CENG400 /0”
String 2 = “ I love MIPS /0”
Page 8 of 10
The two strings are stored in Data Memory and are located at 0x2234F50 and 0x12AD48
Assume that the string contents are already existing in memory and that each string is
terminated by ‘/0’
Page 9 of 10
Extra Sheet
Page 10 of 10