Latch and Flip-flop - Latch

R-S latch
R
Q

S Q'

Reset Hold Set Reset Set 100 Race

R
S
Q
Q’
 R
Q

▪ State transition diagram

– states: possible values S Q'

– transitions: changes
based on inputs SR=10
SR=00 SR=00
SR=01 SR=10
Q Q' SR=01 Q Q'
0 1 1 0
S R Q SR=01 SR=10
0 0 hold SR=11
0 1 0
1 0 1 Q Q'
1 1 unstable SR=11 0 0 SR=11

SR=00
SR=00 SR=11
SR=01 SR=10

possible oscillation
Q Q'
between states 00 and 11
1 1

3
 Gated or Level-Sensitive Latch
\S
▪ Latch is allowed \Q
to change state
when the enable
signal is \R
asserted. Q
Enable
\Enable

Timing diagram: Reset

Set
\S
▪ Propagation
delay from \R
enable signal to
output changes Enable
is shown in the Q
diagram.
\Q
Clocks

▪ Used to keep time

– wait long enough for inputs (R' and S') to settle
– then allow to have effect on value stored
▪ Clocks are regular periodic signals
– period (time between ticks)
– duty-cycle (time clock is high between ticks - expressed as %
of period)
duty cycle (in this case, 50%)

period
Combining Latches
▪ Connect output of one latch to input of another
▪ How to stop changes from racing through chain?
– need to be able to control flow of data from one latch to the
next
– move one latch per clock period
– have to worry about logic between latches (arrows) that is too
fast
R R Q’ R Q’

S S Q S Q

clock
Latch and Flip-flop – Flop-flop
Combining Latches
▪ Connect output of one latch to input of another
▪ How to stop changes from racing through chain?
– need to be able to control flow of data from one latch to the
next
– move one latch per clock period
– have to worry about logic between latches (arrows) that is too
fast
R R Q’ R Q’

S S Q S Q

clock
Master-slave Flip-flop
▪ Break flow by alternating clocks
– use positive clock to latch inputs into one R-S latch
– use negative clock to change outputs with another R-S latch
▪ View pair as one basic unit
– master-slave flip-flop
– twice as much logic
– output changes a few gate delays after the falling edge of
clock but does not affect any cascaded flip-flops
master stage slave stage
P’
R R Q’ R Q’

S S Q S Q
P
CLK
1s Catching Problem
▪ In first R-S stage of master-slave FF
– 0-1-0 glitch on R or S while clock is high is "caught" by master
stage
– leads to constraints on logic to be hazard-free
1s
Set Reset catch

S
R
Clk Master
P Outputs
P’ Slave
Q Outputs
Q’
D Flip-flop
▪ Make S and R complements of each other
– eliminates 1s catching problem
– can't just hold previous value
(must have new value ready every clock period)
– value of D just before clock goes low is what is stored in flip-
flop

master stage slave stage

P’
R Q’ R Q’ Q’

D S Q S Q Q
P
CLK
Latch and Flip-flop – Timing definitions
Timing definitions
▪ clock: periodic event, causes state of memory element to change
✓ can be rising edge or falling edge or high level or low level
✓ setup time: minimum time before the clocking event by which the input
must be stable (Tsu)
✓ hold time: minimum time after the clocking event until which the
input must remain stable (Th)

Tsu Th data
D Q D Q
input

clock clock

there is a timing "window" stable changing

around the clocking event data
during which the input must
remain stable and unchanged clock
in order to be recognized
Typical timing specifications
▪ Positive edge-triggered D flip-flop
– setup and hold times
– propagation delay

Tsu Th
Tsu Th 1.8 0.5
ns ns
1.8 0.5
D ns ns

Clk
Tc2q
Tc2q
Q 1.1 ns
1.1 ns

All measurements are made from the clocking event (the rising edge of the clock).
 D Q

CLK D

positive
edge-triggered
flip-flop CLK

Qedge

D Q
G Qlatch
CLK
transparent
(level-sensitive)
latch
 Summary

✓ RS latch는 11의 입력은 사용하지 않는다.

✓ Latch 와 flip-flop의 근본적인 차이는 Latch 는 ___________________ 이고

Flip-flop은 _________________________ 이다.

✓ Master-slave flip-flop은 Gated latch의 Transparency 문제를 해결한다.

✓ D-flip-flop은 Master-slave flip-flop의 1’s catching 문제를 해결한다.

✓ Flip-flop에 연관된 timing 요소 3가지는 ______________, _______________,

________________ 이다.