DSP Unit 1 To 5 QB
DSP Unit 1 To 5 QB
Q.No. Questions
1. With a neat diagram explain the scheme of the DSP system highlighting the significance of
sampling process.
2. Derive the relationship between analog frequency and digital frequency.
3. Define decimation and interpolation process. Explain them using block diagrams and
equations. With a neat diagram explain the scheme of a DSP system
4. For the FIR filter y(n)=(x(n)+x(n-1)+x(n-2))/3. Determine i) System Function ii)
Magnitude and phase function iii) Step response.
5. Consider the sequence x(n) = [3, 2, -2, 0, 7]. It is interpolated using interpolation
sequence bk=[0.5, 1, 0.5] and the interpolation factor of 2. Find the interpolated
sequence y(m).
6. Consider a difference equation which defines an IIR filter y(n)=0.9y(n-1)+0.1x(n). Analyze how
many multipler, adders and delay elements are required to implement the above IIR filter.
7. Compute the dynamic range and percentage resolution of a signal that uses
a. 16-point fixed-point format
b 32-point floating-point format with 24 bits for the mantissa and 8 bits
for the exponent.
8. Calculate the dynamic range and precision of each of the following number
representation formats
a. 24-bit, single-precision, fixed-point format
b. 48-bit, double-precision, fixed-point format
c. a floating-point format with a 16-bit mantissa and an 8-bit exponent
9. Explain different sources of error in DSP implementations
10. With the suitable example explain the following number representation formats.
a. Fixed-point format
b. Floating-point format
11. Using 16 bits for the mantissa and 8 bits for the exponent, what is the range of numbers that can
be represented using the floating-point format similar to IEEE-754?
12. Find the decimal equivalent of the floating-point binary number 1011000011100. Consider
IEEE-754 format in which, MSB is the sign bit followed by 5 bits for exponent and 7 bits for the
fractional part.
How many complex multiplications are required for N-point DFT computation, if direct
13. computation and radix-2 FFT based DFT are used? Also compute the number of complex
multiplications required using direct computation of DFT and FFT-based DFT computation for
N=64 and 256.
UNIT - 2
Q.No. Questions
1. Explain the working of 4 x 4 binary multiplier and its hardware structure.
2. Explain the working of 4-bit shift-right barrel shifter
3. It is required to find the sum of 64 numbers each represented by 16 bits. How many bits
should the accumulator have so that the sum can be computed without the occurrence of
overflow error or loss of accuracy?
4. Design a MAC unit with guard bits whose inputs are 16-bit numbers. 1f 256 products
are to be summed up in this MAC. How many guard bits should be provided for the
accumulator to prevent overflow condition from occurring?
5. Explain Arithmetic and Logic unit with relevant block diagram
6. What are the memory addresses of the operands in each of the following cases of indirect
addressing modes? In each case, what will be the content of the addrreg after the memory
access? Assume that, the initial contents of the addrreg and the offsetreg are 0200h and
0010h, respectively.
a. ADD *addrreg-.
b. ADD+ *addrreg
c. ADD offsetreg+, *addrreg
d. ADD *addrreg, offsetreg
7.
𝑦 = ∑ 𝑑𝑚𝑎𝑑(𝑖)
𝑖=410ℎ