DIGITAL LOGIC AND COMPUTER ORGANIZATION - 23CSE103

(B.Tech, II Year I /II Semester)

SHORT ANSWER QUESTIONS
UNIT I and UNIT II
1. State Demorgan’s Law.
2. Convert (115.4)10 and (235.5)10 into Octal, Hexadecimal and Binary equivalent.
3. Give the octal equivalent of hexadecimal numbers: (DC.BA)16 and (AB.CD)16.
4. Find the equivalent Gray code for [10110] 2.
5. Convert the Gray Code 11101110 to equivalent Binary Code.
6. Simplify A’BC+AB’C+ABC’+ABC using Boolean algebra.
7. Convert (1001010.1101001)2 to base 16
8. Convert (231.07)8 to base 10
9. Realize a XOR gate using NOR gates only.
10. What is priority encoder?
11. Define the terms Min Term and Max Term.
12. Define Prime Implicant and Essential Prime Implicant.
13. Sketch the logic circuit of a Half Subtractor.
14. Compare Encoder and Decoder.
15. Draw a 2 X 1 Multiplexer using logic gates.
16. Sketch the logic circuit of a full adder.
17. Define priority encoder.
18. List out the properties of Gray Code.
19. List out the properties of Excess-3 Code.
20. Differentiate between Data Selector and Data Distributor.
21. Differentiate between Flip Flop and Latches.
22. Write down the characteristic equation of a J-K Flip Flop.
23. Tabulate the Excitation Table of a J-K Flip Flop.
24. List out the applications of Flip Flops.
25. Form the Hamming Code for the data bits 111010 using Even Parity.
26. Compare sign magnitude, 1s complement and 2s complement representation.
27. Represent the integer (-128)10 in 8-bit and 16-bit signed number format.
28. Compare fixed point representation and floating point representation.
29. Express (-148.75)10 in Single Precision Floating Point Format.

UNIT III, IV and UNIT V

1. Specify the purpose of Guard Bits, Round Bits and Sticky Bits.
2. Enumerate the various rounding modes in IEEE 754 Floating Point Format.
3. Define the term Instruction Cycle.
4. Define the term addressing mode.
5. Specify the purpose of Program Counter (PC) and Instruction Register (IR).
6. Mention the purpose of Program Status Word (PSW)
7. Enumerate the general purpose registers of x86 family of processors.
8. List out the segment registers of x86 family of microprocessors.
9. Specify the purpose of Program Counter (PC) and Instruction Register (IR).
10. Specify the purpose of Overflow flag.
11. Draw the state diagram of an Instruction Cycle.
12. Compare arithmetic shift and logic shift.
13. Define MAR and MBR.
14. Differentiate between a RISC and CISC Processors.
15. Compare Static RAM and Dynamic RAM.
16. Draw the Memory Hierarchy Pyramid.
17. What is EPROM and EEPROM.
18. Differentiate between Volatile and Non-volatile memory.
19. Enumerate the various levels of RAID.
20. A 16 KB cache memory has 64 sets and each cache block has a capacity of 64 bytes. Determine
the associativity of the cache.
21. Compare write through protocol and write back protocol in Cache.
22. A two way set associative cache has lines of 16 bytes and total size of 8 K bytes.
23. The 64 Mbyte main memory is byte addressable. Show the format of main memory address.
24. Define the term pipeline.
25. List out the advantages and drawbacks of instruction pipeline.
26. Write an expression for time taken to execute n instructions in a k-stage pipeline.
27. Write an expression for speed up of a k-stage pipeline compared to execution without pipeline for
executing n instructions.
28. Enumerate the three types of data hazards in an instruction pipeline.
29. List out the advantages and drawbacks of clusters.
30. List out the characteristics of Symmetric Multiprocessors (SMP).
31. What are chip multiprocessors? List out their features.
32. Distinguish between memory mapped I/O and isolated I/O
33. Mention the advantages of DMA transfer scheme.
34. Enumerate the various types of Data Transfer Schemes
35. What is a Graphics Processing Unit? Mention its applications.

LONG ANSWER QUESTIONS

UNIT I and UNIT II
1. Discuss in detail about Eight ideas of computer Architecture.
2. Design and implement 4-bit binary to Gray code converter.
3. Using K-map method, simplify the given Boolean function and obtain minimum SOP and POS
expression. F = ∑m (0, 1, 5, 9, 13, 14, 15) + d (3, 4, 7, 10, 11). Also draw the minimized SOP
circuit diagram.
4. Find the minimum sum of product expression using K map for the function
F=∑m(7,9,10,11,12,13,14,15) and realize the minimized function using only NAND gates.
5. Using K-map method, simplify the given Boolean function and obtain minimum POS expression.
X= m(1,3,5,7,9) d(8,11,15).
6. Using K-map method, Reduce the following Boolean function F= ∑m(0,2,3,6,7) + d(8,10,11,15)
and obtain minimal SOP.
7. Simplify the Boolean Function F(w,x,y,z)=∑m(0,1,2,3,5,7,8,10,12,13,15) using Quine McCluskey
Method and find the minimal SOP expression.
8. Simplify the Boolean Function F (A,B,C,D) =  (0, 3, 5, 8, 10, 13) + d (2, 7, 11) using Quine
McCluskey Method and find the minimal SOP expression.
9. Design 8-line to 3-line encoder with suitable logic gates.
10. Explain the concept of an encoder with a neat logic diagram and truth table.
11. Design and Implement 4-bit BCD to Excess-3 code converter.
12. Design and Implement 4-bit BCD to Gray Code Converter.
13. What is a Priority Encoder? Design an 8 X 3 Priority Encoder and draw the circuit diagram.
14. Explain the working principle of 8 X 1 Multiplexer and 1 X 8 Demultiplexer with suitable
sketches.
15. Draw the logic diagram and truth table of a 3 X 8 decoder.
16. Explain the working of a SR Flip Flop with a neat logic diagram and also tabulate the Truth
Table, Characteristic Table and Excitation Table.
17. Explain the working of a D Flip Flop with a neat logic diagram and also tabulate the Truth Table,
Characteristic Table and Excitation Table.
18. Explain the working of a JK Flip Flop with a neat logic diagram and also tabulate the Truth
Table, Characteristic Table and Excitation Table.
19. What is a Shift register? List and explain the various types based on Input and Output
combination.
20. Explain the working of a T Flip Flop with a neat logic diagram also tabulate the Truth Table,
Characteristic Table and Excitation Table.
21. Explain the various modes of operation of a 4-bit universal shift register with suitable sketches.
22. Design a 2-bit Synchronous Counter using J-K Flip Flop.
23. Design a 3-bit synchronous Counter using T flip-flops.

UNIT III, IV and UNIT V

1. Illustrate the process of unsigned multiplication for the given data: (7)10 * (4)10
2. Draw the flowchart for the Booths algorithm and illustrate the process of signed multiplication
for the given data: (-17)10 * (14)10
3. Illustrate the Modified Booth’s Multiplication Algorithm with the help of a flowchart. Multiply 11
x -9.
4. Draw the flowchart for the Restoring division algorithm and divide 16 by 4 in non-restoring
method.
5. Draw the flowchart for the Non-restoring division algorithm and divide 15 by 5 in non-restoring
method.
6. Draw the block diagram of a floating point adder and illustrate the steps involved in single
precision floating point addition with a suitable example.
7. Elaborate on Round, Sticky and Guard Bits. Illustrate the various Rounding Rules in IEEE 754
format.
8. Perform the following floating point addition and represent the sum in IEEE single precision
format (9.75)10 + (11.5625) 10
9. Explain the multiplication and division algorithm for floating point numbers.
10. Explain the multiplication algorithm for floating point numbers and also Multiply
1.110 X 2-2 with -1.101 X 2-6
11. Divide (118.5)10 by (1.5)10 in floating point number system and represent the result in IEEE
single precision format.
12. What is an addressing mode? Illustrate the most common addressing techniques with suitable
examples.
13. Explain the addressing modes of x86 with suitable examples.
14. Explain the various ARM addressing modes with suitable examples.
15. Compare RISC and CISC Processors.
16. Explain the various classification of Semiconductor Memories.
17. A computer system with a word length of 32 bits has a 16 MB byte addressable main memory
and 64 KB 4-way set associative cache memory with a block size of
18. 256 bytes. Consider the following physical addresses. A1=0x42C8A4, A2=0x546888,
A3=0x6A289C, A4=0x5E4880. Determine the sets in the cache to which these physical addresses
are mapped.
19. A set associative cache consists of 64 lines or slot divided into four-line sets. Main memory
contains 4 Kbyte blocks of 128 words each. Show the format of main memory address.
20. Explain the basic concepts of Cache. Illustrate the various Cache Memory Mapping Techniques.
21. Consider a machine with byte addressable main memory of 64 KB and block size of 8 bytes.
Assume a direct mapped cache memory consisting of 32 lines is used with this machine.
i. Determine how this 16-bit memory address is divided into tag, line number and byte
number.
ii. Into what cache line would the bytes with each of the following addresses stored?

a) 0001 0001 0001 1011

b) 1010 1010 1010 1010
c) 1101 0000 0001 1101
22. Consider a computer with the following characteristics:
Total of 1 M byte of main memory, word size of 1 byte, block size of 16 bytes and a cache size of
64 Kbytes.
a) For the main memory address of F0010 and CABBE. Give the corresponding tag,
cache line address and word offset for a Direct Mapped Cache.
b) Given any two main memory address with different tags that map to the same cache
slot in a Direct Mapped Cache.
c) For the main memory address of F0010 and CABBE. Give the corresponding tag and
offset values for a Fully Associative Cache.
d) For the main memory address of F0010 and CABBE. Give the corresponding tag,
cache set and offset values for a Two-Way Set Associative Cache.
23. Consider a machine with byte addressable main memory of 64 KB and block size of 8 bytes.
Assume a direct mapped cache memory consisting of 32 lines is used with this machine.
a) Determine how this 16-bit memory address is divided into tag, line number and byte number.
b) Into what cache line would the bytes with each of the following addresses
stored?
i) 0001 0001 0001 1011
ii) 1010 1010 1010 1010
iii) 1101 0000 0001 1101

24. What is RAID? Explain the various Levels of RAID scheme with suitable illustrations.
25. Illustrate the working of a six stage instruction pipeline with a suitable timing diagram.
26. What are pipeline hazards? Explain the various types of pipeline hazards with suitable examples.
27. Explain the Flynn’s taxonomy of Parallel Processor architectures.
28. Explain the concepts of Programmed I/O and Interrupt Driven I/O.
29. Explain the various data transfer schemes.
30. What is Direct Memory Access (DMA)? Explain the working principle of a DMA Controller with a
neat block diagram.