Silicon (2022) 14:8557–8566

https://doi.org/10.1007/s12633-022-01669-9

ORIGINAL PAPER

Effect of Positive/Negative Interface Trap Charges on the Performance

of Multi Fin FinFET (M-FinFET)
Rinku Rani Das1   · Santanu Maity2 · Atanu Chowdhury1 · Apurba Chakraborty3 · Suman Kumar Mitra4

Received: 1 November 2021 / Accepted: 5 January 2022 / Published online: 11 January 2022
© The Author(s), under exclusive licence to Springer Nature B.V. 2022

Abstract
Multiple Fins structured FinFET (M-FinFET) is a promising semiconductor device for future improvisation of CMOS tech-
nology. In this paper, we investigate the impact of interface trap charges (positive and negative trap) at the HfO2/Si interface
in M-FinFET for the first time. The various important DC attributes, RF/analog, and linearity metrics are studied in pres-
ence and absence of traps. Simultaneously, the various trap concentration effect on the characteristics of M-FinFET are also
observed. The results show that the introduction of interface trap charges (ITC) has optimized the ON current, OFF current,
and also improves sub-threshold swing (SS) characteristics as compared to no trap condition. It is observed that negative trap
having trap concentration of ­1013/cm2 enhances the ­ION by 1.64%, SS by 5.66%, and various important RF/analog parameter
such as transconductance frequency product (GFP) improves by 1.25%, device efficiency by 37.12% and intrinsic gain (­ Av)
90.38%. On the other hand, linearity parameters like VIP2, VIP3 and 1 dB compression point shows better performance in
presence of positive and negative trap.

Keywords  Voltage intercept point (VIP) · Sub-threshold swing (SS) · Gain frequency product (GFP) · Transconductance
frequency product (TFP)

1 Introduction various transistors can be integrated into a single chip that

reduces the power consumption with better performance [6,
Advancement of technology means scaling of device attrib- 7]. Various MOS [8] initiative structures such as double-gate
utes in nanometer range [1], replacement of conventional MOSFET, dual material gate (DMG) MOSFET, surround-
materials like integration of H­ fO2 material instead [2, 3] ing gate (SG) MOSFET, etc. have been proposed by Gordon
of ­SiO2, and various modification techniques such as gate Moore to increase the efficiency [9, 10]. Aggressive downs-
material engineering, gate oxide engineering, work function caling of device parameters limits the performance of these
engineering, and space engineering, [4, 5] etc. The outcomes all planar MOS structures [11] to meet the requirements of
are reduction of supply voltage, low leakage current whereas the International Technology Roadmap for Semiconductor
Projection (ITRS) [12] and device faced a serious unwanted
problem called short channel effects (SCEs) [13, 14]. Drain-
* Rinku Rani Das induced barrier lowering (DIBL), sub-threshold swing (SS)
rinkutit123@gmail.com [15], threshold voltage variation [16], and mobility degrada-
1
Department of Electronics and Communication Engineering, tion are the various SCEs.
National Institute of Technology, Agartala, Tripura 799046, To minimize these SCEs issues, the researcher developed
India various ultra-modern structures which operated in high fre-
2
Department of Electronics and communication Engineering, quency. Fin shaped Field-effect transistor (FinFET) [17, 18]
Indian Institute of Engineering Science and Technology, 3D dimensional, is one of the mainstream candidates in the
Shibpur 711103, India semiconductor industry over planar conventional devices
3
Department of Electrical and Electronics Engineering, Birla [19] in the 22 nm to sub 10 nm regimes which has supe-
Institute of Technology and Science, Pilani, Goa 403726, rior gate controllability on channel, high transconductance,
India
less leakage current, ideal sub-threshold swing, and high
4
Department of Electrical and Electronics Engineering,
Harcourt Butler Technical University, Kanpur 208002, India

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8558 Silicon (2022) 14:8557–8566

switching speed [20]. The number of Fin increases the drive on Ge FinFET in presence of positive and negative trap
capability as the total channel width also increased. charges (PTC and NTC). They revealed that PTC improves
Nowadays researcher has shown their interest to build the device reliability and introducing of Ferroelectric layer
up a multiple Fin based FinFET structure [21, 22] whereas with NTC enhances the output performance. However, a
multiple parallel Fins between source and drain are placed. very few studies have been reported to analysis the impact of
Multi-Fin FET (M-FinFET) structure is very useful for RF interface trap charges on FinFET device in details. Specially,
application in high frequency and well suppressed in SCEs there is no literature of interface trap effect on M-FinFET
issues. K. Tachi et al. [23] in have investigated multi-channel device which motivates us to implement the same.
Field-Effect Transistors (Mc-FETs) architecture to reduce In this work, the impact of interface traps at the Si-HfO2
the source-drain resistance by combining Ion implantation interface on the performance of the M-FinFET structure
and in-situ doped SEG (Selective Epitaxial Growth) which has been newly investigated. Various interface traps such as
increases the current gain. On the other hand, Emilie Ber- positive trap and negative trap with various trap concentra-
nard et al. [24] in have proposed the multi-channel Field- tions have been introduced and their influences are studied to
Effect Transistor (Mc-FET) and investigated the perfor- analyze the RF/analog performance. The research paper has
mances of electrical parameters such as ­ION and I­ OFF. They been arranged in the following sections. Section 2 describes
showed that Mc-FET contributes ultra-low ­IOFF and high the proposed structure with dimensions and various acti-
­ION which are satisfying low standby power (LSTP) and vated models are mentioned for the simulation study. Sec-
high performance (HP) applications. Wen-Kuan Yeh et al. tion 3 discusses the simulation results. Finally, concluding
[25] investigates the effect of carrier quantization on multi- observation is given in section 4.
fin high K/Metal tri-gate n-type and p-type FinFET where
several Fins exhibited superior device performance. Nev-
ertheless, the above research towards M-FinFET is mainly 2 Design and Simulation
focused on device characteristics without focus on the effects
of interface trap charges. The 3D and 2D views of Multi-Fin based FinFET (M-Fin-
It has been also reported that the presence of interface FET) structure are shown in Fig. 1a & b. 3 numbers Fin are
trap charges at the oxide-channel interface impacts device placed in between source and drain region where all Fin is
reliability [26]. Variation in process, stress, radiation, and in equal dimensions. Silicon used as Fin material and H ­ fO2
hot carriers effect is the reason behind the introduction of used as gate dielectric material is wrapped over three Fin.
interface traps at the oxide-channel interface [27]. Acceptor Titanium (φm = 4.4 eV) to be considered as gate material
and donor are the two types of interface trap which are pre- and ­SiO2 as an oxide material. The channel region is lightly
sent at oxide-channel interface. The presence of acceptor and doped to minimize the adverse effect like mobility degrada-
donor traps changes the device performance where acceptor tion and tunneling issue and the doping concentration value
trap treated as negative charges and donor trap treated as is ­1017 ­cm−3. And the source/drain region is uniformly doped
positive charges. It is reported device is more immune to and the doping concentration value is ­1022 ­cm−3. The length
interface trap effects and improves the electrical characteris- of the source and drain region is 20 nm. The thickness and
tics of the device. K Pratap et al. [28] investigates the impact height of S ­ iO2 buried oxide are taken 14 nm and 15 nm. Gate
of interface trap at Si-SiO2 interface in negative capacitance length value of M-FinFET is considered 5 nm whereas Fin
FinFET structure and found that the smaller variation of the width = 2 nm and Fin height = 8 nm are considered to simu-
threshold voltage is observed in presence of interface trap. late the structure. The simulation of the M-FinFET structure
Paper [29] investigates the impact of negative capacitance is done by TCAD Sentaurus software [30].

Fig. 1  M-FinFET structure (a) 3D view (b) 2D cross-section view (c) enlarged view

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Silicon (2022) 14:8557–8566 8559

In this paper, we proposed an M-FinFET structure and

study the effect of different interface traps such as positive
trap and negative trap and uncover the performance regard-
ing linearity and RF/analog applications. Various models
are activated to simulate the M-FinFET structure. Phonon
scattering and Coulomb scattering models are considered
to account for the effect of mobility degradation due to high
doping concentration in semiconductor devices. SRH model
is turned on in a simulator for the recombination and genera-
tion process. Band narrowing effect leads to activation of
Old Slotboom model. To checking velocity saturation and
mobility of charge carrier purposes, the velocity saturation
model and mobility Masetti model are activated. For car-
rier transportation, the drift-diffusion model is taken. The
quantum density gradient model is activated for quantization
correction effect.
Fig. 2  ID –VG transfer characteristics of Conventional FinFET&
M-FinFET
3 Result and Discussion

This section studied the impact of different interface trap It is clearly noticed that proposed structure M-FinFET
charges such as positive and negative trap at Si-HfO2 inter- contributes better I­ ON than other existing structures. For
face in M-FinFET structure. The various trap concentration all these advantages, the impact of interface trap charges
(TC) value are (­ Nf=) ­1012/cm2, 3 × ­1012/cm2, 7 × ­1012/cm2, has done on the proposed structure.
and ­1013/cm2. Drain to the gate voltage of 0.5 V is con- The impact of positive and negative trap at oxide-chan-
sidered for the whole simulation study. The drain current nel interface changes the flat band voltage which indirectly
with RF/analog and linearity parameters performance of impact on threshold voltage, drain current and other per-
M-FinFET structure has been shown in the presence and formances. We know the formula for changing flat band
absence of traps. Section 3.1 discusses the input/output char- voltage is [33].
acteristics of M-FinFET in presence of an interface trap.
qNf
Section 3.2 portrays the analog performance of the M-Fin- 𝛥Vfb = (1)
FET structure where 3.3 observe the RF performance of the Cox
M-FinFET structure. Section 3.4 demonstrates the linearity
performance. 2∈ox
Cox =
(2)
( )
2tox
tsi ln 1 +
3.1 Input/Output Characteristics of M‑FinFET tsi

Where q is the charge, N fis interface charge density

The comparison of drain current between conventional
∈ ox= permittivity of oxide, tox and tsi is the thickness of
FinFET (C-FinFET) and multi-Fin structure M-FinFET
oxide and Si.
is portrayed in Fig. 2 where all the dimensions remain
Fig. 3a demonstrates the comparison of drain current
same except Fin part. Single Fin is considered in conven-
characteristics of M-FinFET in the presence and absence
tional FinFET where multiple numbers of Fins constructed
of trap where the positive and negative trap having trap
M-FinFET structure. The number of Fins is equal to num-
concentration value of ­1013/cm2. The presence of interface
ber of channels. If number of Fins (channels) is enlarged,
trap at Si-HfO2 interface changes the device performance.
more electrons can pass from source to drain region that
It is observed that positive trap charges increases the on
enhances the coupling effect nearby Fins which improves
current as comparison no trap condition due to reduction
the driving capability of the device. It is observed that
of barrier from source to channel region. On the other
proposed structure exhibits better ­ION than conventional
hand, the presence negative trap decreases the electron
FinFET. The SS value is also minimum (=70.75 mV/dec)
density due to increase of flat band voltage. The effec-
for proposed device whereas C-FinFET has SS value of
tive gate bias decreases the electric field as flat band volt-
88.1 mV/dec. A comparative analysis of proposed device
age increases. As results, M-FinFET with negative trap
with other recent existing structures has shown in Table 1.
charges exhibits less ­ION.

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Table 1  Comparative analysis Reference Device structure parameters Output performance(ION)

of M-FinFET with other
FinFET devices [31] GaN SOI FinFET Lg = 8 nm, 0.8 mA
[29] NC Ge FinFET Lg = 20 nm 10−5A
[32] TG JL SOI FinFET Lg = 5 nm 1.89 × ­10−4A
Proposed structure M-FinFET Lg = 5 nm 12.16 mA

Fig. 3  Transfer characteristics
of M-FinFET structure (a) ­ID
–VG (b) ­ID –VD

Table 2  DC parameters of M-FinFET in presence and absence of The impact of negative trap for different trap concen-
traps trations, when the gate bias is varying within their range
Parameter Without traps Positive trap Negative trap (0 V to 1.5 V), on drain current characteristics is shown in
Fig. 4b. As established in Eq. 1, the density of interface trap
Vth(V) 0.284 0.257 0.397 charges is proportional to flat band voltage which changes
SS(mV/dec) 70.75 73.1 66.96 the threshold voltage. As results, there is a significant incre-
Gmpeak(mS) 11.01 11.05 11.00
ment in drain current and decrement of threshold voltage has
Switching ratio 1.04 × ­1012 9.17 × ­1011 1.07 × ­1012 observed as positive trap concentration value decreases. An
enhancement of ON current is observed for the negative trap
of low trap concentration ­(Nf = −1012/cm2).
The output characteristics ­ID-VD of the M-FinFET device The two important DC attributes like V ­ th and SS are
has presented in Fig. 3b and comparative analysis are shown shown in Fig. 4c and d for positive and negative traps hav-
for with and without traps condition. M-FinFET device con- ing different trap concentrations. TCAD simulator shows
tributes more ON current as drain voltage increases. It is that by keeping trap concentration of positive trap charges
seen that device with positive traps provides maximum ON low, ­Vth value can be improved due to reduction of flat band
current as compared to other variation. voltage. On the other side, the presence of negative trap
The various DC parameters such as ­Vth, SS, and switch- charges increases the threshold voltage that degrades the
ing ratio are tabulated in Table 2. It is reported that sub- performance.
threshold swing improves in presence of negative interface
traps whereas a slight enhancement of SS can be seen with
positive trap charges that degrades the device performance. 3.2 Study of Analog Performance
On the other hand, the variation of the threshold voltage is
less in presence of positive trap due to generation of some Various analog parameters performance like transconduct-
electrons when holes occupy the traps. ance ­(Gm), drain conductance (­ Gd), device efficiency, intrin-
The input characteristics ­ID-VG of M-FinFET device has sic gin ­(Av), and early voltage ­(VEA) have been demonstrated
been demonstrated for various trap concentration (TC) of in Fig. 5 for trap/without trap circumstance to evaluating the
positive trap in Fig. 4a. It can be perceived that there is overall analog performance of M-FinFET [34].
a negligible impact of trap concentration on drain current Transconductance measures the amount of gate control-
from low gate bias to high drain bias due to less variation lability on the drain current and it’s related to the gain of the
of effective gate bias. One inset are added to visualize the transistors. It is found that ­Gm performance varies with gate
variation of drive current for negative traps having different voltage and peak value of G ­ m has been observed at low gate
trap concentrations. bias for the presence of traps (positive and negative trap)

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Silicon (2022) 14:8557–8566 8561

Fig. 4  Transfer characteristics
of M-FinFET structure (a) ­ID
–Vgs (b) ­ID –Vds and SCEs per-
formance (c) ­Vth-TC (d) SS-TC

shown in Fig. 5a and ­Gm falls at high gate voltage due to increases under the influence of negative trap charges shown
mobility degradation. in Fig. 5d.
The variation of ­Gd as a function of gate voltage with or On the other hand, the opposite scenario can be seen in
without interface trap condition is shown in Fig. 5b. Drain the early voltage performance of the M-FinFET device. The
conductance ­(Gd) is also used to estimate the intrinsic gain early voltage ­(VEA = ­Id/Gd) value should be high to improve
of the device. In the linear region, ­Gd value is very high and the analog performance in the device. The early voltage
starts to decrease as drain voltages beyond pinch-off voltage. value is very less in the sub-threshold region. But early volt-
In the saturation region, the performance of ­Gd remains con- age is enhanced with the increase value of gate bias. Without
stant for all variations. From Fig. 5b it is seen that drain con- trap or positive trap condition, M-FinFET contributes an
ductance is fully suppressed at negative trap conditions due efficient value of early voltage.
to increment of output resistance that improved the analog
performance with better driving capability. 3.3 Study of RF Performance
Device efficiency is an important attribute that can be rec-
ognized by the ratio of transconductance to drain current of To evaluate the RF performance [35], various figures of
any circuit. Fig. 5c aiming to compare the device efficiency merit (FOM) such as gate capacitance ­(Cgg), transconduct-
performances with gate voltage variation for M-FinFET ance frequency product (TFP), cut-off frequency ­(Ft), gain
structure in the presence and absence of trap. Interestingly, frequency product (GFP), and transconductance frequency
an insignificant variation of device efficiency has been product (GTFP) have been demonstrated shown in Fig.6.
observed for the trap/without trap condition. Device effi- The gate capacitance and cut-off frequency performance are
ciency value is highest at very low gate bias for all variation investigated by including the introduction of trap/without trap
and in the strong inversion region, device efficiency value is charges shown in Fig. 6a &b. ­Cgg and ­Ft performance of the
very low that indicating the power dissipation of any device. M-FinFET device is affected by the influence of trap charges.
Intrinsic gain ­(Av) and early voltage performance have ­Cgg value increases due to more charge carriers are observed
been shown in Fig. 5d and e. The ratio of transconductance in the gate region due to high gate bias. And in presence of
­(Gm) to output conductance ­(Gd) is called intrinsic gain ­(Av). positive and negative traps, C
­ gg performance is prominent. On
To obtain higher ­Av, the ­Gd value should be less in analog the other hand, cut-off frequency ­(Ft = ­Gm/2πCgg) is defined as
circuit design. The increased value ­Gm and decreased value the frequency at which gain is one. It is seen from Fig. 5b ­Ft
of ­Gd maximize the intrinsic gain. The intrinsic gain value increases at very low gate voltage due to higher value of G ­ m

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8562 Silicon (2022) 14:8557–8566

Fig. 5  Analog performance (a)

transconductance ~gate voltage
(b) drain conductance ~drain
voltage (c) device efficiency ~
gate voltage (d) intrinsic gate
~gate voltage e early voltage
~Drain voltage

and lower value of ­Cgg that enhances the gate controllability

( )( )
Gm Gm
and highest value of ­Ft is obtained due to various interface GTFP = Ft (2)
Gd Id
traps effect.
Another, two RF parameters like gain frequency product The effect of positive traps has a substantial impact on
(GFP) and gain transconductance frequency product (GTFP) the GFP and GTFP characteristics of the device. It is illus-
[36] against gate voltage have been shown in Fig.  6c    d trated that the significantly improved value of Ft and an
respectively. insignificant reduction of ­Gm/Gd improved the GFP per-
GFP and GTFP can be determined by formance in presence of negative traps. The higher value
( ) of GFP is very profitable in ULP applications.
Gm GTFP is the product of transconductance, gain and
GFP = Ft (1)
Gd frequency product which is used to estimates the whole
performance of the device. It is observed that GTFP value
increases due to having higher value cut-off frequency.

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Silicon (2022) 14:8557–8566 8563

Fig. 6  RF performance (a) gate

capacitance ~gate voltage (b)
cut-off frequency ~ gate voltage
(c) GFP ~ gate voltage (d) GTFP
~gate voltage (e) TFP ~ gate
voltage

And peak value of GFP and GTFP is examined under the 𝜕 2 ID

guidance of a negative trap at very low gate voltage. Gm2 = (3)
𝜕 2 Vgs
Transconductance frequency product (TFP = ­Gm/Id*Ft) is
a very useful RF parameter and TFP versus ­VGS has shown
in Fig. 6e. An insignificant variation of TFP is observed 𝜕 3 ID
Gm3 = (4)
from low gate bias to high gate bias due to positive and 𝜕 3 Vgs
negative trap effects. As ­Gm and ­Ft value increases at very
low gate bias, TFP value also increases that indicating lesser Gm2 is a second-order derivative of drain current with
mobility degradation in the device. gate bias at constant drain bias. And G ­ m3 is a third-order
derivative of drain current with respect to gate voltage at
3.4 Study of Linearity Performance fixed drain bias. These two coefficients should be minimum
for better linearity performance. Figure 7a&b represents the
Linearity analysis is very essential for any circuit perfor- ­Gm2 and ­Gm3 performance with respect to the gate voltage in
mance [37]. Linearity of parameters signifies less distortion presence or absence of the traps. It is observed that ­Gm2 and
at the output. The higher-order derivative of transconduct- ­Gm3 value is less with high drain bias (when exceeds 0.5 V)
ance ­(Gm) estimates the overall performance of linearity which is beneficial for linearity performance. Voltage inter-
parameters. cept point (VIP) is very essential for linearity parameters
Gm2 and ­Gm3 are the two higher-order derivative of ­Gm and becomes very fundamental in RF application [38]. The
which can be determined by second-order harmonics called VIP2 can be defined as

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8564 Silicon (2022) 14:8557–8566

Fig. 7  Linearity performance
(a) VIP3 ~ gate voltage (b)
VIP3 ~ gate e voltage (c) 1 dB
compression point ~ gate volt-
age

Gm compression point performance against gate bias has shown

VIP2 = 4
Gm2 (5) in Fig. 7e in the presence and absence of traps. M-FinFET
device with or without interface trap (positive and negative
Third-order harmonics called VIP3 can be determined as trap) condition, provides an efficient value of 1 dB compres-
√ sion point due to high value of transconductance. It indicates
G M-FinFET device has a remarkable impact for various inter-
VIP3 = 24 m (6)
Gm3 face traps (positive and negative trap).
A comparative analysis of proposed M-FinFET and other
VIP2 and VIP3 performance of M-FinFET with/without contemporary device performances has been shown in Table 3.
trap condition has shown in Fig. 7c&d. With a negative trap It is clearly observed that the proposed device M-FinFET has
condition, a peak value of VIP2 is obtained. On other hand, shown superior performances in terms of ON current, device
the M-FinFET device without trap conditions, exhibits maxi- efficiency and SS which are very useful in the future semicon-
mum VIP3 as compared to other variations. The higher value ductor industry.
VIP2 and VIP3 improve the carrier density and transcon-
ductance which leading to an improvement of linearity of
the device.
Another essential linearity parameter called 1 dB compres-
sion point and its efficiency can be improved if the input power
level provides less amount of output power level. The 1 dB

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Table 3  Comparative analysis of M-FinFET with other exiting M-FinFET devices

References Device structure and materials used Parameters

[39] Multi-Fin FinFET (Si as channel, ­HfO2 as dielectric constant, Lg = 30 nm, ­Tox = 1.5 nm, φ = 4.5 eV ­Vd = 0.5 V
Co as gate material) SS = 79.92 mV/dec, Vth = 0.39 V, ­ION = 0.797 mA
[40] Multi-Fin FinFET (Si as channel) Lg = 10 nm,Tox = 0.6 nm,Vd = 0.8, ­ION = 0.01 mA
[41] Multi-Fin FinFET (Si as channel, ­HfO2 as dielectric constant, Lg = 30 nm,Tox = 1.5 nm, ­Gmpeak = 0.8mS, TGF = 45 ­V−1
Copper as gate material) ­ION = 0.36 mA
[42] M-FinFET (GaAs as channel Ti as gate material, H ­ fO2 as Lg = 10 nm, ­Tox = 1 nm, ­ION = 2.7 mA, SS = 71 mV/dec,
dielectric constant. TGF = 36.64 ­V−1, ­Gmpeak = 2.67mS
Proposed structure M-FinFET (Si as channel Ti as gate material, ­HfO2 as dielec- Lg = 5 nm, ­Tox = 1 nm, ­ION = 12.16 mA, ­Vth = 0.28 V
tric constant. SS = 70.75 mV/dec,TGF = 51.89 ­V−1,
­Gmpeak = 11.01mS

4 Conclusion Consent for Publication (Not Applicable)  I, the undersigned, give my

consent for the publication of identifiable details to be published in the
above Journal and Article.
In this work, we have successfully investigated the impact
of different interface trap charges (ITC) on the device per-
Conflict of Interest/Competing Interests (Not Applicable)  There is no
formance of the M-FinFET structure. Various interface conflict of interest.
traps such as positive and negative traps having differ-
ent trap concentrations have been studied to examine the Disclosure of Potential Conflicts of Interest (Not Applicable)  No poten-
tial conflict of interest was reported by the authors.
dependability of device performance. The various DC
parameters such as V ­ th, SS, G
­ mpeak, and I­ ON/OFF (switching Research Involving Human Participants and/or Animals (Not Applica-
ratio) are calculated with the consideration of the pres- ble)  This article does not contain any studies with human participants
ence and absence of traps, comparatively. The important or animals performed by any of the authors.
highlights from this simulation study are: the presence Consent Informed (Not Applicable)  Additional informed consent was
of interface trap at oxide/channel interface maximizes obtained from all individual participants for whom identifying informa-
the drive current without degrading of I­ OFF in M-FinFET tion is included in this article.
device. Careful optimization of trap concentration of nega-
tive trap reduces the V­ th and SS when trapping concentra-
tion value is decreases from 1­ 013/cm2 to ­1012/cm2. While
we analyzed, the device has a negligible effect of positive
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