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TPA3111D1
SLOS618F – AUGUST 2009 – REVISED JULY 2016

TPA3111D1 10-W Filter-Free Mono Class-D Audio Power Amplifier With Speaker Guard™
1 Features 3 Description
1• 10-W into an 8-Ω Load at 10% THD+N From a The TPA3111D1 device is a 10-W, efficient, Class-D
12-V Supply audio power amplifier for driving a bridge tied
speaker. Advanced EMI suppression technology
• 7-W into an 4-Ω Load at 10% THD+N From a 8-V enables the use of inexpensive ferrite bead filters at
Supply the outputs while meeting EMC requirements.
• 94% Efficient Class-D Operation into 8-Ω Load SpeakerGuard speaker protection system includes an
Eliminates Need for Heat Sinks adjustable power limiter and a DC detection circuit.
• Wide Supply Voltage Range Allows Operation The adjustable power limiter lets the user to set a
virtual voltage rail lower than the chip supply to limit
from 8 to 26 V
the current through the speaker. The DC Detect
• Filter-Free Operation circuit measures the frequency and amplitude of the
• SpeakerGuard™ Speaker Protection Includes PWM signal and shuts off the output stage if the input
Adjustable Power Limiter Plus DC Protection capacitors are damaged or shorts exist on the inputs.
• Flow-Through Pinout Facilitates Easy Board The TPA3111D1 can drive a mono speaker as low as
Layout 4 Ω. The high efficiency of the TPA3111D1, >90%,
• Robust Pin-to-Pin Short-Circuit Protection and eliminates the requirement for an external heat sink
Thermal Protection With Auto-Recovery Option when playing music.
• Excellent THD+N and Pop-Free Performance The outputs are fully protected against shorts to
GND, VCC, and output-to-output. The short-circuit
• Four Selectable, Fixed Gain Settings
protection and thermal protection includes an auto-
• Differential Inputs recovery feature.

2 Applications Device Information(1)

• Televisions PART NUMBER PACKAGE BODY SIZE (NOM)

• Monitors and Laptops TPA3111D1 HTSSOP (28) 4.40 mm × 9.70 mm

• Consumer Audio Equipment (1) For all available packages, see the orderable addendum at
the end of the data sheet.

Simplified Application Diagram

1uF

OUT+ INP TPA3111D1

Audio OUT - INN
Source

OUTP FERRITE
10W
BEAD
OUTN FILTER 8Ω
GAIN0
GAIN1

PLIMIT

Fault
SD PVCC 8 to 26V

Copyright © 2016, Texas Instruments Incorporated

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features .................................................................. 1 7.3 Feature Description................................................. 11
2 Applications ........................................................... 1 7.4 Device Functional Modes........................................ 14
3 Description ............................................................. 1 8 Application and Implementation ........................ 15
4 Revision History..................................................... 2 8.1 Application Information............................................ 15
8.2 Typical Application .................................................. 15
5 Pin Configuration and Functions ......................... 3
6 Specifications......................................................... 4 9 Power Supply Recommendations...................... 20
6.1 Absolute Maximum Ratings ...................................... 4 10 Layout................................................................... 21
6.2 ESD Ratings.............................................................. 4 10.1 Layout Guidelines ................................................. 21
6.3 Recommended Operating Conditions....................... 5 10.2 Layout Example .................................................... 22
6.4 Thermal Information .................................................. 5 11 Device and Documentation Support ................. 23
6.5 DC Characteristics – VCC = 24 V .............................. 5 11.1 Device Support...................................................... 23
6.6 DC Characteristics – VCC = 12 V .............................. 5 11.2 Documentation Support ........................................ 23
6.7 AC Characteristics – VCC = 24 V .............................. 6 11.3 Receiving Notification of Documentation Updates 23
6.8 AC Characteristics – VCC = 12 V .............................. 6 11.4 Community Resources.......................................... 23
6.9 Typical Characteristics .............................................. 7 11.5 Trademarks ........................................................... 23
7 Detailed Description ............................................ 10 11.6 Electrostatic Discharge Caution ............................ 23
7.1 Overview ................................................................. 10 11.7 Glossary ................................................................ 23
7.2 Functional Block Diagram ....................................... 11 12 Mechanical, Packaging, and Orderable
Information ........................................................... 23

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision E (August 2012) to Revision F Page

• Added Device Information table, ESD Ratings table, Feature Description section, Device Functional Modes section,
Application and Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section....................................... 1

Changes from Revision D (July 2012) to Revision E Page

• Changed 0.1 mF to 0.1 µF and 220 mF to 220 µF .............................................................................................................. 20

• Changed 0.1 mF to 0.1 µF and 1 mF to 1 µF ...................................................................................................................... 21

Changes from Revision C (October 2010) to Revision D Page

• Added a 100-kΩ resistor to AVCC (Pin 14) and Note 1 to Figure 17................................................................................... 15

Changes from Revision B (August 2010) to Revision C Page

• Added < 10 V/ms to VI ............................................................................................................................................................ 4

Changes from Revision A (July 2010) to Revision B Page

• Replaced the Dissipations Ratings Table with the Thermal Information Table...................................................................... 5
• Changed the 220-nf capacitor rated for at least 25 V to 470-nF capacitor rated to at least 16 V ....................................... 19

Changes from Original (August 2009) to Revision A Page

• Added slew rate adjustment information .............................................................................................................................. 11

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5 Pin Configuration and Functions

PWP Package
28-Pin HTSSOP
Top View

SD 1 28 PVCC

FAULT 2 27 PVCC

GND 3 26 BSN

GND 4 25 OUTN

GAIN0 5 24 PGND

GAIN1 6 23 OUTN

AVCC 7 22 BSN

AGND 8 21 BSP

GVDD 9 20 OUTP

PLIMIT 10 19 PGND

INN 11 18 OUTP

INP 12 17 BSP

NC 13 16 PVCC

AVCC 14 15 PVCC

Not to scale

Pin Functions
PIN
I/O DESCRIPTION
NAME NO.
AGND 8 — Analog supply ground. Connect to the thermal pad.
Analog supply. A 100-kΩ resistor in series with AVCC is needed if the PVCC slew rate is greater than
AVCC 7 P
10 V/ms.
AVCC 14 P Connect AVCC supply to this pin.
BSP 17 I Bootstrap I/O for positive high-side FET.
BSP 21 I Bootstrap I/O for positive high-side FET.
BSN 22 I Bootstrap I/O for negative high-side FET.
BSN 26 I Bootstrap I/O for negative high-side FET.
Open-drain output used to display short-circuit or DC Detect Fault status. Voltage compliant to AVCC.
FAULT 2 O Short-circuit faults can be set to auto-recovery by connecting FAULT pin to SD pin. Otherwise both short-
circuit faults and DC Detect Faults must be reset by cycling PVCC.
GAIN0 5 I Gain select least significant bit. TTL logic levels with compliance to AVCC.
GAIN1 6 I Gain select most significant bit. TTL logic levels with compliance to AVCC.
GND 3 — Connect to local ground
GND 4 — Connect to local ground
High-side FET gate drive supply. Nominal voltage is 7 V. Can also be used as supply for PLILMIT divider.
GVDD 9 O
Add a 1-µF capacitor to ground at this pin.
INP 12 I Positive audio input. Biased at 3 V.
INN 11 I Negative audio input. Biased at 3 V.
NC 13 — Not connected

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Pin Functions (continued)

PIN
I/O DESCRIPTION
NAME NO.
OUTP 18 O Class-D H-bridge positive output.
OUTP 20 O Class-D H-bridge positive output.
OUTN 23 O Class-D H-bridge negative output.
OUTN 25 O Class-D H-bridge negative output.
PGND 24 — Power ground for the H-bridges.
PGND 19 — Power ground for the H-bridges.
Power limit level adjust. Connect directly to GVDD pin for no power limiting. Add a 1-µF capacitor to
PLIMIT 10 I
ground at this pin.
PVCC 15 P Power supply for H-bridge. PVCC pins are also connected internally.
PVCC 16 P Power supply for H-bridge. PVCC pins are also connected internally.
PVCC 27 P Power supply for H-bridge. PVCC pins are also connected internally.
PVCC 28 P Power supply for H-bridge. PVCC pins are also connected internally.
Shutdown logic input for audio amplifier (LOW = outputs Hi-Z, HIGH = outputs enabled). TTL logic levels
SD 1 I
with compliance to AVCC.

6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
Supply voltage, VCC AVCC, PVCC –0.3 30 V
–0.3 VCC + 0.3 V
SD, FAULT, GAIN0, GAIN1, AVCC (Pin 14) (2)
<10 V/ms
Interface pin voltage, VI
PLIMIT –0.3 VGVDD + 0.3
V
INN, INP –0.3 6.3
Minimum load resistance, RL BTL 3.2 Ω
Continuous total power dissipation See Thermal Information
Operating free-air temperature, TA –40 85 °C
Operating junction temperature, TJ (3) –40 150 °C
Storage temperature, Tstg –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The voltage slew rate of these pins must be restricted to no more than 10 V/ms. For higher slew rates, use a 100-kΩ resistor in series
with the pins.
(3) The TPA3111D1 incorporates an exposed thermal pad on the underside of the chip. This acts as a heatsink, and it must be connected
to a thermally dissipating plane for proper power dissipation. Failure to do so may result in the device going into thermal protection
shutdown. See Quad Flatpack No-Lead Logic Packages and QFN/SON PCB Attachment for more information about using the QFN
thermal pad. See PowerPad™ Thermally Enhanced package for more information about using the HTQFP thermal pad.

6.2 ESD Ratings

VALUE UNIT
(1)
Human-body model (HBM) ±2000
V(ESD) Electrostatic discharge V
Charged-device model (CDM) (2) ±500

(1) In accordance with JEDEC Standard 22, Test Method A114-B.

(2) In accordance with JEDEC Standard 22, Test Method C101-A

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6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VCC Supply voltage PVCC, AVCC 8 26 V
VIH High-level input voltage SD, GAIN0, GAIN1 2 V
VIL Low-level input voltage SD, GAIN0, GAIN1 0.8 V
VOL Low-level output voltage FAULT, RPULLUP = 100 kΩ, VCC = 26 V 0.8 V
IIH High-level input current SD, GAIN0, GAIN1, VI = 2 V, VCC = 18 V 50 µA
IIL Low-level input current SD, GAIN0, GAIN1, VI = 0.8 V, VCC = 18 V 5 µA

6.4 Thermal Information

TPA3111D1
THERMAL METRIC (1) (2) PWP (HTSSOP) UNIT
28 PINS
RθJA Junction-to-ambient thermal resistance 30.3 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 33.5 °C/W
RθJB Junction-to-board thermal resistance 17.5 °C/W
ψJT Junction-to-top characterization parameter 0.9 °C/W
ψJB Junction-to-board characterization parameter 7.2 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 0.9 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator.

6.5 DC Characteristics – VCC = 24 V

TA = 25°C, RL = 8 Ω (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Class-D output offset voltage (measured
|VOS| VI = 0 V, Gain = 36 dB 1.5 15 mA
differentially)
ICC Quiescent supply current SD = 2 V, no load, PVCC = 21 V 40 mA
ICC(SD) Quiescent supply current in shutdown mode SD = 0.8 V, no load, PVCC = 21 V 400 µA
High side 240
RDS(ON) Drain-source ON-state resistance IO = 500 mA, TJ = 25°C mΩ
Low side 240
VGAIN0 = 0.8 V 19 20 21
VGAIN1 = 0.8 V
VGAIN0 = 2 V 25 26 27
G Gain dB
VGAIN0 = 0.8 V 31 32 33
VGAIN1 = 2 V
VGAIN0 = 2 V 35 36 37
tON Turnon time VSD = 2 V 10 ms
tOFF Turnoff time VSD = 0.8 V 2 µs
VGVDD Gate drive supply IGVDD = 2 mA 6.5 6.9 7.3 V

6.6 DC Characteristics – VCC = 12 V

TA = 25°C, RL = 8 Ω (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Class-D output offset voltage (measured
|VOS| VI = 0 V, Gain = 36 dB 1.5 15 mA
differentially)
ICC Quiescent supply current SD = 2 V, no load, PVCC = 12 V 20 mA
ICC(SD) Quiescent supply current in shutdown mode SD = 0.8 V, no load, PVCC = 12 V 200 µA
High side 240
RDS(ON) Drain-source ON-state resistance IO = 500 mA, TJ = 25°C mΩ
Low side 240

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DC Characteristics – VCC = 12 V (continued)

TA = 25°C, RL = 8 Ω (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VGAIN0 = 0.8 V 19 20 21
VGAIN1 = 0.8 V
VGAIN0 = 2 V 25 26 27
G Gain dB
VGAIN0 = 0.8 V 31 32 33
VGAIN1 = 2 V
VGAIN0 = 2 V 35 36 37
tON Turnon time VSD = 2 V 10 ms
tOFF Turnoff time VSD = 0.8 V 2 µs
VGVDD Gate drive supply IGVDD = 2 mA 6.5 6.9 7.3 V
Output voltage maximum under PLIMIT
PLIMIT VPLIMIT = 2 V, VI = 6 V differential 6.75 7.9 8.75 V
control

6.7 AC Characteristics – VCC = 24 V

TA = 25°C, RL = 8 Ω (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
200-mVPP ripple from 20 Hz to 1 kHz,
KSVR Power supply ripple rejection –70 dB
Gain = 20 dB, Inputs AC-coupled to AGND
PO Continuous output power f = 1 kHz, VCC = 24 V, THD+N ≤ 0.1% 10 W
THD+N Total harmonic distortion + noise f = 1 kHz, VCC = 24 V, PO = 5 W (half-power) <0.05%
65 µV
VN Output integrated noise 20 Hz to 22 kHz, A-weighted filter, Gain = 20 dB
–80 dBV
Crosstalk f = 1 kHz, VO = 1 Vrms, Gain = 20 dB –70 dB
Maximum output at THD+N < 1%, f = 1 kHz,
SNR Signal-to-noise ratio 102 dB
Gain = 20 dB, A-weighted
fOSC Oscillator frequency 250 310 350 kHz
Thermal trip point 150 °C
Thermal hysteresis 15 °C

6.8 AC Characteristics – VCC = 12 V

TA = 25°C, RL = 8 Ω (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
200-mVPP ripple from 20 Hz to 1 kHz,
KSVR Power supply ripple rejection –70 dB
Gain = 20 dB, Inputs AC-coupled to AGND
f = 1 kHz, RL = 8 Ω, THD+N ≤ 10% 10
PO Continuous output power W
f = 1 kHz, RL = 4 Ω, THD+N ≤ 0.1% 10
THD+N Total harmonic distortion + noise f = 1 kHz, RL = 8 Ω, PO = 5 W (half-power) <0.06%
65 µV
VN Output integrated noise 20 Hz to 22 kHz, A-weighted filter, Gain = 20 dB
–80 dBV
Crosstalk f = 1 kHz, PO = 1 W, Gain = 20 dB –70 dB
Maximum output at THD+N < 1%, f = 1 kHz,
SNR Signal-to-noise ratio 102 dB
Gain = 20 dB, A-weighted
fOSC Oscillator frequency 250 310 350 kHz
Thermal trip point 150 °C
Thermal hysteresis 15 °C

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6.9 Typical Characteristics

All measurements taken at 1 kHz, unless otherwise noted. Measurements were made using the TPA3111D1 EVM.

10 10

THD − Total Harmonic Distortion − %

THD − Total Harmonic Distortion − %

1 1

0.1 0.1 PO = 1 W
PO = 1 W

0.01 0.01 PO = 10 W
PO = 5 W PO = 5 W
PO = 2.5 W
0.001 0.001
20 100 1k 10k 20k 20 100 1k 10k 20k
f − Frequency − Hz f − Frequency − Hz
G001 G002

Gain = 20 dB VCC = 12 V ZL = 8 Ω + 66 µH Gain = 20 dB VCC = 24 V ZL = 8 Ω + 66 µH

Figure 1. Total Harmonic Distortion vs Frequency Figure 2. Total Harmonic Distortion vs Frequency
10 10

THD+N − Total Harmonic Distortion + Noise − %

THD − Total Harmonic Distortion − %

1 1
PO = 5 W

f = 1 kHz
f = 20 Hz
0.1 PO = 10 W 0.1

0.01 0.01
PO = 1 W

f = 10 kHz

0.001 0.001
20 100 1k 10k 20k 0.01 0.1 1 10 20
f − Frequency − Hz PO − Output Power − W
G003 G004

Gain = 20 dB VCC = 12 V ZL = 4 Ω + 33 µH Gain = 20 dB VCC = 12 V ZL = 8 Ω + 66 µH

Figure 3. Total Harmonic Distortion vs Frequency Figure 4. Total Harmonic Distortion + Noise
vs Output Power
10 10
THD+N − Total Harmonic Distortion + Noise − %

THD+N − Total Harmonic Distortion + Noise − %

1 1

f = 1 kHz
f = 20 Hz f = 1 kHz f = 20 Hz
0.1 0.1

0.01 0.01

f = 10 kHz f = 10 kHz
0.001 0.001
0.01 0.1 1 10 20 0.01 0.1 1 10 20
PO − Output Power − W PO − Output Power − W
G005 G006

Gain = 20 dB VCC = 24 V ZL = 8 Ω + 66 µH Gain = 20 dB VCC = 12 V ZL = 4 Ω + 33 µH

Figure 5. Total Harmonic Distortion + Noise Figure 6. Total Harmonic Distortion + Noise
vs Output Power vs Output Power

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Typical Characteristics (continued)

All measurements taken at 1 kHz, unless otherwise noted. Measurements were made using the TPA3111D1 EVM.
25 20
PO(Max) − Maximum Output Power − W

20
15

PO − Output Power − W
15

10

10

5
5

0 0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 0.0 0.5 1.0 1.5 2.0
VPLIMIT − PLIMIT Voltage − V VPLIMIT − PLIMIT Voltage − V
G007 G008

Dashed line represents thermally limited region. Dashed line represents thermally limited region.
Gain = 20 dB VCC = 24 V ZL = 8 Ω + 66 µH Gain = 20 dB VCC = 12 V ZL = 4 Ω + 33 µH

Figure 7. Maximum Output Power vs PLIMIT Voltage Figure 8. Output Power vs PLIMIT Voltage
40 100 100
VCC = 12 V
90
35 50
Phase 80
30 0 VCC = 24 V
70
h − Efficiency − %

25 −50 60
Gain − dB

Phase − °

Gain
20 −100 50

40
15 −150
30
10 −200
20
5 −250 10

0 −300 0
10 100 1k 10k 100k 0 1 2 3 4 5 6 7 8 9 10
f − Frequency − Hz PO − Output Power − W
G009 G012

Gain = 20 dB VCC = 12 V ZL = 8 Ω + 66 µH Gain = 20 dB ZL = 8 Ω + 66 µH

CI = µF VI = 0.1 VRMS
Filter = Audio Precision AUX-0225

Figure 9. Gain/Phase vs Frequency Figure 10. Efficiency vs Output Power

100 1.2

90
1.0
80
ICC − Supply Current − A

70
0.8
h − Efficiency − %

60
VCC = 12 V
50 0.6

40
0.4
30

20 VCC = 24 V
0.2
10

0 0.0
0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 7 8 9 10
PO − Output Power − W PO(Tot) − Total Output Power − W
G013 G014

Gain = 20 dB VCC = 12 V ZL = 4 Ω + 33 µH Gain = 20 dB ZL = 8 Ω + 66 µH

Figure 11. Efficiency vs Output Power Figure 12. Supply Current vs Total Output Power

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Typical Characteristics (continued)

All measurements taken at 1 kHz, unless otherwise noted. Measurements were made using the TPA3111D1 EVM.
1.2 0

KSVR − Supply Ripple Rejection Ratio − dB

1.0 −20
ICC − Supply Current − A

0.8 −40

0.6 −60

0.4 −80

0.2 −100

0.0 −120
0 1 2 3 4 5 6 7 8 9 10 20 100 1k 10k 20k
PO(Tot) − Total Output Power − W f − Frequency − Hz
G015 G016

Gain = 20 dB VCC = 12 V ZL = 4 Ω + 33 µH Gain = 20 dB VCC = 12 V ZL = 8 Ω + 66 µH

Figure 13. Supply Current vs Total Output Power Figure 14. Supply Ripple Rejection Ratio vs Frequency

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7 Detailed Description

7.1 Overview
To facilitate system design, the TPA3111D1 requires only a single power supply from 8 V to 26 V for operation.
An internal voltage regulator provides suitable voltage levels for the gate driver, digital and low-voltage analog
circuitry. Additionally, all circuitry requiring a floating voltage supply, that is, the high-side gate drive, is
accommodated by built-in bootstrap circuitry with integrated bootstrap diodes requiring only an external capacitor
for each half-bridge. The audio signal path, including the gate drive and output stage is designed as identical,
independent full-bridges. Place all decoupling capacitors as close to their associated pins as possible. In general,
the physical loop with the power supply pins, decoupling capacitors and GND return path to the device pins must
be kept as short as possible and with as little area as possible to minimize induction (see TPA3111D1 Evaluation
Module for additional information).
For a properly functioning bootstrap circuit, a small ceramic capacitor must be connected from each bootstrap pin
(BSx) to the power-stage output pin (OUTx). When the power-stage output is low, the bootstrap capacitor is
charged through an internal diode connected between the gate-drive power-supply pin (GVDD) and the bootstrap
pins. When the power-stage output is high, the bootstrap capacitor potential is shifted above the output potential
and thus provides a suitable voltage supply for the high-side gate driver. In an application with PWM switching
frequencies approximately 310 kHz, TI recommends ceramic capacitors with at least 220-nF capacitance, size
0603 or 0805, for the bootstrap supply. These capacitors ensure sufficient energy storage, even during clipped
low frequency audio signals, to keep the high-side power stage FET (LDMOS) fully turned on during the
remaining part of its ON cycle. Pay special attention to the power-stage power supply; this includes component
selection, PCB placement, and routing. For optimal electrical performance, EMI compliance, and system
reliability, it is important that each PVCC pin is decoupled with ceramic capacitors placed as close as possible to
each supply pin. TI recommends following the PCB layout of the TPA3111D1 EVM. For additional information on
recommended power supply and required components, see Application and Implementation and Power Supply
Recommendations. The PVCC power supply must have low output impedance and low noise. The power-supply
ramp and SD release sequence is not critical for device reliability as facilitated by the internal power-on-reset
circuit, but TI recommends releasing SD after the power supply is settled for minimum turnon audible artifacts.

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7.2 Functional Block Diagram

GVDD
PVCC BSP
OUTP FB + PVCC
OUTP FB
± ± ±
INP Gain + + PWM Gate
Control ± PLIMIT Logic Drive OUTP
INN ±
+ + +
OUTN FB
±
FAULT PGND

SD
TTL
GAIN0 Buffer
Gain Control
GAIN1 Ramp
Generator
PLIMIT
PLIMIT
Reference
GVDD BSN
PVCC
AVCC PVCC
LDO
AVCC SC Detect
Regulator
GVDD Gate
Startup DC Detect OUTN
GVDD Biases and Drive
Protection
References Thermal
Logic OUTN FB
Detect

UVLO and PGND

OVLO
AGND

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7.3 Feature Description

7.3.1 Gain Setting Through GAIN0 and GAIN1 Inputs
The gain of the TPA3111D1 is set by two input pins, GAIN0 and GAIN1. The voltage slew rate of these gain
pins, along with SD and AVCC (pin 14), must be restricted to no more than 10 V/ms. For higher slew rates, use a
100-kΩ resistor in series with the pins.
The gains listed in Table 1 are realized by changing the taps on the input resistors inside the amplifier. This
causes the input impedance (ZI) to be dependent on the gain setting. The actual gain settings are controlled by
ratios of resistors, so the gain variation from part-to-part is small. However, the input impedance from part to part
at the same gain may shift by ±20% due to shifts in the actual resistance of the input resistors.
For design purposes, the input network must be designed assuming an input impedance of 7.2 kΩ, which is the
absolute minimum input impedance of the TPA3111D1. At the lower gain settings, the input impedance could
increase as high as 72 kΩ

Table 1. Gain Setting

INPUT IMPEDANCE
AMPLIFIER GAIN (dB)
GAIN1 GAIN0 (kΩ)
TYPICAL TYPICAL
0 0 20 60
0 1 26 30
1 0 32 15
1 1 36 9

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7.3.2 SD Operation
The TPA3111D1 employs a shutdown mode of operation designed to reduce supply current (ICC) to the absolute
minimum level during periods of nonuse for power conservation. The SD input pin must be held high (see
specification table for trip point) during normal operation when the amplifier is in use. Pulling SD low causes the
outputs to mute and the amplifier to enter a low-current state. Never leave SD unconnected, because amplifier
operation would be unpredictable.
For the best power-off pop performance, place the amplifier in the shutdown mode before removing the power
supply voltage.

7.3.3 PLIMIT
The voltage at pin 10 can used to limit the power to levels less than what is possible based on the supply rail.
Add a resistor divider from GVDD to ground to set the voltage at the PLIMIT pin. An external reference may also
be used if tighter tolerance is required. Also add a 1-µF capacitor from pin 10 to ground.
The PLIMIT circuit sets a limit on the output peak-to-peak voltage. This limit can be thought of as a virtual
voltage rail which is lower than the supply connected to PVCC. This virtual rail is 4 times the voltage at the
PLIMIT pin. This output voltage can be used to calculate the maximum output power for a given maximum input
voltage and speaker impedance.

Figure 15. PLIMIT Circuit Operation

The PLIMIT circuits sets a limit on the output peak-to-peak voltage. The limiting is done by limiting the duty cycle
to fixed maximum value. This limit can be thought of as a virtual voltage rail which is lower than the supply
connected to PVCC. This virtual rail is 4 times the voltage at the PLIMIT pin. This output voltage can be used to
calculate the maximum output power for a given maximum input voltage and speaker impedance.

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2
ææ RL ö ö
çç ç ÷ ´ VP ÷÷
è RL + 2 ´ RS ø
POUT =è ø for unclipped power
2 ´ RL

where
• RS is the total series resistance including RDS(on), and any resistance in the output filter.
• RL is the load resistance.
• VP is the peak amplitude of the output possible within the supply rail.
– VP = 4 × PLIMIT voltage if PLIMIT < 4 × VP
– POUT(10%THD) = 1.25 × POUT(unclipped) (1)

Table 2. PLIMIT Typical Operation

PLIMIT OUTPUT OUTPUT VOLTAGE
TEST CONDITIONS
VOLTAGE POWER (W) AMPLITUDE (VP-P)
VCC = 24 V, VIN=1 Vrms,
1.92 10 15
RL = 4 Ω, Gain=20 dB
VCC = 24 V, VIN = 1 Vrms,
1.24 5 10
RL = 4 Ω, Gain = 20 dB
VCC = 12 V , VIN = 1 Vrms,
1.75 10 15.3
RL = 4 Ω, Gain = 20 dB
VCC = 12 V, VIN = 1 Vrms,
1.2 5 10.3
RL = 4 Ω, Gain = 20 dB

7.3.4 GVDD Supply

The GVDD supply is used to power the gates of the output full bridge transistors. It can also used to supply the
PLIMIT voltage divider circuit. Add a 1-µF capacitor to ground at this pin.

7.3.5 DC Detect
TPA3111D1 has circuitry which protects the speakers from DC current that might occur due to defective
capacitors on the input or shorts on the printed-circuit board at the inputs. A DC Detect Fault is reported on the
FAULT pin as a low state. The DC Detect Fault also causes the amplifier to shutdown by changing the state of
the outputs to Hi-Z. To clear the DC Detect it is necessary to cycle the PVCC supply. Cycling SD does not clear
a DC Detect Fault.
A DC Detect Fault is issued when the output differential duty-cycle exceeds 14% (for example, 57% or –43%) for
more than 420 ms at the same polarity. This feature protects the speaker from large DC currents or AC currents
less than 2 Hz. To avoid nuisance faults due to the DC Detect circuit, hold the SD pin low at power-up until the
signals at the inputs are stable. Also, take care to match the impedance seen at the positive and negative input
to avoid nuisance DC Detect Faults.
The minimum differential input voltages required to trigger the DC Detect are shown in Table 3. The inputs must
remain at or above the voltage listed in the table for more than 420 ms to trigger the DC Detect.

Table 3. DC Detect Threshold

AV (dB) VIN (mV, DIFFERENTIAL)
20 112
26 56
32 28
36 17

7.3.6 Short-Circuit Protection and Automatic Recovery Feature

TPA3111D1 has protection from overcurrent conditions caused by a short circuit on the output stage. The short
circuit protection fault is reported on the FAULT pin as a low state. The amplifier outputs are switched to a Hi-Z
state when the short-circuit protection latch is engaged. The latch can be cleared by cycling the SD pin through
the low state.

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If automatic recovery from the short-circuit protection latch is desired, connect the FAULT pin directly to the SD
pin. This allows the FAULT pin function to automatically drive the SD pin low that clears the short-circuit
protection latch.

7.3.7 Thermal Protection

Thermal protection on the TPA3111D1 prevents damage to the device when the internal die temperature
exceeds 150°C. There is a ±15°C tolerance on this trip point from device to device. When the die temperature
exceeds the thermal set point, the device enters into the shutdown state and the outputs are disabled. This is not
a latched fault. The thermal fault is cleared once the temperature of the die is reduced by 15°C. The device
begins normal operation at this point with no external system interaction.
Thermal protection faults are NOT reported on the FAULT pin.

7.4 Device Functional Modes

7.4.1 TPA3111D1 Modulation Scheme
The TPA3111D1 uses a modulation scheme that allows operation without the classic LC reconstruction filter
when the amp is driving an inductive load. Each output is switching from 0 V to the supply voltage. The OUTP
and OUTN are in phase with each other with no input so that there is little or no current in the speaker. The duty
cycle of OUTP is greater than 50% and OUTN is less than 50% for positive output voltages. The duty cycle of
OUTP is less than 50% and OUTN is greater than 50% for negative output voltages. The voltage across the load
sits at 0 V throughout most of the switching period, greatly reducing the switching current, which reduces any I2R
losses in the load.

OUTP

OUTN
Output = 0 V
Differential +12 V
Voltage
0V
Across
Load -12 V

Current

OUTP

OUTN Output > 0 V

Differential +12 V
Voltage
0V
Across
-12 V
Load

Current

Figure 16. The TPA3111D1 Output Voltage and Current Waveforms into an Inductive Load

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8 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

8.1 Application Information

The TPA3111D1 is designed for use in stereo speakers like in televisions, monitors and laptops, and consumer
audio equipment. The TPA3111D1 can either be configured in stereo or mono mode, depending on output power
conditions. Depending on output power requirements and necessity for (speaker) load protection, the built-in
PLIMIT circuit can be used to control system power.

8.2 Typical Application

PVCC

0.1 μF

100 μF 1000 pF
100 kΩ
Control 1 28
SD PVCC
System
1 kΩ
2 27
FAULT PVCC
3 26
GND BSN
0.47 μF
4 25
GND OUTN
5 24
GAIN0 PGND
6 23 FB
AVCC GAIN1 OUTN
7 22 1000 pF
PVCC AVCC BSN
10 Ω 1 µF TPA3111D1
8 21
AGND BSP
1000 pF
1 µF 9 20
GVDD OUTP
FB
10 19
PLIMIT PGND
0.47 μF
1 µF 11 18
INN OUTP
Audio 12 17
INP BSP
Source
1 µF
13 16
NC PVCC
100 kΩ 0.1 μF
14 15
AVCC AVCC PVCC
GND 100 μF 1000 pF
29
PowerPAD

PVCC

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100-kΩ resistor is required if the PVCC slew rate is more than 10 V/ms.

Figure 17. Mono Class-D Amplifier With BTL Output

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Typical Application (continued)

8.2.1 Design Requirements
For this design example, use the parameters listed in Table 4 as the input parameters.

Table 4. Design Parameters

PARAMETER EXAMPLE VALUE
Input voltage range PVDD 8 V to 26 V
Ferrite bead + capacitor 120 Ω to 600 Ω at 1 MHz + 1 nF / 2.2 nF

8.2.2 Detailed Design Procedure

8.2.2.1 Ferrite Bead Filter Considerations

Using the Advanced Emissions Suppression Technology in the TPA3111D1 amplifier it is possible to design a
high efficiency, Class-D audio amplifier while minimizing interference to surrounding circuits. it is also possible to
accomplish this with only a low-cost ferrite bead filter. Carefully select the ferrite bead used in the filter.
One important aspect of the ferrite bead selection is the type of material used in the ferrite bead. Not all ferrite
material is alike, so it is important to select a material that is effective in the 10 MHz to 100 MHz range which is
key to the operation of the Class-D amplifier. Many of the specifications regulating consumer electronics have
emissions limits as low as 30 MHz. It is important to use the ferrite bead filter to block radiation in the 30 MHz
and above range from appearing on the speaker wires and the power supply lines which are good antennas for
these signals. The impedance of the ferrite bead can be used along with a small capacitor, approximately
1000 pF, to reduce the frequency spectrum of the signal to an acceptable level. For best performance, the
resonant frequency of the ferrite bead and capacitor filter must be less than 10 MHz.
The ferrite bead must be large enough to maintain its impedance at the peak currents expected for the amplifier.
Some ferrite bead manufacturers specify the bead impedance at a variety of current levels. It is possible to make
sure the ferrite bead maintains an adequate amount of impedance at the peak current the amplifier receives. If
these specifications are not available, it is also possible to estimate the bead current handling capability by
measuring the resonant frequency of the filter output at very low power and at maximum power. A change of
resonant frequency of less than 50% under this condition is desirable.
A high-quality ceramic capacitor is also required for the ferrite bead filter. A low-ESR capacitor with good
temperature and voltage characteristics works best.
Additional EMC improvements may be obtained by adding snubber networks from each of the Class-D outputs to
ground. Suggested values for a simple RC series snubber network would be 10 Ω in series with a 330-pF
capacitor. However, design of the snubber network is specific to every application and the design must take into
account the parasitic reactance of the printed-circuit board as well as the audio amp. Evaluate the stress on the
component in the snubber network, especially if the amp is running at high PVCC. Also, make sure the layout of
the snubber network is tight and returns directly to the PGND or the PowerPad beneath the chip.

8.2.2.2 Efficiency: LC Filter Required With the Traditional Class-D Modulation Scheme
The main reason that the traditional Class-D amplifier requires an output filter is that the switching waveform
results in maximum current flow. This causes more loss in the load, which causes lower efficiency. The ripple
current is large for the traditional modulation scheme, because the ripple current is proportional to voltage
multiplied by the time at that voltage. The differential voltage swing is 2 × VCC, and the time at each voltage is
half the period for the traditional modulation scheme. An ideal LC filter is required to store the ripple current from
each half cycle for the next half cycle, while any resistance causes power dissipation. The speaker is both
resistive and reactive, whereas an LC filter is almost purely reactive.
The TPA3111D1 modulation scheme has little loss in the load without a filter because the pulses are short and
the change in voltage is VCC instead of 2 × VCC. As the output power increases, the pulses widen, making the
ripple current larger. Ripple current could be filtered with an LC filter for increased efficiency, but for most
applications the filter is not required.
An LC filter with a cutoff frequency less than the Class-D switching frequency allows the switching current to flow
through the filter instead of the load. The filter has less resistance but higher impedance at the switching
frequency than the speaker, which results in less power dissipation, therefore increasing efficiency.

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8.2.2.3 When to Use an Output Filter for EMI Suppression

The TPA3111D1 has been tested with a simple ferrite bead filter for a variety of applications including long
speaker wires up to 125 cm and high power. The TPA3111D1EVM passes FCC Class-B specifications under
these conditions using twisted speaker wires. The size and type of ferrite bead can be selected to meet
application requirements. The filter capacitor can also be increased if necessary with some impact on efficiency.
There may be a few circuit instances where it is necessary to add a complete LC reconstruction filter. These
circumstances might occur if there are nearby circuits which are very sensitive to noise. In these cases a classic
second order Butterworth filter similar to those shown in Figure 18, Figure 19, and Figure 20 can be used.
33 mH
OUTP
C2
L1
1 mF

33 mH
OUTN
C3
L2
1 mF

Figure 18. Typical LC Output Filter, Cutoff Frequency of 27 kHz, Speaker Impedance = 8 Ω

15 mH
OUTP
L1 C2
2.2 mF

15 mH
OUTN
L2 C3
2.2 mF

Figure 19. Typical LC Output Filter, Cutoff Frequency of 27 kHz, Speaker Impedance = 4 Ω

Ferrite
Chip Bead
OUTP

1 nF
Ferrite
Chip Bead
OUTN

1 nF

Figure 20. Typical Ferrite Chip Bead Filter

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8.2.2.4 Input Resistance

Changing the gain setting can vary the input resistance of the amplifier from its smallest value, 9 kΩ ±20%, to the
largest value, 60 kΩ ±20%. As a result, if a single capacitor is used in the input high-pass filter, the –3-dB or
cutoff frequency may change when changing gain steps.

Zf

Ci
Zi
Input IN
Signal

The –3-dB frequency can be calculated using Equation 2. Use the ZI values given in Table 1.
1
f =
2p Zi Ci (2)

8.2.2.5 Input Capacitor, CI

In the typical application, an input capacitor (CI) is required to allow the amplifier to bias the input signal to the
proper DC level for optimum operation. In this case, CI and the input impedance of the amplifier (ZI) form a high-
pass filter with the corner frequency determined in Equation 3.

-3 dB

1
fc =
2p Zi Ci

fc (3)
The value of CI is important, as it directly affects the bass (low-frequency) performance of the circuit. Consider
the example where ZI is 60 kΩ and the specification calls for a flat bass response down to 20 Hz. Equation 3 is
reconfigured as Equation 4.
1
Ci =
2p Zi fc (4)
In this example, CI is 0.13 µF; so, a value of 0.15 µF would likely be chosen. If the gain is known and is constant,
use ZI from Table 1 to calculate CI. A further consideration for this capacitor is the leakage path from the input
source through the input network (CI) and the feedback network to the load. This leakage current creates a DC-
offset voltage at the input to the amplifier that reduces useful headroom, especially in high-gain applications. For
this reason, a low-leakage tantalum or ceramic capacitor is the best choice. If a ceramic capacitor is used, use a
high-quality capacitor with good temperature and voltage coefficient. An X7R type works well and if possible use
a higher voltage rating than required. This gives a better capacitance versus voltage characteristic. When
polarized capacitors are used, the positive side of the capacitor must face the amplifier input in most applications
as the DC level there is held at 3 V, which is likely higher than the source DC level. It is important to confirm the
capacitor polarity in the application. Additionally, lead-free solder can create DC-offset voltages and it is
important to ensure that boards are cleaned properly.

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8.2.2.6 BSN and BSP Capacitors

The full H-bridge output stage uses only NMOS transistors. Therefore, they require bootstrap capacitors for the
high side of each output to turn on correctly. A 470-nF ceramic capacitor, rated for at least 16 V, must be
connected from each output to its corresponding bootstrap input. Specifically, one 470-nF capacitor must be
connected from OUTP to BSP, and one 470-nF capacitor must be connected from OUTN to BSN. See Simplified
Application Diagram.
The bootstrap capacitors connected between the BSx pins and corresponding output function as a floating power
supply for the high-side N-channel power MOSFET gate drive circuitry. During each high-side switching cycle,
the bootstrap capacitors hold the gate-to-source voltage high enough to keep the high-side MOSFETs turned on.

8.2.2.7 Differential Inputs

The differential input stage of the amplifier cancels any noise that appears on both input lines of the channel. To
use the TPA3111D1 with a differential source, connect the positive lead of the audio source to the INP input and
the negative lead from the audio source to the INN input. To use the TPA3111D1 with a single-ended source, AC
ground the INP or INN input through a capacitor equal in value to the input capacitor on INN or INP and apply
the audio source to either input. In a single-ended input application, the unused input must be AC grounded at
the audio source instead of at the device input for best noise performance. For good transient performance, the
impedance at each of the two differential inputs must be the same.
The impedance at the inputs must be limited to an RC time constant of 1 ms or less if possible. This is to allow
the input DC-blocking capacitors to become completely charged during the 14-ms power-up time. If the input
capacitors are not allowed to completely charge, there is some additional sensitivity to component matching
which can result in pop if the input components are not well matched.

8.2.2.8 Using Low-ESR Capacitors

A real, as opposed to ideal, capacitor can be modeled simply as a resistor in series with an ideal capacitor. The
voltage drop across this resistor minimizes the beneficial effects of the capacitor in the circuit. The lower the
equivalent value of this resistance, the more the real capacitor behaves like an ideal capacitor.

8.2.3 Application Curves

10 10
THD+N − Total Harmonic Distortion + Noise − %

THD+N − Total Harmonic Distortion + Noise − %

1 1

f = 1 kHz f = 1 kHz
f = 20 Hz
f = 20 Hz
0.1 0.1

0.01 0.01

f = 10 kHz
f = 10 kHz
0.001 0.001
0.01 0.1 1 10 20 0.01 0.1 1 10 20
PO − Output Power − W PO − Output Power − W
G004 G005

Gain = 20 dB VCC = 12 V ZL = 8 Ω + 66 µH Gain = 20 dB VCC = 24 V ZL = 8 Ω + 66 µH

Figure 21. Total Harmonic Distortion + Noise Figure 22. Total Harmonic Distortion + Noise
vs Output Power vs Output Power

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10

THD+N − Total Harmonic Distortion + Noise − %

1

0.1 f = 1 kHz f = 20 Hz

0.01

f = 10 kHz
0.001
0.01 0.1 1 10 20
PO − Output Power − W
G006

Gain = 20 dB VCC = 12 V ZL = 8 Ω + 33 µH

Figure 23. Total Harmonic Distortion + Noise

vs Output Power

9 Power Supply Recommendations

The TPA3111D1 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling
to ensure that the output total harmonic distortion (THD) is as low as possible. Power supply decoupling also
prevents oscillations for long lead lengths between the amplifier and the speaker.
Optimum decoupling is achieved by using a network of capacitors of different types that target specific types of
noise on the power supply leads. For higher frequency transients due to parasitic circuit elements such as bond
wire and copper trace inductances as well as lead frame capacitance, a good-quality, low equivalent-series-
resistance (ESR) ceramic capacitor from 220 pF to 1000 pF works well. This capacitor must be placed as close
to the device PVCC pins and system ground (either PGND pins or PowerPad) as possible. For mid-frequency
noise due to filter resonances or PWM switching transients as well as digital hash on the line, another good-
quality capacitor typically 0.1 µF to 1 µF placed as close as possible to the device PVCC leads works best. For
filtering lower frequency noise signals, a larger aluminum electrolytic capacitor of 220 µF or greater placed near
the audio power amplifier works well. The 220-µF capacitor also serves as a local storage capacitor for supplying
current during large signal transients on the amplifier outputs. The PVCC pins provide the power to the output
transistors, so a 220-µF or larger capacitor must be placed on each PVCC pin. A 10-µF capacitor on the AVCC
pin is adequate. Also, a small decoupling resistor between AVCC and PVCC can be used to keep high
frequency, Class-D noise from entering the linear input amplifiers.

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10 Layout

10.1 Layout Guidelines

The TPA3111D1 can be used with a small, inexpensive ferrite bead output filter for most applications. However,
because the Class-D switching edges are very fast, take care when planning the layout of the printed-circuit
board. The following suggestions help to meet EMC requirements.
• Decoupling capacitors: The high-frequency decoupling capacitors must be placed as close to the PVCC and
AVCC pins as possible. Large, 220-µF or greater, bulk power supply decoupling capacitors must be placed
near the TPA3111D1 on the PVCC supplies. Local, high-frequency bypass capacitors must be placed as
close to the PVCC pins as possible. These capacitors can be connected to the thermal pad directly for an
excellent ground connection. Consider adding a small, good-quality, low-ESR ceramic capacitor from 220 pF
to 1000 pF and a larger mid-frequency capacitor from 0.1 µF to 1 µF also of good quality to the PVCC
connections at each end of the chip.
• Keep the current loop from each of the outputs through the ferrite bead and the small filter capacitor and back
to PGND as small and tight as possible. The size of this current loop determines its effectiveness as an
antenna.
• Output filter: The ferrite EMI filter (Figure 20) must be placed as close to the output pins as possible for the
best EMI performance. The LC filter (Figure 18 and Figure 19) must be placed close to the outputs. The
capacitors used in both the ferrite and LC filters must be grounded to power ground.
• Thermal Pad: The thermal pad must be soldered to the PCB for proper thermal performance and optimal
reliability. The dimensions of the thermal pad and thermal land must be 6.46 mm by 2.35 mm. Seven rows of
solid vias, three vias per row, 0.33-mm or 13-mils diameter, must be equally spaced underneath the thermal
land. The vias must connect to a solid copper plane, either on an internal layer or on the bottom layer of the
PCB. The vias must be solid vias, not thermal relief or webbed vias. See PowerPad™ Thermally Enhanced
package (SLMA002) for more information about using the HTSSOP thermal pad. For recommended PCB
footprints, see mechanical pages appended to the end of this data sheet.
For an example layout, see the TPA3111D1EVM Audio Amplifier Evaluation Board User's Guide (SLOU270).
The EVM documentation is available on the TI website at http://www.ti.com/tool/TPA3111D1EVM.

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10.2 Layout Example

100PF

100nF

1nF

1 28

2 27

3 26

4 25 0.47µF
FB
5 24

6 23 1nF
7 22

8 21
1PF
9 20 1nF

10 19
1PF FB
11 18 0.47µF
12 17

13 16

14 15

1nF

100nF
100PF

Top Layer Ground and Thermal Pad Via to Bottom Ground Plane

Pad to Top Layer Ground Pour Top Layer Signal Traces

Figure 24. BTL Layout Example

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11 Device and Documentation Support

11.1 Device Support

11.1.1 Development Support
For development support, see the following:
• TI PCB Thermal Calculator
• TPA3111D1EVM

11.2 Documentation Support

11.2.1 Related Documentation
For related documentation see the following:
• Quad Flatpack No-Lead Logic Packages (SCBA017)
• QFN/SON PCB Attachment (SLUA271)
• PowerPad™ Thermally Enhanced package (SLMA002)
• TPA3111D1EVM Audio Amplifier Evaluation Board User's Guide (SLOU270)

11.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.

11.4 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.

11.5 Trademarks
SpeakerGuard, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

TPA3111D1PWP ACTIVE HTSSOP PWP 28 50 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 TPA3111D1
& no Sb/Br)
TPA3111D1PWPR ACTIVE HTSSOP PWP 28 2000 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 TPA3111D1
& no Sb/Br)

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

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provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 6-Feb-2020

OTHER QUALIFIED VERSIONS OF TPA3111D1 :

• Automotive: TPA3111D1-Q1

NOTE: Qualified Version Definitions:

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 26-Feb-2019

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPA3111D1PWPR HTSSOP PWP 28 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 26-Feb-2019

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPA3111D1PWPR HTSSOP PWP 28 2000 350.0 350.0 43.0

Pack Materials-Page 2
 GENERIC PACKAGE VIEW
TM
PWP 28 PowerPAD TSSOP - 1.2 mm max height
4.4 x 9.7, 0.65 mm pitch SMALL OUTLINE PACKAGE

Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4224765/A

www.ti.com
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