Basics of SPI: Timing Requirements

and Switching Characteristics

TIPL 6002
TI Precision Labs – Digital Communications
Presented by Alex Smith
Prepared by Joseph Wu

1
SPI Communication
A timing diagram shows the specifications and the
timing relationship between the SPI digital lines
CONTROLLER PERIPHERAL CS
SS CS

SCLK SCLK

MOSI DIN SCLK

MISO DOUT

DIN
Names commonly
used in TI devices
DOUT

Violating a timing specification can cause a failure

to read the data and may cause unexpected results.

2
SPI Timing: Setup Time Example is SPI mode 0:
SCLK idles low and data
is clocked in on the
leading edge of SCLK
Setup time
SCLK

Here, a 1 is
clocked into
Hold time DIN the device

Propagation Delay DOUT

tSU

The state of DIN is read into the device at Setup time is the minimum time required
the rising edge of SCLK. To ensure the data before the clocking edge for which the
is correctly read, DIN must be at the correct data must be stable to be latched correctly
state for a setup time before the SCLK rises

3
SPI Timing: Hold Time

Setup time
SCLK

1 is clocked
into the device
Hold time DIN here also

Propagation Delay DOUT

tHOLD

Again, the state of DIN is read into the Hold time is the minimum time required
device at the rising edge of SCLK. after the clocking edge for which the data
DIN must be held at the correct state must be stable to be latched correctly
for a hold time after the SCLK rises

4
SPI Switching: Propagation Delay
The falling edge of
SCLK sets up the
data on DOUT
Setup time
SCLK

Hold time DIN

Propagation Delay DOUT

tDELAY

DOUT is read by the controller at the rising Propagation delay is the time required
edge of SCLK. However, the peripheral for an input change to cause an output
sets the output at the previous falling edge change through the digital circuitry
of SCLK. This delay from one clock event
to the response is a propagation delay.

5
 SPI Timing Timing Requirements
are typically setup
Timing Requirements times and hold times
and Switching
Characteristics
example from the
ADS1118

Switching Characteristics
are typically propagation
delays

6
SPI Timing Diagram

Timing diagram for the

ADS1118
Device uses SPI Mode 1:
SCLK idles low, data
clocked in at falling edge
of SCLK
Boxes for DIN and DOUT
are high or low data
Arrows enclose timing
specifications

7
SPI Timing Diagram

tCSH
Minimum pulse duration,
CS high
This time defines the time
required for the CS to
stay high to ensure that
the device has reset the
SPI communications.

8
SPI Timing Diagram

tCSSC
CS low to first SCLK high
This time defines the time
required for the CS to
stay high to ensure that
the device recognizes it
is the peripheral.
A violation may cause the
device to miss the first
SCLK pulse

9
SPI Timing Diagram

tSCLK
The minimum time for an
SCLK period
SCLKs can be sent to a
device only so fast before
the device fails to
recognize it. This defines
the minimum time for
SCLK.
1/tSCLK is the SCLK
frequency

10
SPI Timing Diagram

tSPWH, tSPWH
The minimum time for an
SCLK high and the
minimum time for an
SCLK low
These two times with tSCLK
define how much skew in
the SCLK duty cycle is
allowed
For this device, there is a
maximum tSPWL for SPI
timeout

11
SPI Timing Diagram

tSCCS
Time from the falling
edge of SCLK to the
rising edge of CS
Because CS disables the
SPI, ensure that the
device receives the last
bit of data before shutting
down SPI communication
A violation of this could
cause the device to miss
the last data transmission

12
SPI Timing Diagram

tSCSC
Time from the falling
edge of SCLK to the
rising edge of SCLK in
the next CS
This time is required to
execute the command
from one CS period, to
start a new command in
another CS period

13
SPI Timing Diagram

tDIST
Setup time from the rising
edge of DIN to the falling
edge of SCLK
For data to be read into
the device, the DIN must
first be established for a
time period before the
SCLK falling edge.

14
SPI Timing Diagram

tDIHD
Hold time from the falling
edge of SCLK to the
falling edge of DIN.
Once the data is set onto
the DIN line, the SCLK
falling edge latches the
data into the device.
However, there is a
required time for the data
to be held after the SCLK
falling edge

15
SPI Timing Diagram

tCSDOD
Propagation delay time
from CS falling to DOUT
actively driven
When CS is high, the
DOUT is high impedance
or Hi-Z, allowing for
multiple devices on the
bus to drive DOUT a
device at a time.
When CS goes low,
DOUT is actively driven

16
SPI Timing Diagram

tDOPD
Propagation delay time
from rising edge of SCLK
to data appearing on
DOUT
SCLK is used to clock out
data from the device.
When SCLK is driven
high, this signals to the
device that data should
be put on DOUT that can
be clocked out on the
falling edge of DOUT

17
SPI Timing Diagram

tDOHD
Propagation delay time
from rising edge of SCLK
to data changing on
DOUT
This defines the time for
which the last data is still
valid once the rising edge
of SCLK occurs

18
SPI Timing Diagram

tCSDOZ
Propagation delay time
from rising edge of CS to
DOUT becoming Hi-Z

19
Thanks for your time!
Please try the quiz.

20
Quiz: Basics of SPI: Timing Diagram
1. The following diagram is CPOL = 0, CPHA = 1. Data is clocked in on the
falling edge of SCLK. DIN must be stable for a time after the SCLK falling
edge. This timing is an example of which timing requirement?
a. Setup time
b. Hold time SCLK
c. Propagation delay
d. None of the above
DIN

DOUT

21
Quiz: Basics of SPI: Timing Diagram
1. The following diagram is CPOL = 0, CPHA = 1. Data is clocked in on the
falling edge of SCLK. DIN must be stable for a time after the SCLK falling
edge. This timing is an example of which timing requirement?
a. Setup time
b. Hold time SCLK
c. Propagation delay
d. None of the above
DIN

DOUT

22
Quiz: Basics of SPI: Timing Diagram
2. The following diagram is CPOL = 0, CPHA = 1. DIN and DOUT are read on
the falling edge of SCLK. However, DOUT is set up on the rising edge of
SCLK, and there may be time required for the data to arrive on DOUT. This
timing is an example of which timing requirement?
a. Setup time
SCLK
b. Hold time
c. Propagation delay
d. None of the above DIN

DOUT

23
Quiz: Basics of SPI: Timing Diagram
2. The following diagram is CPOL = 0, CPHA = 1. DIN and DOUT are read on
the falling edge of SCLK. However, DOUT is set up on the rising edge of
SCLK, and there may be time required for the data to arrive on DOUT. This
timing is an example of which timing requirement?
a. Setup time
SCLK
b. Hold time
c. Propagation delay
d. None of the above DIN

DOUT

24
Quiz: Basics of SPI: Timing Diagram
3. The following diagram is CPOL = 0, CPHA = 1. Data is clocked in on the
falling edge of SCLK. DIN must be stable for a time before the falling edge of
SCLK. This timing is an example of which timing requirement?
a. Setup time
b. Hold time SCLK
c. Propagation delay
d. None of the above
DIN

DOUT

25
Quiz: Basics of SPI: Timing Diagram
3. The following diagram is CPOL = 0, CPHA = 1. Data is clocked in on the
falling edge of SCLK. DIN must be stable for a time before the falling edge of
SCLK. This timing is an example of which timing requirement?
a. Setup time
b. Hold time SCLK
c. Propagation delay
d. None of the above
DIN

DOUT

26
Thanks for your time!

27
© Copyright 2020 Texas Instruments Incorporated. All rights reserved.
This material is provided strictly “as-is,” for informational purposes only, and without any warranty.
Use of this material is subject to TI’s , viewable at TI.com
Basics of SPI: Timing Requirements
and Switching Characteristics
TIPL 6002
TI Precision Labs – Digital Communications
Presented by Alex Smith
Prepared by Joseph Wu

Hello, and welcome to our in-depth look at communications with precision data
converters. In this video, we describe the timing requirements and switching
characteristics between digital lines associated with Serial Peripheral Interface or SPI
communication. We'll discuss timing and switching specifications that you may see in a
datasheet. Then we'll describe an example of the timing diagram for one of TI’s
precision data converters.

1
SPI Communication
A timing diagram shows the specifications and the
timing relationship between the SPI digital lines
CONTROLLER PERIPHERAL CS
SS CS

SCLK SCLK

MOSI DIN SCLK

MISO DOUT

DIN
Names commonly
used in TI devices
DOUT

Violating a timing specification can cause a failure

to read the data and may cause unexpected results.

In a previous video, we discussed how data is clocked into and out of precision data
converters using the four digital lines of SPI. An active low peripheral select line,
commonly known as Chip Select is used to select the device for communication. A serial
clock of SCLK clocks data in and out of the peripheral device to the controller. Finally
data lines of MOSI and MISO, commonly named DIN and DOUT for the peripheral
device are used to send the data.

For all of these digital lines, there are specifications that define the time required from
the change of one digital line to another. Many of these specifications are related to the
time between the changes in the data of the DIN and DOUT lines to SCLK. These
specifications ensure that the data is properly clocked into and out of the digital
sections of the controller and peripheral device.

Regardless, all timing specifications must be followed to ensure that the controller and
peripheral device are properly sending and receiving data. Violating a timing
specification can cause failure to read the data and may cause unexpected results.

2
SPI Timing: Setup Time Example is SPI mode 0:
SCLK idles low and data
is clocked in on the
leading edge of SCLK
Setup time
SCLK

Here, a 1 is
clocked into
Hold time DIN the device

Propagation Delay DOUT

tSU

The state of DIN is read into the device at Setup time is the minimum time required
the rising edge of SCLK. To ensure the data before the clocking edge for which the
is correctly read, DIN must be at the correct data must be stable to be latched correctly
state for a setup time before the SCLK rises

Most timing specifications can be categorized into one of three categories. They are
setup times, hold times, or propagation delays. Using this timing diagram, we show the
SCLK, DIN, and DOUT of a peripheral device. Using SPI mode 0, the SCLK idles low and
the data is clocked in on the rising edge of the SCLK.

First, setup time is the time required for a data input to be stable before the edge of the
clocking signal to be latched correctly. In the diagram, the example is SPI mode 0,
where SCLK idles low and the data is clocked in on the rising edge of SCLK. DIN is set
high so that at the rising edge of SCLK a 1 is clocked into the peripheral device. DIN
must be set high first and it must stay high for a specific setup time so that the 1 is
properly received.

3
SPI Timing: Hold Time

Setup time
SCLK

1 is clocked
into the device
Hold time DIN here also

Propagation Delay DOUT

tHOLD

Again, the state of DIN is read into the Hold time is the minimum time required
device at the rising edge of SCLK. after the clocking edge for which the data
DIN must be held at the correct state must be stable to be latched correctly
for a hold time after the SCLK rises

Second, hold time is the time required for a data input to be held at the proper level
after the clocking signal. In the diagram, DIN is already set high, and then the SCLK rises
to clock in the signal. DIN must stay high for a hold time after the clock rises to ensure
that the 1 again is properly received.

4
SPI Switching: Propagation Delay
The falling edge of
SCLK sets up the
data on DOUT
Setup time
SCLK

Hold time DIN

Propagation Delay DOUT

tDELAY

DOUT is read by the controller at the rising Propagation delay is the time required
edge of SCLK. However, the peripheral for an input change to cause an output
sets the output at the previous falling edge change through the digital circuitry
of SCLK. This delay from one clock event
to the response is a propagation delay.

Lastly, there are propagation delays. This term describes the time required for the signal
from one line to change the signal from another.

In the diagram, the SCLK comes into the device, and the controller reads DOUT on the
rising edge of the clock. For the peripheral device, the falling edge of the clock sets up
the next data bit so that by the rising edge of the clock when the controller reads the
device, the correct data is on DOUT. This delay time describes how long it takes from
the SCLK falling edge to place the data on the DOUT line.

5
 SPI Timing Timing Requirements
are typically setup
Timing Requirements times and hold times
and Switching
Characteristics
example from the
ADS1118

Switching Characteristics
are typically propagation
delays

Here we can take an in-depth look at SPI timing from an example datasheet. Using the
ADS1118 precision ADC, two tables show the Timing Requirements and the Switching
Characteristics. Typically, timing requirements show setup and hold times for the SPI
communications and the switching characteristics will show propagation delays. These
tables will give minimum and maximum times for different characteristics shown in a
timing diagram.

6
SPI Timing Diagram

Timing diagram for the

ADS1118
Device uses SPI Mode 1:
SCLK idles low, data
clocked in at falling edge
of SCLK
Boxes for DIN and DOUT
are high or low data
Arrows enclose timing
specifications

Continuing with the example, here is the timing diagram. We can go through the
specifications and explain how to read them. The timing diagram shows specific timing
requirements between the different digital lines. For all digital communications, this
timing must be followed, or the device may not recognize commands, fail to understand
the configuration settings, or properly output data.

We’ll cover each of these specifications, and explain what they mean.

7
SPI Timing Diagram

tCSH
Minimum pulse duration,
CS high
This time defines the time
required for the CS to
stay high to ensure that
the device has reset the
SPI communications.

tCSH is the hold time of chip select. This is the minimum amount of time that chip
select can be held high that ensures that the device recognizes that the chip select has
been set high and low again. Here, it does not appear to be a hold time because it does
not come before a clock signal in the diagram. However, this timing is internal and
defines a hold time based on latching the CS signal to an internal clock.

8
SPI Timing Diagram

tCSSC
CS low to first SCLK high
This time defines the time
required for the CS to
stay high to ensure that
the device recognizes it
is the peripheral.
A violation may cause the
device to miss the first
SCLK pulse

tCSSC is the minimum time required between chip select transitioning low and the first
SCLK. As chip select is taken low, it still takes a small amount of time for the device to
determine that it is the active peripheral. This also allows for time to setup data that
the device needs to send out on DOUT at the first SCLK rising edge pulse.

9
SPI Timing Diagram

tSCLK
The minimum time for an
SCLK period
SCLKs can be sent to a
device only so fast before
the device fails to
recognize it. This defines
the minimum time for
SCLK.
1/tSCLK is the SCLK
frequency

10

tSCLK is the SCLK period. SCLK must have a minimum period to ensure proper digital
timing. Transistors and logic gates can’t be clocked infinitely fast, so there is a limit to
how fast data can be clocked out.

10
SPI Timing Diagram

tSPWH, tSPWH
The minimum time for an
SCLK high and the
minimum time for an
SCLK low
These two times with tSCLK
define how much skew in
the SCLK duty cycle is
allowed
For this device, there is a
maximum tSPWL for SPI
timeout

11

tSPWH and tSPWL are the minimum time periods for the SCLK pulse high and low. This
is similar to the total minimum SCLK period, but it really describes the acceptable duty
cycle and skew of the SCLK signal.

For this timing specification, there is an additional limit. The timing requirement table
lists a maximum tSPWL time of 28ms. This maximum time comes from a timeout built
into the SPI communications of this device.

11
SPI Timing Diagram

tSCCS
Time from the falling
edge of SCLK to the
rising edge of CS
Because CS disables the
SPI, ensure that the
device receives the last
bit of data before shutting
down SPI communication
A violation of this could
cause the device to miss
the last data transmission

12

tSCCS is the minimum time from the last SCLK falling edge to the rising edge of chip
select. This is a specification required for clocking in data to the device. Because chip
select disables the SPI communication, any data must be clocked into the device with
the falling edge of SCLK before chip select rises. It is a hold time for the data with SCLK
and a setup time for the chip select to the device's internal clock.

12
SPI Timing Diagram

tSCSC
Time from the falling
edge of SCLK to the
rising edge of SCLK in
the next CS
This time is required to
execute the command
from one CS period, to
start a new command in
another CS period

13

tSCSC is the time required between the last falling edge of SCLK from one command to
the next rising edge of SCLK for the next command. For the device, there is some time
required to parse and execute a command in one chip select frame before being able to
take another command from another chip select frame.

13
SPI Timing Diagram

tDIST
Setup time from the rising
edge of DIN to the falling
edge of SCLK
For data to be read into
the device, the DIN must
first be established for a
time period before the
SCLK falling edge.

14

tDIST is the setup time for the DIN data. In this diagram, the communication uses SPI
mode 1, where the SCLK idles low and data are clocked in on the falling edge of SCLK.
Here, the DIN is typically set up on the rising edge of SCLK, but this defines a minimum
time that DIN must be valid before the falling edge of SCLK.

Again, this device is SPI mode 1, where the data is clocked in at the falling edge of SCLK.
The setup time is the time required for DIN to be stable, before the active falling SCLK
edge.

14
SPI Timing Diagram

tDIHD
Hold time from the falling
edge of SCLK to the
falling edge of DIN.
Once the data is set onto
the DIN line, the SCLK
falling edge latches the
data into the device.
However, there is a
required time for the data
to be held after the SCLK
falling edge

15

tDIHD is the hold time for the DIN data. When the data is clocked in on the falling edge
of SCLK, DIN must be stable from the setup time before and the hold time after the
SCLK falling edge.

15
SPI Timing Diagram

tCSDOD
Propagation delay time
from CS falling to DOUT
actively driven
When CS is high, the
DOUT is high impedance
or Hi-Z, allowing for
multiple devices on the
bus to drive DOUT a
device at a time.
When CS goes low,
DOUT is actively driven

16

tCSDOD is the time from the falling edge of chip select to the enabling of DOUT. When
chip select is high, the DOUT of the peripheral device is high impedance, or Hi-Z. This
prevents an inactive peripheral device from trying to drive the DOUT line. When chip
select is driven low, DOUT is driven by the active peripheral. tCSDOD shows the
propagation delay from the chip select going low to when the DOUT is active.

16
SPI Timing Diagram

tDOPD
Propagation delay time
from rising edge of SCLK
to data appearing on
DOUT
SCLK is used to clock out
data from the device.
When SCLK is driven
high, this signals to the
device that data should
be put on DOUT that can
be clocked out on the
falling edge of DOUT

17

tDOPD is the maximum propagation delay time from the rising edge of SCLK to the data
appearing on DOUT. Again, data is clocked out by the controller on the falling edge of
SCLK, so the rising edge of SCLK is used by the device to send data to DOUT.

17
SPI Timing Diagram

tDOHD
Propagation delay time
from rising edge of SCLK
to data changing on
DOUT
This defines the time for
which the last data is still
valid once the rising edge
of SCLK occurs

18

tDOHD is the propagation delay time from the SCLK rising edge to when DOUT becomes
invalid. Again, DOUT is set up on the rising edge of SCLK so that it can be read out on
the falling edge of SCLK. However, if you choose to read the data, you have until tDOHD
after the next rising edge of SCLK to read the data.

This specification isn’t important if the data is read on the falling edge of SCLK.

18
SPI Timing Diagram

tCSDOZ
Propagation delay time
from rising edge of CS to
DOUT becoming Hi-Z

19

tCSDOZ is the time from the rising edge of chip select to when DOUT returns to high
impedance. Similar to tCSDOD, this is important when there are peripheral multiple
devices on the SPI bus.

19
 Thanks for your time!
Please try the quiz.

20

That concludes this video – thank you for watching! Please try the quiz to check your
understanding of this video’s content.

20
Quiz: Basics of SPI: Timing Diagram
1. The following diagram is CPOL = 0, CPHA = 1. Data is clocked in on the
falling edge of SCLK. DIN must be stable for a time after the SCLK falling
edge. This timing is an example of which timing requirement?
a. Setup time
b. Hold time SCLK
c. Propagation delay
d. None of the above
DIN

DOUT

21

21
Quiz: Basics of SPI: Timing Diagram
1. The following diagram is CPOL = 0, CPHA = 1. Data is clocked in on the
falling edge of SCLK. DIN must be stable for a time after the SCLK falling
edge. This timing is an example of which timing requirement?
a. Setup time
b. Hold time SCLK
c. Propagation delay
d. None of the above
DIN

DOUT

22

B. Hold time. The SCLK is clocks in data on a falling edge. Here we see that we want to
clock in DIN to the peripheral on the SCLK falling edge. This timing diagram shows the
amount of time that is required to hold DIN after the falling edge of SCLK.

22
Quiz: Basics of SPI: Timing Diagram
2. The following diagram is CPOL = 0, CPHA = 1. DIN and DOUT are read on
the falling edge of SCLK. However, DOUT is set up on the rising edge of
SCLK, and there may be time required for the data to arrive on DOUT. This
timing is an example of which timing requirement?
a. Setup time
SCLK
b. Hold time
c. Propagation delay
d. None of the above DIN

DOUT

23

23
Quiz: Basics of SPI: Timing Diagram
2. The following diagram is CPOL = 0, CPHA = 1. DIN and DOUT are read on
the falling edge of SCLK. However, DOUT is set up on the rising edge of
SCLK, and there may be time required for the data to arrive on DOUT. This
timing is an example of which timing requirement?
a. Setup time
SCLK
b. Hold time
c. Propagation delay
d. None of the above DIN

DOUT

24

C. Propagation delay. In this diagram data is set up on the rising edge of the SCLK and
clocked in the peripheral or controller on the falling edge. Here, the SCLK rising edge
tells the peripheral to get the data out to DOUT so that it can be latched into the
controller on the falling edge. This is a propagation delay showing the amount of time
required from the rising edge of SCLK to get data out on DOUT.

24
Quiz: Basics of SPI: Timing Diagram
3. The following diagram is CPOL = 0, CPHA = 1. Data is clocked in on the
falling edge of SCLK. DIN must be stable for a time before the falling edge of
SCLK. This timing is an example of which timing requirement?
a. Setup time
b. Hold time SCLK
c. Propagation delay
d. None of the above
DIN

DOUT

25

25
Quiz: Basics of SPI: Timing Diagram
3. The following diagram is CPOL = 0, CPHA = 1. Data is clocked in on the
falling edge of SCLK. DIN must be stable for a time before the falling edge of
SCLK. This timing is an example of which timing requirement?
a. Setup time
b. Hold time SCLK
c. Propagation delay
d. None of the above
DIN

DOUT

26

A. Setup time. Data is latched on the falling edge of SCLK. This setup time defines how
much time is required to that the DIN is set and stable before the falling edge of SCLK.

26
Thanks for your t

27
© Copyright 2020 Texas Instruments Incorporated. All rights reserved.
This material is provided strictly “as-is,” for informational purposes only, and without any warranty.
Use of this material is subject to TI’s , viewable at TI.com

28