SERIAL PERIPHERAL INTERFACE(SPI)

Introduction to SPI
The Serial Peripheral Interface (SPI) is a widely used synchronous serial
communication protocol designed for short-distance communication. It was
developed by Motorola and is commonly used in embedded systems for
communication between microcontrollers and peripheral devices like sensors,
memory devices, and display modules. SPI operates in full-duplex mode,
meaning data can be transmitted and received simultaneously.

In this protocol, devices are communicated in the master-slave relationship. The

master device controls the slave device, and the slave device takes the instruction
from the master device. The simplest configuration of the Serial Peripheral
Interface (SPI) is a combination of a single slave and a single master. But, one
master device can control multiple slave devices.

Key Features of SPI:

• Full-Duplex Communication: Both master and slave can send and receive
data simultaneously.
• Multiple Slave Support: Although SPI supports multiple slaves, only one
slave can communicate with the master at a time.
• Configurable Clock Polarity (CPOL) and Phase (CPHA): These
settings allow for flexibility in timing and synchronization.
• High-Speed Communication: SPI can achieve data transfer rates up to 20
Mbps, making it suitable for high-speed applications.

SPI Interface:
The SPI bus typically consists of four primary signals:

• MOSI (Master Out Slave In): This line carries data from the master to
the slave.
• MISO (Master In Slave Out): This line carries data from the slave to the
master.
• SCK (Serial Clock): This clock signal is generated by the master to
synchronize data transmission.
• SS/CS (Slave Select/Chip Select): This signal is used to select the slave
device that will communicate with the master.
SPI Modes
SPI can operate in four different modes, defined by the clock polarity (CPOL)
and clock phase (CPHA) settings. These modes determine when data is sampled
and shifted relative to the clock signal.

1. Mode 0 (CPOL = 0, CPHA = 0):

o Clock polarity is low when idle.
o Data is sampled on the rising edge of the clock.
2. Mode 1 (CPOL = 0, CPHA = 1):
o Clock polarity is low when idle.
o Data is sampled on the falling edge of the clock.
3. Mode 2 (CPOL = 1, CPHA = 0):
o Clock polarity is high when idle.
o Data is sampled on the falling edge of the clock.
4. Mode 3 (CPOL = 1, CPHA = 1):
o Clock polarity is high when idle.
o Data is sampled on the rising edge of the clock.

These modes ensure that the master and slave devices are properly synchronized
for data transfer.
How SPI Works
SPI communication involves a master device and one or more slave devices. The
master initiates the communication by generating the clock signal (SCK) and
selecting the slave device using the SS/CS line.

1. Initialization:
o The master configures the SPI peripheral, setting the clock speed,
polarity, phase, and frame format (8-bit or 16-bit).
2. Data Transmission:
o The master pulls the SS/CS line low to select the slave.
o Data is loaded into the SPI data register.
o The master generates the clock signal.
o On each clock edge (rising or falling, depending on the mode), data
bits are shifted out from the MOSI line and into the MISO line.
o After 8 or 16 clock pulses, the data transfer is complete.
3. Data Reception:
o Data is simultaneously received from the slave on the MISO line
while the master transmits on the MOSI line.
o The received data is stored in the SPI data register.

4. Completion:
o The master pulls the SS/CS line high to deselect the

slave.
o The received data is read from the SPI data register.
This process allows for efficient and high-speed
communication between the master and slave devices.
Single Master and Multiple Slave Implementations
This is a multiple slave configuration with one master and multiple slaves through
the SPI serial bus. The multiple slaves are connected in parallel to the master
device with the SPI serial bus. Here, all the clock lines and data lines are
connected together, but the chip select pin from each slave device must be
connected to a separate slave select pin on the maser device.

STM32F401RBT6 SPI Features

The STM32F401RBT6 microcontroller includes several SPI interfaces with the
following features:

• Full-Duplex Synchronous Transfers: Allows simultaneous transmission

and reception of data.
• Simplex Synchronous Transfers: Can operate with two lines, using either
MOSI or MISO.
• 8- or 16-bit Transfer Frame Format: Configurable data frame size.
• Master or Slave Operation: Can function as either a master or a slave
device.
 • Programmable Clock Polarity and Phase: Provides flexibility in timing
and synchronization.
• NSS Management: Can be managed by hardware or software to select the
slave device.
• Interrupt Capability: Supports interrupts for transmission and reception
events.
• DMA Capability: Can use Direct Memory Access (DMA) for efficient
data transfer without CPU intervention.

Example Configuration for STM32F401RBT6

Below is an example configuration for initializing SPI on the STM32F401RBT6
microcontroller:

#define RCC_AHB1ENR *((int *)0x40023830)

#define RCC_APB2ENR *((int *)0X40023844)
#define GPIOA_MODE *((int *)0X40020000)
#define SPI1_CR1 *((int *)0X40013000)
#define GPIOA_AFRL *((int *)0X40020020)
#define SPI1_DR *((int *)0X4001300C)
#define SPI1_SR *((int *)0X40013008)

void Init(void)
{
RCC_AHB1ENR |= 0x01<<0; //set 1st bit to enable port a clock
while(!(RCC_AHB1ENR & 0x01)); //wait until port a clock is set
RCC_APB2ENR |= 0X01<<12;
while(!(RCC_APB2ENR & (0x01<<12)));
}
void config(void)
{
GPIOA_MODE &= 0XFFFF00FF;
GPIOA_MODE |= 0X0000AA00;
GPIOA_AFRL &= 0X0000FFFF;
GPIOA_AFRL |= 0X55550000;
SPI1_CR1 &= ~(0X38);
SPI1_CR1 &= ~(0X0800);
SPI1_CR1 |= 0X344;
//SPI1_CR1 |= (0X01<<6);
SPI1_CR1 |= (0X300);
SPI1_CR1 |= (0X44);
//SPI1_CR1 |= (0X01<<9);
}
This code snippet demonstrates how to enable the SPI peripheral clock,
configure the GPIO pins for SPI functionality, set the SPI parameters, and
enable the SPI peripheral.

STM32 SPI Block Diagram:

As you can see in the SPI block diagram above, there is the main shift register
lying between two buffer registers one for transmission (TX) and the other for
reception (RX). And a logical control unit on the right side with a bunch of
signals coming in and out to the control registers.

The control registers give you the ability to change any of the SPI hardware
configurations by software instructions. And there is also the status register that
gives you some signals about the ongoing and last-done transaction and any error
if happened.
The baud rate generator (Clock signal SCK) is also configurable by software as
we can tell and there is a control logic dedicated for the NSS pin (if you’re going
to use it).
STM32 SPI Flags (Status and Errors):
There are some status flags provided for the application to completely monitor
the state of the SPI bus.

• Tx buffer empty flag (TXE) – When it is set, this flag indicates that
the Tx buffer is empty and the next data to be transmitted can be
loaded into the buffer. The TXE flag is cleared when writing to the
SPI_DR register.
• Rx buffer not empty (RXNE) – When set, this flag indicates that
there are valid received data in the Rx buffer. It is cleared when
SPI_DR is read.
• BUSY flag – The BSY flag is useful to detect the end of a transfer if
the software wants to disable the SPI and enter Halt mode (or disable
the peripheral clock). This avoids corrupting the last transfer. For
this, the procedure described below must be strictly respected. The
BSY flag is also useful to avoid write collisions in a multi-master
system.
There are also other SPI flags that indicate whether a specific type of error has
occurred or not.

• SPI Master mode fault (MODF) – Master mode fault occurs when
the master device has its NSS pin pulled low (in NSS hardware
mode) or SSI bit low (in NSS software mode), this automatically
sets the MODF bit.
• SPI Overrun condition – An overrun condition occurs when the
master device has sent data bytes and the slave device has not cleared
the RXNE bit resulting from the previous data byte transmitted.
 • SPI CRC error – This flag is used to verify the validity of the value
received when the CRCEN bit in the SPI_CR1 register is set. The
CRCERR flag in the SPI_SR register is set if the value received in
the shift register does not match the receiver SPI_RXCRCR value.

Advantages of SPI
1. The main advantage of the SPI is to transfer the data without any
interruption.
2. It is simple hardware.
3. It provides full-duplex communication.
4. There is no need for a unique address of the slave in this protocol.
5. This protocol does not require precise oscillation of slave devices because
it uses the master's clock.
6. In this, software implementation is very simple.
7. It provides high transfer speed.
8. Signals are unidirectional.
9. It has separate lines of MISO and MOSI, so the data can be sent and
received at the same time.

Disadvantages of SPI
1. Usually, it supports only one master.
2. It does not check the error like the UART.
3. It uses more pins than the other protocol.
4. It can be used only from a short distance.
5. It does not give any acknowledgment that the data is received or not.

Applications of SPI

• Memory: SD Card, MMC, EEPROM, and Flash.

• Sensors: Temperature and Pressure.
• Control Devices: ADC, DAC, digital POTS, and Audio Codec.
• Others: Camera Lens Mount, Touchscreen, LCD, RTC, video game
controller, etc.
Conclusion
The versatility and efficiency of SPI make it an ideal choice for a wide range of
applications in embedded systems. From memory devices and sensors to
communication modules and display interfaces, SPI enables high-speed and
reliable communication, contributing to the functionality and performance of
numerous electronic devices and systems. Understanding the various applications
of SPI helps in designing and implementing effective communication solutions
in embedded system projects.