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2) Lecture2

1. The document discusses hardware description language (HDL) and focuses on VHDL. 2. It provides an example of a basic even parity detection circuit in VHDL using entity declaration, signal declaration, and concurrent statements. 3. Structural and behavioral descriptions in VHDL are explained using examples of even and odd detector circuits constructed from smaller components like XOR gates.

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58 views31 pages

2) Lecture2

1. The document discusses hardware description language (HDL) and focuses on VHDL. 2. It provides an example of a basic even parity detection circuit in VHDL using entity declaration, signal declaration, and concurrent statements. 3. Structural and behavioral descriptions in VHDL are explained using examples of even and odd detector circuits constructed from smaller components like XOR gates.

Uploaded by

faxofi9132
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Hardware Description

Language
Based on slides from Pong P. Chou
Outline

1. Overview on hardware description


language
2. Basic VHDL Concept via an example
3. VHDL in development flow

COEN313 - 2
Hardware Description
Language
1. Overview on hardware
description language
Programming language

• Can we use C or Java as HDL?


• No ! Modeled after a sequential process
– Operations performed in a sequential order
– Help human's thinking process to develop an algorithm
step by step
– Resemble the operation of a basic computer model

COEN313 - 4
HDL : Hardware Description Language
• Characteristics of digital hardware
– Connections of parts
– Concurrent operations
– Concept of propagation delay and timing
• Characteristics cannot be captured by
traditional PLs
• Require new languages: HDL
– Formal documentation
– Input to a simulator
– Input to a synthesizer
COEN313 - 5
Two HDLs used today
– VHDL and Verilog
– Syntax and ``appearance'' of the
two languages are very different
– Capabilities and scopes are quite
similar
– Both are industrial standards and are
supported by most software tools

COEN313 - 6
VHDL
– VHDL: VHSIC (Very High Speed Integrated Circuit) HDL
– Initially sponsored by DoD as a hardware documentation
standard in early 80s
– Transferred to IEEE and ratified it as IEEE standard
1176 in 1987 (known as VHDL-87)
– Major modification in ’93 (known as VHDL-93)
– Revised continuously

COEN313 - 7
Hardware Description
Language

2. Basic VHDL Concept


via an example
Even parity detection circuit

• Input: a(2), a(1), a(0)


• output: even

COEN313 - 9
First example Entity declaration
i/o ports
(“outline” of
the circuit)

Signal declaration

concurrent
statement

COEN313 - 10
Conceptual Interpretation

COEN313 - 11
Another VHDL description!

• Same entity declaration


• Implicit δ-delay (delta delay)
COEN313 - 12
Structural description

• In structural view, a circuit is constructed by smaller


parts.
• Structural description specifies the types of parts
and connections.
• Essentially a textual description of a schematic
• Done by using “component” in VHDL
– First declared (make known)
– Then instantiated (used)

COEN313 - 13
Example

• Even detector using previously


designed components (xor2 and not1)

COEN313 - 14
Structural Description of the
even_detector circuit

Declaration of internal wires

Stitch the
components
together via
wires

COEN313 - 15
Somewhere in the library

COEN313 - 16
Problem

library ieee;
use ieee.std_logic_1164.all;

entity odd_detector is port(


a: in std_logic_vector(3 downto 0); odd: out std_logic);
end odd_detector;

architecture str_arch of odd_detector is

component xor2 port( i1, i2: in std_logic; o1: out std_logic);


end component;

signal sig1,sig2: std_logic;

begin
unit10: xor2 port map (i1 => a(0), i2 => a(1), o1 => sig1);
unit11: xor2 port map (i1 => a(2), i2 => a(3), o1 => sig2);
unit2: xor2 port map (i1 => sig1, i2 => sig2, o1 => odd);
end str_arch; COEN313 - 17
Solution

COEN313 - 18
“Behavioral” description
• No formal definition on “behavioral” in VHDL
• VHDL “process”: a language construct to encapsulate
“sequential semantics”
– The entire process is a concurrent statement
– Syntax:

COEN313 - 19
Behavioral description: Example

COEN313 - 20
Conceptual interpretation

COEN313 - 21
Listing 2.6

COEN313 - 22
Testbench
• a “virtual” experiment table
– Circuit to be tested
– Input stimuli (e.g., function generator)
– Output monitor (e.g., logic analyzer)
• e.g.,

COEN313 - 23
VHDL Listing 2.7

COEN313 - 24
COEN313 - 25
COEN313 - 26
Configuration
• Multiple architecture bodies can be associated with an
entity declaration
– Like IC chips and sockets

• VHDL configuration specifies the binding


• E.g.,

COEN313 - 27
VHDL in development
flow

COEN313 - 28
Coding for synthesis

• “Execution” of VHDL codes


– Simulation:
• Design “realized” in a virtual environment
(simulation software)
• All language constructs can be “realized”
• “realized” by a single CPU

COEN313 - 29
Summary: Synthesis

• Design realized by hardware components


• Many VHDL constructs cannot be
synthesized (e,g, file operation, floating-
point data type, division)
• Only small subset can be used (E.g., 10
additions)
• Syntactically correct code ≠
Synthesizable code
• Synthesizable code ≠ Efficient code
• Synthesis software only performs
transformation and local search COEN313 - 30
Course Objectives

• The course focuses on hardware, not


VHDL (i.e., the “H”, not “L” of HDL)
• Emphasis on coding for synthesis:
– Code accurately describing the underlying
hardware structure
– Code providing adequate info to guide
synthesis software to generate efficient
implementation

COEN313 - 31

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