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17 views135 pagesDokumen - Tips - Microprocessor by Apgodse Dagodse
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© © All Rights Reserved
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/ 135
alee tel eerste) oa
Microprocessor
ISBN 9788184317060
All rights reserved with Technical Publications, No part of this book should be.
reproduced in any form, Electranic, Machanical, Photocopy er any informotion storage and
retrieval system without prior permission in wting, from Technical Publications, Pune,
Published by :
‘Technical Publications Pune”
#1, Amit Residency, 412, Shaniwar Peth, Pune - 411 030, India,
Printer :
‘Avet DTPrintes
Scne. 10/3,Siehagad Road,
Pie 411 041 Fie scone el
Chapter -4 introduction to Intel 6085 Microprocessor (1-14) to (1 - 84)
Chapter-2 Intel 2086 Architecture: (2-1) to (2-28)
Chapter - 3 Instruction Set of 8086 / 88 (3 - 1) to (3 - 46)
Chapter-4 8086 ALP Programming (4-1) to (4-50)
Chapter-5 Mixed Mode Programming with
C - Language and Assembly (5-1) to (5 - 18)
Chapter - 6 Designing the 8086 CPU Module (6 - 1) to (6 - 26)
Chapter -Z 8086 Interrupts (7-1) to (7-12)
Chapter -§ Memory Interfacing (8-1) to (B- 28)
Chepter-9 I/O Interfacing (9-1) to (9- 14)
Chepter-10 — Paralle! Communication Interface - 8255 (10 - 1) to (10 - 68)
Chapter - 11 Programmable Interrupt Controller - 8259 (11 - 1) to (11 - 20)
Chapter-12 Programmable Interval Timer 8253/54 (12 - 1) to (12-26)
Chapter-19 8237 DMAG (13 - 1) to (13 - 20)
Chapter-14 Multiprocessor Systems (14 - 1) to (14 - 80)
Chapter- 15 0 Buses and Standards (15-1) to (15-14)
Appendix-A 8086 Software Experiments (A- 1) to (A-86)
Appendix-B instruction Set Summary (B- 1) to (8-8)
Appendix-C Commonly used DOS Functions {C- 1) to (C- 28)
Appendix-D Debugger (D- 1) to (D - 6)
EE EERE RR AA VS OE 1, Introduction to Inte! 8085 Microprocessor (Chapter -1)
Basic functions of the microprocessor, System bus architecture, Pin configuration and
| programmer's model of intel O85 microprocessor.
‘Qverview of the instruction groups of 8085 and the addressing mades.
(No progremming based on 8085)
2. Intel 8086 Architecture (Chapter -2)
Major features of 8086 processor, 086/88 CPU architecture and the pipelined operation,
Programmer's model and segmented memory.
3. Instruction Set of 8086 and Programming (Chapters -3, 4, 5, Appendix-A)
Instruction set of 8086 microprecessar in details, Addressing mocles of 8086/88, Programming
the 8086 in assembly |; age, Mixed mode ramming with C-lanquage and assembly,
4, Designing the 8086 CPU Module (Chapters -6, 7)
8086 pin description in details, Generating the 8086 system clock and reset signals, 8086
minimum and maximum mode CPU modules, Minimum and maximum mode timing diagrams,
Interrupt structure, Interrupt processing and the predefined interrupts in 8086 processor.
5. Peripheral Controllers for 8086 Family and System Design
(Chapters -8, 9, 10, ti, 12, £3)
Functional block diagram and description, Control word formats, Operating modes and
applications of the peripheral controller’ namely 8255-PPI, 8253-PIT, 8259-PIC and
8237-DMAC, Interfacing of the above peripheral controllers.
Keyword and display interface using 8255.
Memory interfacing : SRAM, ROM and DRAM (using a typical DRAM controller such as intel
8203.
‘System design based on the memory and peripherals.
6. Multiprocessor Systems (Chapter -14)
Study of multiprocessor configurations namely Tightly Coupled System (TCS) and. Loosely
| Coupled System (LCS). TCS with the case study of the coprocessor, Various system bus
arbitration schemes in LCS, and role of the bus arbiter (Intel 8289) in the LCS,
7.1/0 Buses and Standards (Chapter -15)
Rae ia eee eT ERT
Gopyrighte Table of Contents (Detail)
eis
1.1 Introduction
1.2 8085 Architecture.
1.2.1 Registers:
1.2.2 Arithmetic Logic Unit (ALU)
1.2.3 Instruction Decoder
1.2.4 Address Bufier. .
1.2.5 Address/Data Bufler
1.2.6 Incrementer/Decrementer Address Latch.
1.2.7 Interrupt Control.
1.2.8 Serial VO Control ae
4.2.9 Timing and Control Circuitry.
1.3 Pin Configuration .
1.3.4 Programmer's Model of Intel 8085 Microprocessor .
1.3.2 Data Bus and Address Bus
1.3.3 Control and Status Signals.
1.3.4 Interrupt Signals .
1.3.5 Serial VO Signals
1.3.6 DMA Signal.
1.3.7 Reset Signals .
1.4 8085 System...
1.4.1 Clock Circuits
1.4.2 Demuitiplexing AD, - ADs
14.3 Reset Circuit,
1.4.4 Generation of Control Signals
14.5 Bus Drivers.........
4.4.6 Typical Configuration
1.5 8985 Interrupts...
1-1
1-3
leo ko |eé> loo lee tee IN IN IN IN IN IN ae 4.5.4 Types of interrupts, .. 1...
1.5.2 Overall Interrupt Structure .
i nlemupl
1.5.2.2 Software interrupts in 8085.
1.5.3 Masking / Unmasking of Interrupts
1.5.4 Pending Interrupts.
1.5.5 Interrupt Timing .
1.55 Interrupt Driven WO
1.6 Addressing Modes
17 Instruction Sel
4.7.4 Data Transfer Group
1.2.2 Arithmetic Group
17.3 Logie Group...
17.4 Rotate Group...
1.2.5 Slack Operations.
4.2.5 Branch Group
1.2.7 Input/Output.
1.2.8 Machine Control Group -
1.8 Instruction Set Summary..
1.9 Instruction Comparisons ..
Review Questions ...
2.4 Introduction ....
2.2 Major Features of 8086 Processor
2.3 Programmer's Model...........
2.3.1 General Purpose Registers
2.3.2 Segment Registers...
2:33 Pointers and Index Registers .
2.3.4 Flag Register .
2.4 8086/88 CPU Architecture ....
2.4.1 Bus Interface Unit [BIU} .
2.42 Pipelined Operation...
2.4.3 Execution Unit [EU] 5
LALA ENS EAT A 2.4.3.4 Control Circuitry, Instruction Decoder, ALU... se ptneaceaey!
243.2 Flag Register. au é oe . 2-7
243.3 General Purpose Registers... Eaeibe nega
2.4.4 Segmented Memory pres sorneeimenas w 2 2-8
2.4.4.1 Rulas far Memory Sagmantation erie tes ae sienew
2.4.4.2 Advantages of Memory Sogmentation r : 2.5
24.4.3 Generation of O-bitAddress 0 Be
24.4.4 Pointers end index Repistors : aesrracan BEAT
24.4.5 Defaultand Alternate Register Assignments... ss Be
2.4.4.8 Segment Override Prefix
2.5 Addressing Modes of 8086/88 ...
2.5.4 Data Addressing Modes .
25.1.4 Addressing Medes fr Acesing imme and Rogier Dats saeco neascen EO
2.5.1.2 Addressing Modes for Accessing Data in Memory... ws 2.15
2.5.4.3 Addressing Modes for Accessing VO Ports (VO Modes)... es 2-22
2.5.2 Program Memary-Addressing Modes.
2.5.8 Stack Memory Addressing Modes .
24.32 PUSH and POP Operations... ee 2-26
2833 CALL Operation... p a 2-28
25.3.4 REY Operation : pees : 2 2-27
25.3.5 Overlowand Underowal Stack. oe
Review Questions.
University Questions
3.1 Introduction
3.2 Data Movement Instructions
3.2.1 MOV Instruction. .
3.2.2 PUSH/POP Instructions.
3.2.3 Load Effective Address...
‘3.2.4 String Data Transfer Instructions. . .
3.2.5 Miscellaneous Data Transfer Instructions...
3.3 Addition, Subtraction and Compare Instructions. 33.4 Addition.
33.2 Subtraction
333 Comparison : :
3.4 Multiplication and Division Instructions
B41 Multiplication .....0..sesseseeseeees : nt
342 Division... gore eee cepecrennies 23-15
3.5 BCD and ASCII Arithmetic Instructions,
3.5.1 BED Arithmetic
3.6.2 ASCII Arithmetic .
3.6 Logical Instructions
37.4 Shift... penerepenee scree sevarmespee 218-28
2.2 Rotate ‘i sera “a6
3.8 String Compare Instructions ..
3.9 Jump Instructions...
3.14 Interrupt Instructions ..
3.12 Assembler Directives and Operators ..
3.12.4 Assembler Directives...
3.12.2 Summary of Assembler Directives .
3.12.3 Variables, Suffix and Operators.
3.12.4 Accessing 2 Procedure and Data from Another Assembly Module
Review Questions ..
4.4 Introduction ...
4.2 Languages used for Programming..
4.2.1 Machine Level Programs.
4.2.2 Assembly Language Programs .
4.2.3 High Level Language Programs
4.3 Assembly Language Programming Tips...
4.4 Assembly Language Program Development and Execution 4.5 Procedures...
45.1 Reentrant Procedure...
45.2 Recursive Procedure.
4.6 Libraries...
4.7 Controlling the Flow of an Assembly Language Program...
4.8 Macros...
4.9 Assembly Language Example Programs
4.10.1 Routines to Convert Binary to ASCII .
{101.1 8 AAM Instn (Foe number ess han 100) an a 4B
4.10.1.2 By Series of Decimal Division. _.
4.10.2 Routine to Convert ASCII to Binary.
4.10.4 Routine to Display Hexadecimal Data.
4.10.5 Lookup Tablas for Data Conversions _
4.11 Timings and Delays ..
4.41.1 Timer Delay using NOP Instruction
4.14.2 Timer Delay using Counters...
4.11.3 Timer Delay using Nested Loops
Review Questions...
University Question...
5.1 Introduction ..
5.2 Combining C and Assembly.
5.3 In-Line Assembly
53.1 Inline syntax. ..
§.3.2 Features of an In-Line Asserbly Language 5.4
§.3.3 Accessing C Data. 5-5
§.3.4 Jumps and Labels 5-7
5.3.5 Writing Functions.
5.3.6 Calling C Functions .
5.3.7 Defining _asm Block as C Macros. . 8.44.2 Funclional Description. .
8.4.4.3 Modes of Oparaticn
8.4.44 Operaling States
8.4.4.5 Interfacing with 8068 System
8.4.4.5 Interfacing with 8086 System
8.5 Wait State Generator Circuitry.
Review Questions ...
University Questions...
9.1 Introduction ....
9.2 Programmed 1/0...
9.3 1/0 Interfacing Technique:
9.3.1 VO Mapped VO...
9.3.2 Memory Mapped 0
9.3.3 VO Device Selection...
9.3.4 Interfacing B-bit input Port.
9.3.5 Interfacing 16-bit Inpul Port...
.3.6 Interfacing B-bit Output Devi
9.3,7 Interfacing 16-bit Output Device...
9.3.8 VO Interfacing with 16-bit Port Address.
9.3.9 VO Interfacing with Memory Mapoed VO
9.4 Comparison between Memory Mapped
0 and {0 Mapped I/O in 8086.
9.5 Interrupt Driven W/O ....
Reveiw Questions ..
University Questions ..
10.3 Pin Diagram. 10-2
10.4 Block Diagram - 10.4.2 Control Logic. A
10.4.3 Group A and Group B Controls.
10.5 Operation Modes ..
10.5.1 Bit SetReset (BSR) Mode.
105.20 Modes...
10.6 Control Word Formats.
10.6.2 For WO Mode... ..
10.7 8255 Programming and Operation
10.7.1 Programming in Mode 0...» ancy emeneanaes
10.7.2 Programming in Mode 1 (Input / Output With Handshake)
10.7.3 Programming in Mode 2 (Strobes Bi-directional Bus VO) .
10.8 Interfacing 8255 1o 8086 in VO Mapped I/O Mode.
10.9 Interfacing 8255 to 8086 in Memory Mapped VO.
10,10 Keyboard and Display Interfacing ...
10.11 Stepper Motor Interfacing ..
10.12 Control of High Power Devices using 8255
40.124 Integrated Circuit Buffers
10.12.2 Transistor Buffers.
10.42:3.2 Solid Stato Relays... ee a. 10-38
10.13 D/A Converters
10.13.1 IC 1408
* 10.13.2 DACOB30 .
10.13.21 Features...
10.13.2.2 Pin Diagrams
10.13.2.3 Fuctional Black Diagram. 10-45
10.13.24 Double-Buffered Operation i ai 10-45
10.19.25 Analog Output... arent a reer eee Aes 10-48
10.43.26 Typical Connection... : : : 10-48
10.13.2,7 Interfacing DACOBS0 lo 6085 Microprocessor... ss 10-49 10.13.28 Interfaring DACO830 to BOB5 Microprocessor using B255 see 10edo
10.14 interfacing A/D Converters,
10.14.1 ADCOE04 Family
10.14.1.1 Pin Dlagrom
10.14.1.2 Features. -
10.14.1.3 Operation «ws
10.14.4.4 Anaiog Inputs... .
10.14.1.5 Clock Signal momen
10.14.1.6 Typical Interface... ene + 10-53
10.14.1.7 Interfacing the ADC 080G/0804/0805 to 8086 Microprocessor ._. .. 10-53
10.14.1.8 interfacing ADC 0803/0804/0805 to 8086 using 8255.
10.14.1.9 Appliestion
10.14.2 ADC 0808/0809...
10.14.24 Foams . 2.)
10.14.2.2 Pin Diagram...
10.14.2.3 Operation...» «
10.14.24 interfacing...
10.15 Temperature Control System.
Review Questions...
University Questions
pter=i7 initertup itroller:
11.1 8259A Programmable Interrupt Controller...
11.2 Features of 8259A
11.3 Block Diagram of 82594 ....
11.4 Interrupt Sequence with 8086...
11.5 Priority Modes and Other Features.
11.6 Programming the 8259A..
11.7 82594 Interfacing with 8085 .
11.8 82594 Interfacing...
Review Questions
University Questions 12.1 Introduction
12.2 Features ..
12.3 Block Diagram...
412.4 Operational Description
12.5 Mode Definition...
12.8 Programming Examples...
12.7 Interfacing of 8253/54 with 806¢
412.8 Interfacing 8253/54 to 80BG in Memory Mapped I/0...
12.9 Application ; Pre-Settable Alarm Syster.....
12.10 Application : DC Motor Speed and Direction Control.
Review Questions..............
University Questions ......
Chapter #138257 DMAG
43.1 Introduction
13.4.1 Software Controlled Data Transfer.
13.4.2 Hardware Controlled Data Transfer ,
1.1.24 DMA idle Cycle
13.1.2.2 DMA Active Cycle... .
13.2 Data Transfer Modes of DMA...
13.3 DMA Controller 8237
43.3.4 Features of 8237.
43.3.2 Pin Diagram of 82378
13.3.3 Block Diagram of 82374.
13.3.4 Trensfer Types...
133.441 ivory Aero Taner
13.3.4.2 Autoinitiaize
13.3.5 Priomty....
13.3.5.1 Fiwed Priority.
13.3.5:2 Rotating Privy...
13.3.6 Register Descriotion
13.3.7 Interfacing,
ISS CRT RET RNR:
‘Interval Thier €253/64 Review Questions
University Questions.
14.2.3 Tightly Coupled System using 6086...........
414.3 Loosely Coupled Multiprocessor Configuration .
14.3.1 Loosely Coupled System using 8088 __
14.3.2 Advantages of Loosely Coupled System ....
14.4.3 Multipart Memory 16-12
14.5 Contention Problems in Multiprocessor Syeterist 14-414
145.1 Memory Confection ere 14-14
14.5.3 Hot Spot Contention...
14.5.4 Techniques for Reducing Contentions.
14.6 Bus Arbitration ..
14.7 8289 Bus Arbiter ..
14.8 Numeric Processor 8087 ..
14.8.1 Features of 8087
14.8.2 Pin Diagram of 8087.....................
u i
14.8.4 Intoraction between 8086 and 8087.
14.8.5 The 8087 Architecture .............
14.8.5.1 Instruction Queve . . . . .
148.52 Data Registers.
14.8.5.3 Status Registers... .
448.54 Control Register . . 14.8.7 Stacks in 8087 . . 14-39
14.8.8 Instructions of 8087 14-40
14.8.8.1 Data Transfer Instructions : 3 aRoTERRENETONS 14-40
14.8.8.2 Arithmetic Instructions . an : ce WM?
14.8.8.3 Compara instructions - - : x 14-85
148.4 Transcondental (Higonomete and Exponential insuaons . 14-87
14.8.8.5 Instructions Which Load Constants .
14.2.8.5 Processor Control Instructions
14.8.9 Programming using 8087 Caprocessor .
14.9 /0 Processor B089
14.9.1 Features.......
14.9.2 Architecture of 8089
14,9.3 Communicetion between 8086 and 8089,
14.10 System Design Based on Memory and Peripherals
Review Questions...
University Questions
15.1.1.2 Half Duplex Ess
16.4.1.3 Full Ouplex, 2.2.2. ee ee
16.1.2 Basic Serial Communication Data Formats .
18.1.2. Asynchronous see
‘15.1.2.1 Synchronous. 2 2
15.2 RS-232C ....
16.2.1 DB-25 P Connector
15.2.2 DB-SP Connector...
15.2.3 Data Transmission and Reception using RS-232C .
15.24 Inlerfacing RS-232C.
415.3 IEEE 488 Standard
Review Questions .......
University Questions...
SE EAR EP TOL TT TERS Programs Involving Data Transfer Instructions ...
Programs Involving Arithmetic and Logical Operations...
Programs Involving Bit Manipulation Instructions like Checking
Programs Involving Branch/Loop Instructions enone
Programs on String Manipulations ..
Programs to use DOS Interrupt INT21H Function Calls.
C.1 Character Input Functions
C.2 Character Display Functions
C.3 File Control Block Functions
C.4 Handle Functions.
C.5 Memory Management Functions
€.6 Display Functions Provided by ROM BIOS
C.7 Printer Functions...
Aphendi<=DiDebugger! 0) is Se eA) toe): Lob Exporimant | : Stora 8-bit date in memory.
Lob Experiment 2 : Exchange the contents of mamery locevions
Lob Exparimont 3 : Add two B
Lob Experiment 4 : Subjrocttwe B-bitrumbers. 2...
Lob Experiment § = Add two 16:bit numbers.
Lob Experiment 6 : Sublractiwe 16-bilnumbers. 2. 2
Lob Experiment 7 : Check results alter execution of INR B, INR C.ond INX8 instructions.
Lob Exporimant 8 : Check rosuits alter execution of DCR C, DCR B and DCXB instructions.
mymbore seis ieee as
Lob Experiment 9 : Find the 1's complement ofanumber.... 2.22... se
Lob Experiment 10 : Find the 2’s complement ofo number...
Lob Experiment 111 : Pack the two unpacked BCD numbers.
Lob Experiment 12 : Unpack the BCD number. ‘
Lob Exporimant 13 : Somple subroutine progrom.
Copyrighted materia 1 — _
Introduction to Intel
8085 Microprocessor
1.4 Intraduction
The world’s first microprocessor, the Intel 4004, was a 4d-bil microprocessor.
{A bit is a binary digit with a value zero ar ene and 4-bit microprocessor
means the microprocessor can process 4-bit word in one cycle, It has 12-bit
address lines to access 4096 4-bit wide memory locations, The 4004
microprocessor has only 45 instructions.
The Intel released the 4040, as updated version of 4004 wilh enhancement in
speed and without any improvement in word length and memory size.
In 1971 announced the 8008, 8-bit and faster version of 4004. This version came
up with expanded memory size upto 16 kbytes and additional instructions to
make total of 48 instructions. (A byte is 8-bit binary number and a K is 1024).
In 1974 Intel came out with 8080 was a considerable improvement over its
predecessors, A six month later Motorola corporation announced its 8-bit
processor MC6800. Then Zilog and so on.
‘The Table 1.1 shows the early &-bit microprocessors.
Microprocessor number Manufacturer
6502 [ MOS technology
8080 [ Intel
FB Fairchid
IMP-8. National semiconductor
PPS-8 Rockwall International
z8 Zilog
Table 1.1
@-4)
Sar] Microprocessor 1-2 Introduction to Inte! 8085 Microprocessor
In 1977, Intel introduced updated version of 8080, 8085. The features of 8085
microprocessor are as given below :
Features of 8085
‘The features of 8085 include :
1. It is an 6-bit microprocessor ie. it can accept, process or provide S-bit data
simultaneously.
2 It operates on a single +5 V power supply connected at Vcc; power supply ground.
is connected to V,.
3. It operates on clock cycle with 50 % duty cycle,
44. It has on chip clock generator, This internal clock generator requires tuned circuit
like LC, RC or crystal, The internal clock generator divides oscillator frequency by
2 and generates clock signal, which can be used for synchronizing extecnal devices.
5. It can operate with a 3 MHz clock frequency. The B085A-2 version can operate at
the maximum frequeney of 5 MHz.
6. It has 16 address lines, hence it can access (2"*) 64 kbytes of memory.
7. It provides &-bit 1/O addresses to access (2° ) 256 I/O ports.
8. In 8085, the lower 8-bit address bus (Aq-A;) and data bus (Dy-D;) are
multiplexed to reduce number of external pins. But due to this, external hardware
(atch) is required to separate address lines and data lines.
9. It supports 74 instructions with the following addressing modes :
a) Immediate b) Register c) Direct d) Indirect e) Implied
10. The Arithmetic Logic Unit (ALU) of 8085 performs :
a) 8-bit binary addition with or without carry.
b) 16-bit binary addition.
<) 2 digit BCD addition.
d) 8-bit binary subtraction with or without borrow.
e) 8-bit logical AND, OR, EX-OR, complement (NOT) and bit shift operations.
11, It has 8-bit accumulator, flag register, instruction register, six &-bit general purpose
registers (B, C, D, E, H and L) and two 16-bit registers (SP and PC). Getting the
operand from the general purpose registers is more faster than from memory.
Hence skilled programmers always prefer general purpose registers to store
program variables than memary.
12. It provides five hardware interrupts : TRAP, RST 7.5, RST 6.5, RST 5.5 and INTR.
13. It has serial 1/0 control which allows serial communication.
14. It provides control signals (10/M, RD, WR) to control the bus cycles and hence
external bus contraller is not required. Microprocessor 1-5 Introduction to Inte! 8085 Microprocessor
temporary data register. However, it is internally used for execution of most of the
arithmetic and logical instructions.
For example ; ADD B is the instruction in the arithmetic group of instructions which
adds the contents of register A and register B and stores result in register A. The addition
operation is performed by ALU. The ALU takes inputs from register A and temporary
data register. The contents of register B are wansferred to temporary data register for
applying second input to the ALU.
1b) W and Z registers : W and % registers are temporary rogisters. These registers are
used to hold S-bit data during cxccution of some instructions. These registers are not
available for programmer, since 8085 uses them internally.
Use of W and Z registers :
The CALL instruction is used to transfer program control to a subprogram er
subroutine. This instruction pushes the current PC contents onto the stack and loads the
given address into the PC. The given address is temporarily stored in the W and Z
registers and placed on the bus for the fetch cycle. Thus the program control is transferred.
to the address given in the instruction. XCHG instruction exchanges the contents of H with
D and L with E. At the time of exchange W and Z registers are used for temporary
storage of data.
3, Special purpose registers
a) Register A (Accumulator) ; It is a tri-state cight bit register. It is extensively used
in arithmetic, logic, load and store operations, a3 well as in, input/output (1/0)
operations. Most of the mes the result of arithmetic and logical operations is
stored in the register A. Hence it is alsa identified as accumulator
b) Flag register ; It is an S-bit register, in which five of the bils cary significant
information in the form of flags : S (Sign flag), 2 (Zero flag), AC (Auxiliary carry
flag), P (Parity flag) and CY (carry flag) as shown in Fig. 1.2
0, Dg Ds Dy Ds Dy
Fig. 1.2 Flag register
S-Sign flag : After the execution of arithmetic or logical operations, if bit D, of the
result is 1, the sign flag is set. In a given byte if D, is 1, the number will be viewed as
negative number. If D, is 0, the number will be considered as positive number.
Z-Zero flag : The zero flag sets if the result of operation in ALU is zero and flag resets
if result is non-zero. The zero flag is also set if a certain register content becomes zero:
following an increment or decrement operation of that register.
AC-Auxiliary carry flag : This flag is set if there is an overflow out of bit 3 ie., carry
from lower nibble to higher nibble (D, bit to D, bit). This flag is used for BCD operations.
and it is not available for the programmer. Microprocessor 1-6 Introduction to Intel 8085 Microprocessor
P-Parity flag : Parity is defined by the number of ones present in the accumulator.
After an arithmetic or logical operation if the result has an even number of ones, i.e. even
parity, the flag is set. If the parity is odd, fing is reset.
C¥-Carry flag : This flag is set if there ix an overflow out of bit 7. The carry flag also
secves as a borrow flag for subtraction, In both the examples shown below, the carry flag
is set.
ADDITION ‘SUBTRACTION
98H 1001 1001 89H 1000 1901
+ 78H + 0111 o101 = ABH = 1010 1011
Gary Gio §=TJooor 0000) owow (JOEH © EE]tt07 1110
© Instruction register : In a typical processor operation, the processor first fetches the
opcode of instruction from memory (ie. it places an address on the address bus
and memory responds by placing the data stored at the specified address on the
data bus). The CPU stores this opcode in a register called the instruction register.
This opcode is further sent to the instruction decoder to select one of the 256
alternatives.
4. Sixteen bit registers
a) Program counter (PC) : Program is a sequence of instructions. As mentioned
earlier, microprocessor fetches these instructions from the memory and executes
them sequentially. The program counter is a special purpose register which, at a
given time, stores the address of the next instruction to be felched. Program
counter acts as a pointer to the next instruction. How processor increments
program counter depends on the nature of the instruction; for one byte instruction
it inctements program counter by one, for two byte instruction it increments
program counter by two and for three byte instruction it increments program
counter by three such that program counter always points to the address of the
next instruction.
In case of JUMP and CALL instructions, address followed by JUMP and CALL
instructions is placed in the program counter. The processor then fetches the next
instruction from the new address specified by JUMP or CALL instruction. In
conditional JUMP and conditional CALL instructions, if the condition is nat
satisfied, the processor increments program counter by three so that it points the
instruction followed by conditional JUMP or CALL instruction; otherwise processor
fetches the next instruction from the new address specified by JUMP or CALL
b) Stack pointer (SP) : The stack is a reserved area of the memory in the RAM where
temporary information may be stored. A 16-bit stack pointer is used to hold the
address of the most recent stack entry. Microprocessor 1-7 Introduction to Inte! 8085 Microprocessor
1.2.2 Arithmetic Logic Unit (ALU)
‘The 8085's ALU performs arithmetic and logical functions on eight-bit variables. The
arithmetic unit performs bitwise fundamental arithmetic operations such as addition and.
subtraction. The logic unit performs logical operations such as complement, AND, OR and
EX-OR, as well as rotate and clear. The ALU alsa looks after the branching decisions.
4.2.3 instruction Decoder
‘As mentioned earlier, the processor first fetches the opcode of instruction from
memory and stores this opcode in the instruction register. It is then sent to the instruction
decoder. The instruction decoder decodes it and accordingly gives the timing and control
signals which control the register, the data buffers, ALU and external peripheral signals
(explained in Jater sections) depending on the nature of the instruction,
The 8085 executes seven different types of machine cycles. It gives the informatian
about which machine cycle is currently executing in the encoded form on the S,, S, and
10/M lines. This task is done by machine cycle encoder.
1.2.4 Address Buffer
This is an bit unidirectional buffet. It is used to drive external high order address
bus (Ayg-As). It is also used to tri-state the high order address bus under certain conditions
such as reset, hold, halt and when address lines are not in use.
1.2.5 Address/Data Buffer
This is an 8-bit bi-directional buffer. It is used to drive multiplexed address/data bus,
ite. low order address bus (A,-A,) and data bus (D,-D,). It is also used to tri-state the
multiplexed address/data bus under certain conditions such as reset, hold, halt and when
the bus is not in use.
The address and data buffers are used to drive external address and data buses
respectively. Due to these buffers the address and data buses can be tri-stated when they
are not in use,
1.2.6 Incrementer/Decrementer Address Latch
ister is used fo increment or decrement the contents of program counter
or stack pointer as a part of execution of instructions related to them.
4.2.7 Interrupt Contro!
‘The processor fetches, decodes and executes instructions in a sequence. Sometimes it is
necessary to have processor the automatically execute one of a collection of special
routines whenever special condition exists within a program or the microcomputer system.
The most important thing is that, after execution of the special routine, the program
control must be transferred to the program which processor was exceuting before the
occurrence of the speelal condition. The occurrence of this special condition is referred as. Microprocessor 1-8 Introduction to Intel 8085 Microprocessor
interrupt. The interrupt control block has five interrupt inputs RST 5.5, RST 65, RST 7.5,
TRAP and INTR and one acknowledge signal INTA. We will discuss these interrupts
section 1.5 in more details.
1.2.8 Serial VO Control
In situations like, data transmission over long distance and communication with
cassette tapes or a CRT terminal, it is necessary to transmit data bit by bit to reduce the
cost of cabling. In serial communication one bit is transferred at a time over a single line.
The 8085's serial I/O control provides twe lines, SOD and SID for serial communication,
The serial output data (SOD) line is used to send data serially and serial input data (SID)
line is used to receive data serially.
1.2.9 Timing and Control Circuitry
The control circuitry in the processor 8085 is responsible for all the operations. The
control circuitry and hence the operations in 8085 ore synchronized with the help of clock
signal. Along with the control of fetching and decoding operations and generating
appropriate signals for instruction execution, control circuitry also generates signals
required to interface external devices to the processor, 8085.
1.3 Pin Configuration
Fig. 13 (a) and (b) show 8085 pin configuration and functional pin diagram of 8085
respectively. The signals of 8085 can be classified into seven groups according to their
functions.
a) Power supply and frequency signals _b) Data bus and address bus
¢) Control bus 4) Interrupt signals
©) Serial 1/O signals 1) DMA signals
8) Reset signals
1.3.1 Programmer's Model of Intel 8085 Microprocessor
3) Ve : It requires a single +5 V power supply.
ii) Vy. : Ground reference.
iif) X, and X,: A tuned circuit like LC, RC or crystal is connected at these two pins.
‘The internal clock generator divides oscillator frequency by 2, therefore, to operate
a system at 3 MHz, the crystal of tuned circuit must have a frequency of 6 MHz.
iv) CLK OUT : This signal is used as a system clock for other devices. Its frequency is
half the oscillator frequency. Microprocessor 1-9 Introduction to Intel 8085 Microprocessor
Higrarder
gl eddreso Ou
Pr
REScT OUT
(a) Pin configuration (b) Functional
Fig. 1.3
1.3.2 Data Bus and Address Bus
A) AD, to AD, : The S-bit data bus (D, - D,) is multiplexed with the lower half
(Ag- Az) of the 16-bit address bus. During first part of the machine cycle (T,), lower &-bits
‘of memory address or I/O address appear on the bus. During remaining part of the
machine cycle (T, and T;) these lines are used as a bi-directional data bus.
B) A, to A,, : The upper half of the 16-bit address appears on the address lines Ag to
Ajs These lines are exclusively used for the most significant 8-bits of the 16-bit address
lines.
1.3.3 Control and Status Signals
A) ALE (Address Latch Enable) : We know that AD, to AD, lines are multiplexed and
the lower half of address (Ay - A;) is available only during T, of the machine cycle. This Microprocessor 41-10 Introduction to Intel 8085 Microprocessor
lower half of address is also necessary during T, and T; of machine cycle to access specific
location in memory or 1/O port. This means that the lower half of an address must be
latched in T, of the machine cycle, so that it is available throughout the machine cycle. The
latching of lower half of an address bus is done by using external latch and ALE signal
from 8085.
B) RD and WR : These signals are basically used to control the direction of the data
flow between processer and memory or I/O device/port. A low on RD indicates that the
data must be read from the selected memory location or 1/O port via data bus. A low on
WR indicates that the data must be written into the selected memory location or 1/0 port
via data bus.
© IO/M, S, and S, : 1O/M indicates whether 1/O operation or memory operation is
being carried out. S, and Sy indicate the type of machine cycle in progress.
D) READY : It is used by the microprocessor to sense whether a peripheral is ready or
not for data transfer. If not, the processor waits. It is tus used to synchronize slower
peripherals to the microprocessor.
4.3.4 Interrupt Signals
The 8085 has five hardware interrupt signals : RST 5.5, RST 6.5, RST 7.5, TRAP and
INTR. The microprocessor recognizes interrupt requests on these Hines at the end of the
current instruction execution,
‘The INTA (Interrupt Acknowledge) signal is used to indicate that the processor has
acknowledged an INTR interrupt.
1.3.5 Serial /O Signals
A) SID (Serial I/P data) : This input signal is used to accept serial data bit by bit from
the external device.
B) SOD (Serial O/P data) : This is an output signal which enables the transmission of
serial data bit by bit to the external device.
1.3.6 DMA Signal
A) HOLD : This signal indicates that another master is requesting for the use of
address bus, data bus and control bus.
B) HLDA : This active high signal is used to acknowledge HOLD request.
1.3.7 Resot Signals
A) RESET IN: A low on this pin
2) Sets the program caunter to zero (0000H).
2) Resets the interrupt enable and HLDA flip-flops. Microprocessor 1-41 Introduction to Inte! 8085 Microprocessor
3) Tri-states the data bus, address bus and control bus. (Note : Only during RESET is
active).
4) Affects the contents of processor's internal registers randomly.
On reset, the PC sets to OO00H which causes the 8085 to execute the first instruction
from address 0000H. Far proper reset operation reset signal must be held low for atleast
3 clock cycles. The power-on reset circuit can be used to ensure execution of first
instruction from address 0000H.
B) RESET QUT : This active high signal indicates that processor is being reset. This
signal is synchronized to the processor clock and it can be used to reset other devices
connected in the system.
1.4 8085 System
The 8085 microprocessor system consists of 8085 microprocessor and supporting
circuits such as clock circuit, reset circuit, demultiplexer circuit and circuit required for
goncration of control signals. In this section. we are going to see these additional circuits
and their operation in connection with microprocessor 8085.
1.4.1 Clock Circuits
The 8085 has on chip clock generator. Fig. 1.4 shows the internal block diagram of the
‘on chip clock generator. The internal clock gencrator requires tuned circuit like LC, RC or
crystal, or external clock source as an input to generate the clock. The internal T flip-flop
divides the frequency by 2. Hence the operating frequency of the 8085 is always half of the
oscillator frequency. The driving frequence or crystal frequency for 8085 must be at least
1 MHz ic. its operating frequency must be atleast 500 MHz. If operating frequency is
below 500 kHz the 8085 will not operate.
pVock*S V) Clk Out,
a | %
acl
Xx
Fig. 1.4 Block diagram of built-in clock generator Microprocessor 1-12 Introduction to Intel 8085 Microprocessor
Xs
ext R
I pe
Fig. 1.5 LC circuit Fig. 1.6 RC circuit
Its an LC resonant tank circuit. The resonant frequency for this circuit is given by,
LC tuned circuit ;
where C,, is the internal capacitance and it is normally 15 pF. The output frequency of
this circuit has 10 % variations. To minimize the variations in the output frequency, it is
recommended to have C,. atleast twice that of C,, Le. 30 pF.
RG tuned circuit : Fig. 1.6 shows the RC tuned circuit. The output frequency of this
circuit is also not exactly stable. But this circuit has an advantage that its component cost
fs less.
Crystal oscillator circuit : Fig. 1.7 shows the crystal oscillator circuit. It is the most stable
circuit. The 20 pF capacitor in the circuit is connected to assure oscillator start-up at the
correct frequency.
External clock :
Fig. 1.8 shows how to drive clock input of 8085 with external frequency source. Here
external clock is applied at X, input and X, input is kept open.
Crystal
Exemel
‘clock’
Norconnacted
wey
Fig, 1.7 Crystal oscillator circuit Fig. 1.8 External frequoncy sourco Microprocessor 4-13 Introduction to Intel 8085 Microprocessor
1.4.2 Demultiplexing AD; - AD,
We know that AD, to AD, lines are multiplexed and the lower half of address
(Ap~ Ay) is available only during T, of the machine cycle. This lower half of address is also
necessary during T, and T; of machine cycle to access specific location in memory or 1/0
port. This means that the lower half of an address bus must be latched in T, of the
machine cycle, so that it is available throughout the machine cycle. The latching of lower
half of an address is done by using external latch and ALE signal from 8085. The Fig. 1.9
shows the hardware connection for latching the lower half of an address. The IC 74LS373
is an 8-bit latch, having 8 D flip-flops. The input is transferred to the output only when
clock is high. This clock signal is driven by ALE signal from 8085. The ALE signal is
activated only during Tj, so input is transferred to the output only during T, ie. address
(Ag-A;) on the AD, to AD; multiplexed bus. In the remaining part of the machine cycle,
ALE signal is disabled so output of the latch (AyA;) remains unchanged. To latch lower
half of an address, in each machine cycle, the 8085 gives ALE signal high during T, of
every machine cycle.
Ic 74L$373
Fig. 1.9 Latching circuit Microprocessor 1-14 Introduction to Inte! 8085 Microprocessor
4.4.3 Reset Circuit
On reset, the PC sels to 0000H which
causes. the 8085 to exeeute the first instruction
from address Q000H. For proper reset
operation reset signal must be held low for at
Jeast 3 clock cycles. The power-on reset circuit
can be used to ensure execution of first
Reset instruction from address Q0QUH. Fig.1.10
shows the power-on reset circuit with typical
R, C values. (Note : R, C values may vary due
to power supply ramp up tim:
Not} as .
contact Upon power-up, RESET IN must remain
Li low for at least 10ms after minimum Vgc has
been reached, in the circuit shown in Fig. 1.10.
‘Upon power up or key press, the RESET IN
goes low and slowly rises to +5 V, providing
sufficient time for the processor to reset the system. The diode is connected to discharge
the capacitor immediately when power supply is switched OFF.
After RESET, 8085 loads Q000H in PC register and clears the INTE flag. Before going to
exeeute interrupt service routine, it is necessary to setup certain parameters, required to
execute interrupt service routine. To avoid interrupt to occur before completion of these
initial requirements, after power on or reset, INTE flip-flop is cleared to disable interrupts.
It can be enabled by EI instruction after initial settings.
+5.
IN 4148
1000
Fig. 1.10 Power on reset
As we know that, after power up or reset 8085 fetches its first instruction from 0000H
address, and it has to be the first instruction from monitor program. Therefore EPROM
consisting of monitor program must be located from address 0000H in any microprocessor
system.
1.4.4 Generation of Control Signals
The 6085 microprocessor provides RD and WR signals to initiate read or write cycle.
‘Because these signals are used both for reading/writing memory and for reading/writing
an input device, it is necessary to generate separate read and write signals for memory
and 1/0 devices.
The 8085 provides 10/M signal to indicate whether ‘the initiated cycle is for 1/0 device
‘or for memory device, Using IO/M signal along with RD and WR, it is possible to
generale separate four control signals =
MEMR © (Memory Read) : Ta read data from memory.
MEMW (Memory Write) : To write data in memory.
TOR /O Read) : To read data from I/O device.
IoWw (/O Write) : To write data in 1/O device. Microprocessor 1-15
Fig. 1.11 shows the circuit which generates MEMR, MEMW, IOR and IOW signals.
Fig. 1.11 Generation of MEMR, MEMW, IOR and IGW signals
‘We know that for OR gate, when both the inputs are @ low th then en only output is low.
Table 1.2 shows the truth table used to generate MEMR, MEMW, IOR and IOW si
The signal 1O/M_goes low for memory operation. This signal is logically ORed with RD
and WR to get MEMR and MEMW signals. When both RD and I0/M signals go low,
MEME signal goes low. Similarly, when both WR and IO/M signals go low, MEMW
signal goes low. To generate [OR and TOW signals for I/O operation, 10/M signal is first
inverted and then logically ORed with RD and WR signals.
om | m | wR | enn _
RD + 10/8 | WR + 10/5
Bw + to/si
° o 0 | Condition never exists, because RD and WR signals do not go low
simultaneously
0
hs bo Lb
7 o o Condition never exists, because RD and WR signals do not go low
simultaneously Microprocessor 1-16 Introduction to Intel 8085 Microprocessor
Same truth table can be implemented using 3: 8 decoder as shown in Fig. 1.12,
a
wa
D.
lo
ae
Fig. 1.12 Generation of control signals using 3 : 8 decoder
1.4.5 Bus Drivers
‘Typically, the 8065 buses can source 400 WA and sink 2 mA of current, Lc. it can drive
only one TTT. load. Therefore, it is necessary to increase driving capacity of the 6085 buses.
Bus drivers, buffers are used to increase the driving capacity of the buses.
Unidirectional buffers :
As we know, the address bus is unidirectional, &-bit unidirectional buffer, 74LS244 is
used to buffer higher address bus. The Fig. 113 shows the logic diagram of 74L5244. It
consists of eight non-inverting buffers with tri-state outputs. Each one can sink 24mA and
20 1
0 18
Fig. 1.43 Logic diagram of the 74LS244 icroprocessor 1-47 Introduction to Intel 8085 Microprocessor
saurce 15 mA of current, These buffers are divided into two groups. The enabling and
disabling of these groups are controlled by 1G and
Bi-diractional buffer =
To increase the driving capacity of data bus, bi-directional buffer is used. Fig. 1.14
shows the logic diagram of the bi-directional buffer 74LS245, also called an octal bus
transceivers, It consists of sixteen non-inverting buffers, eight for each direction, with
tri-state output. The direction of data flow is controlled by the pin DIR. When DIR is high,
data flows from the A bus to the B bus; when it is low, data flows from B to A. The active
Jow enable signal and. the DIR signal are ANDed to activate the bus lines. Each buffer in
this device can sink 24 mA and source 15 mA of current
29 -T4LS245 79,
Funetion table
B Datato ABus
A Dalato B Bus
leolation
19
Direction Enable
contrat
Fig. 1.14 Logic diagram of the 74LS245
4.4.6 Typical Configuration
Fig. 115 shows schematic of the 8085 microprocessor demullptexed address bus and
control signals.
HW also shows clock and reset circuits, Interrupt lines which are not in use are
grounded. This is necessary because floating intecrupt Tine may cause false triggering of
interrupt. Similarly, since the DMA controlier is not used, HOLD line is also grounded. As
we know READY signal is used to synchronize slow peripherals with the microprocessor.
When it is low, microprocessor enters in the wait state and when it is high, it indicates
that the memory or peripheral is ready to send or receive data. Here, the READY signal is
tied high to prevent the microprocessor from entering the wait state. ALE signal is
connected to the clock input of the latch, to latch the low order address in T; of the
machine cycle. To contro! the direction of the bi-directional buffer 74L$245, RD signal from.
8085 is connected to DIR input of the bi-directional buffer. Thus, when RD signal is low, Microprocessor
Introduction to Intel 8085 Microprocessor
DIR is low and data flows from memory or I/O device to the microprocessor, performing
read operation, When RD signal is high, DIR is high and data flows from microprocessor
to memory or I/O device performing write operation.
we
20
Kis = t .
7 Veo [eA
para Au
Tifratszad] Octat fg—Aro High
[a
Ea
ais]
a
Fig. 1.15 Typical 8085 configuration Microprocessor 1-18 Introduction to Inte! 8085 Microprocessor
1.5 8085 Interrupts
Sometimes it is necessary to have the computer automatically execute one of a
collection of special routines whenever certain conditions exists within a program or the
microcomputer system e.g. It is necessary that microcomputer system should give response
to devices suich as keyboard, sensor and other components when they request for service.
The most common method of servicing such device is the polled approach. This is
where the processor must test each device in sequence and in effect “ask” each one if it
needs communication with the processor. It is easy ta see that a large portion of the main
program is looping through this continuous polling cycle. Such a method would have a
serious and decremental effect on system throughput, thus limiting the tasks that could be
assumed by the microcomputer and reducing the cost effectiveness of using such devices.
‘A more desirable method would be the one that allows the microprocessor to execute
its main program and only stop to service peripheral devices when it is told to do so by
the device itself. In effect, the method, would provide an external asynchronous input that
would inform the processor that it should complete whatever instruction that is currently
being executed and fetch a new routine that will service the requesting device, Once this
servicing is completed, the processor would resume exactly where it left off. This method
is called interrupt method. It is easy to see that system throughput would drastically
increase, and thus enhance its east effectiveness. Most microprocessors allow execution of
special routines by interrupting normal program execution. When a microprocessor 1s
interrupted, it stops executing its current program and calls a special routine which
“services” the interrupt. The event that causes the interruption is called interrupt and the
special routine executed to service the interrupt is called interrupt service
routine/procedure.
Maskable and nonmaskable interrupts
Maskable interrupts are enabled and disabled under program control. By setting or
resetting particular flip-flops in the processor, interrupts can be masked or unmasked,
respectively. When masked, processor docs not respond to the interrupt eventhough the
interrupt is aetivated. Most of the processors provide the masking facility. In the processor
those interrupts which can be masked under software control are called maskable
interrupts. The interrupts which cannot be masked under software contral are called
nonmaskable interrupts.
Vectored interrupts
When the external device interrupts the MPU (interrupt request), MPU has to exccute
interrupt service routine for servicing that interrupt. If the internal contro! circuit of the
processor produces a CALL to a predetermined memary location which is the starting
address of interrupt service routine, then that address is called vector address and such
interrupts are called vector interrupts. For vector interrupts fastest and most flexible
resporse is obtained since such an interrupt causes a direct hardware-implemented
transition to the interrupt-service routine. This technique is called vectoring. Fig. 1.16
shows a widely used vectored interrupt scheme Microprocessor 1-20 Introduction to Intel 8085 Microprocessor
vm
nen
interrus |
so sees
lines ro
sae
sui
nt
ae
Fig. 1.16 A vectored interrupt scheme
As shown in Fig. 1.16, interrupt request signals are stored in the interrupt register. The
programmable interrupt mask register is used to disable any or all of the interrupt request
lines. For any AND gate, one input is the interrupt request signal from interrupt register
and second input is the inverted mask condition for the same interrupt from. interrupt
mask register. When any interrupt is masked (1), the input to AND gate is zero, hence
output goes zero. This means when interrupt is masked, the corresponding interrupt
request line is disabled. When interrupt request is present for unmasked interrupt, that is
fed into a priority encoder which produces the address which is then inserted inta the
program counter,
Nested interrupts
For some devices, a long delay in responding to an interrupt request may cause error
in the operation of computer. Such interrupts are acknowledged and serviced eventhough
processor is executing an interrupt service routine for another device. A system of
interrupts that allows an interrupt service routine to be interrupted is known as nested
interrupts. Consider, for example, a computer that keeps a track of the time of day using
real time clock. This real time clock requests te the processor at regular intervals and
processor accordingly updates the counts for seconds, minutes and hours of the day. For
the proper operation such an interrupt request from real time clock must be processed
eventhough computer is executing an interrupt service for another device. Microprocessor
Introduction to Inte! 8085 Microprocessor
41.5.1 Types of Interrupts
‘The 8085 has multilevel interrupt system. Tt supports two types of interrupts :
a. Hardware
b. Software
Hardware : Some pins on the 8085 allow peripheral device to interrupt the main
program for 1/O operations. When an interrupt occurs, the 8085 completes the instruction
is currently executing and transfers the program control to a subroutine that services the
peripheral device. Upon completion of the service routine, the MPU retums to the main
program. These types of interrupts, where MPU pins are used to receive interrupt requesis,
are called hardware interrupts.
Software : In software interrupts, the cause of the interrupt is an execution of the
instruction. These are special instructions supported by the microprocessor. After execution
of these instructions microprocessor completes the execution of the instruction it is
currently executing and transfers the program control to the subroutine program. Upon
completion of the execution of the subroutine program, program control returns to the
main program
1.5.2 Overall interrupt Structure
1.5.2.1 Hardware Interrupts in 8085
The 8085 has five hardware interrupts
1. TRAP
2. RST 75
3. RST 65
4. RST 55
5. INTR
When any of these pins, except INTE, is active, the internal control elreuit of the 8085
produces a CALL to a predetermined memory location. This memory location, where the
subroutine starts is referred to as vector location and such interrupts are called vectored
interrupts. The INTR is not a veciored interrupt. It receives the address of the subroutine
from the external device.
In 8085, all interrupts except TRAP are maskable. When logic signal is applied ta a
maskable interrupt input, the 8085 is interrupted only if that particular input is enabled
‘These interrupts can be enabled or disabled under program control. If disabled, 8085
disables an interrupt request. The interrupt TRAP is nonmaskable whish means that it is
not maskable by program control. The Fig. 1.17 shows the interrupt structure of 8085. The
figure indicates that, the 8085 is designed to respond to edge triggering, level triggering or
both. Microprocessor 1-22 Introduction to Intel 8085 Microprocessor
Priority Input pin Mask Vector
locations
2
ve edge 003C 45,
triggered
Reset-
RST 7.5 Interrupt.
recognized 0038; 5,
TL
Level triggered O06
— 0030, 6
4
Leval tnggered 00245
_ 00286
' { l 002414
Bath +ve edge
‘and level triggered 0020; 6
00186
Reset. 00106
‘Any interrupt recognized.
RST 0008; 6
— code.
5 from 0000,5,
external
Level tnageres hardware
Fig. 1.17 Interrupt structure of 8085
TRAP : This interrupt is a nonmaskable interrupt. It is unaffected by any mask or
interrupt enable, TRAP has the highest priority. TRAP interrupt is edge and level
triggered. This means that the TRAP must go high and remain high until it is
acknowledged. This avoids false triggering caused by noise and transients.
As shown in the Fig. 1.18, the positive edge of TRAP signal sets the D flip-flop.
However, due to the AND gate, it is necessary to sustain high level on the TRAP input.
‘There are two ways to clear TRAP interrupt :
1. By resetting microprocessor ie. giving a low signal on RESETIN pin (External
signal)
2. By giving a high TRAP ACKNOWLEDGE (Internal signal) Microprocessor 1-23 Introduction to Intel 8085 Microprocessor
RESET IN.
ACKNOWLEDGE
Fig. 1.18 Interrupt circuit for trap interrupt
After recognition of TRAP interrupt, 8085 internally generates a high TRAP
ACKNOWLEDGE which clears the flip flop. Once the TRAP is acknowledged, the 8085
completes its current instruction. It then pushes the address of the next instruction ic.
retum address onto the stack and loads PC with the fixed vector address 0024H. Due to
this, 8085 starts execution of instructions from address 0024H which is the starting address
of an interrupt service routine for TRAP.
RST 7.5 : The RST 75 interrupt is a maskable interrupt. It has the second highest
priority. As shown in Fig. 1.17, it is positive edge triggered and the positive edge trigger
is stored internally by the D flip-flop until it is cleared by software reset using SIM
instruction or by internally generated ACKNOWLEDGE signal,
‘The positive edge signal on the RST 7.5 pin sets the D flip flop. If the mask bit M7.5
is 0 ic. RST 7.5 is unmasked then 8085 completes its current instruction. It then pushes the
address of the next instruction onto the stack and loads PC with the fixed vector address
003CH. Due to this, 8085 starts execution of instructions from address 003CH which is the
starting address of an intecrupt service routine for RST 7.5.
RST 6.5 and RST 5.5 : The RST 65 and RST 5.5 both are level triggered. These
interrupts can be masked using STM instruction. The RST 6.5 has the third priority whereas
RST 5.5 has the fourth priority. The vector addresses of RST 6.5 and RST 55 are 00341
and 002CH respectively. After recognition of RST 6.5 or RST 5.5 interrupt, 8085 completes
its current instruction; pushes the address of next instruction onta the stack and loads PC
with corresponding vector address.
INTR : INTR is a maskable interrupt, but not the vector interrupt. It has the lowest
Priority. The following sequence of events occur when INTR signal goes high
1, The 8085 checks the status of INTR signal during execution of each instruction.
2. If INTR signal is high, then 8085 completes its current instruction and sends an
active low interrupt acknowledge signal (INTA) if the interrupt is enabled. Microprocessor 1-24 Introduction to Inte! 8085 Microprocessor
3. In response to the INTA signal, external logic places an instruction OPCODE on
the data bus. In the case of multibyte instruction, additional interrupt acknowledge
machine cycles are generated by the 8085 to transfer the additional bytes into the
microprocessor.
4. On receiving the instruction, the 8085 saves the address of next instruction on stack
and executes received instruction.
Note : Theoretically, the external logic can place any instruction code on the data bus
in response to the INTA, However, only CALL and RST codes save the contents of the PC
on the stack and branch program control to the subroutine address.
Response for RST instruction : If the external device places an opcode for any one of
the RST instruction (RST 0 - RST 7), then 8085 pushes the contents of PC onto the stack. It
then branches the program control to the vector address of the corresponding RST
instruction.
Response for CALL instruction : If the external device places an opcode for CALL
instruction then 8085 generates two additional interrupt acknowledge cycles
1. It sends an active low interrupt acknowledge signal second time.
2. In response to second INTA signal, external logic places the lower byte address for
the CALL instruction.
3. After receiving lower byte address, 8085 sends the third interrupt acknowledge
signal.
4. In response to third INTA signal, external logic places the higher byte address for
the CALL instruction.
5. After receiving sixteen bit address for CALL, 8085 pushes the contents of the PC
‘onto the stack and branches the program control to the subroutine whose address
is received from the external logic.
Example : The Fig. 1.19 shows the diagram of external logic that gives the RST 7
instruction opcode on interrupt acknowledge.
External logic controls a tri-state buffer with the INTA signal in order to place an
opcode for RST 7 instruction. The INTA signal from the microprocessor is used as an
output enable signal for the buffer as well as reset signal for D flip-flop. The request from
the I/O device is routed through the D flip-flop to the INTR. The D flip-flop is used to
‘hold the INTR signal high until 8085 gives interrupt acknowledge signal. The INTA signal
that is generated enables the tri-state buffer whose data inputs are hardwired to the value
equal to the opcode for RST 7 (FFH) instruction. The 8085 receives this opcode during
interrupt acknowledge cycle. After receiving the opcode 8085 pushes the contents of
Program Counter onto the stack, thus saving the return address. It then branches the
Program control to the address 0038H (Vector address of RST 7). Table 1.3 shows the
summary of hardware interrupts in 8085. Microprocessor 1-25 Introduction to Intel 8085 Microprocessor
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