International Journal of Scientific Engineering and Applied Science (IJSEAS) - Volume-1, Issue-3, June 2015

ISSN: 2395-3470
www.ijseas.com

Design & Implementation of I2C Protocol P P

Chinmay Modi , Heli Shah , Bhargav Tarpara3

1
P PR R
2
P P P

1, 2,
P M.Tech., VLSI, U.V.Patel College of Engineering and Technology, Kherva, Mehsana, India
P 2T 2T

3
Verification Technical Assistant, eiTRA, Ahmedabad, India
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Abstract—we
42T present design of an
42T

intellectual property (IP) for inter-integrated To exploit these similarities and benefit
circuit (I2C) bus protocol. To enable multiple
P P
to both systems designers and equipment
devices to communicate with each other over manufacturers and to maximize hardware
serial data bus without any data or address efficiency and circuit simplicity, that is why a
loss, as well as to enable faster devices with simple bidirectional 2-wire bus for efficient
slower ones. The inter IC(I2C) protocol was P P
inter-IC control. This bus is called the Inter IC
put forward by Philips semiconductors in 4th P P
or I2C-bus. All I2C-bus devices incorporate an
P P P P

April 2014. This protocol design proposed on-chip interface which allows them to
for reusability concept. In this paper, a communicate directly with each other via the
design on FPGA Platform is presented for I2C-bus. This design concept solves the many
P P

I2C protocol. Also proposed model is used for

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interfacing problems encountered when
communication between multiple masters designing digital control circuits [1]. The model
and multiple slaves. The entire design has can be used as a master, multiple masters or as a
been coded in verilog & verified using slave, multiple slave or both. We first present
Spartan kit. the characteristics of the I2C protocol and the P P

controller, then focus on the modeling of the IP

and show Simulation Results.
Keywords— IP(Intellectual Property), I2C(Inter
42T 42T P P

Integrated Circuit), FPGA(Field Programmable

II. I2C Bus Specification
Gate Array), Verilog, System Verilog(SV),
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Universal Verification methodology(UVM).

The I2C bus is containing two-wire
I. INTRODUCTION serial bus, one is for SDA (serial data) and other
is for SCL (serial clock). Each device has its
THE I2C-bus is a de facto world standard
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own unique address, and can work either as a

that is now implemented more than 103 P P

transmitter or a as a receiver. The I2C master is

different ICs manufactured by 50+ companies. the device that initiates a transfer and generates
Additionally, I2C-bus is used in various control P P

the clock for the same. Any device addressed by

architectures like System Management Bus the master is also the slave. If more than one
(SMBus), Power Management Bus (PMBus), master attempts to transmit in address or data,
Intelligent Platform Management Interface there will be a collision. The I2C specification
(IPMI), Display Data Channel (DDC) and solves this collision by its arbitration process,
Advanced Telecom Computing Architecture clock synchronization and also clock Stretching
(ATCA)[1]. There are many similarities concept. Before go to the arbitration process,
between seemingly unrelated design for various Clock synchronization process. The basic I2C
industries like consumer electronics, characteristics are given below. [2][3]
telecommunications and industrial electronics.
For Example, A. I2C Characteristics
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1. Some intelligent control in a single-chip

micro-controller. • Both Master and slave operation
2. EEPROM, A/D & D/A Converter. • Unique Start/Stop/Repeated Start
3. Audio-video systems, temperature sensor, condition
Digital imaging.

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 International Journal of Scientific Engineering and Applied Science (IJSEAS) - Volume-1, Issue-3, June 2015
ISSN: 2395-3470
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• Slave selection protocol uses a 7-bit transition from High to Low. Initially both are
slave address at high impedance (Z) and for STOP condition
• Bidirectional data transfer indicate that SCL must be high rising
• Data transfer Speed edge/state. And SDA line must follow the
1. standard mode - 100 Kbit/s transition from Low to High.[1][2]In software
2. fast mode - 400 Kbit/s simulation based verification, the HDL code of
3. High Speed mode - 3.4 Mbits/s the digital logic is simulated by the simulation
• Acknowledgement after each transferred software. Logic simulation is the primary tool
byte used for verifying the logical correctness of a
• No fixed length of transfer hardware design. In many cases, logic
• True Multi-master capability simulation is the first activity performed in the
process of taking a hardware design from
• Fully supports Clock synchronization &
concept to realization. Test-bench can be
arbitration process
written around the design under test (DUT) and
• Data stability
inputs can be passed to the DUT through the
• Programmable SCL frequency test-bench. Simulation is completely generic
• Soft reset of I2C Master/Salve and any hardware design can be simulated.
• Electrical & timing Specification[1] Setup is simple, quick and easy highest level of
controllability and observability Designer gets
B. I2C Addressing Format
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complete feedback of the verification process

[2] [3].
The various devices on the I2C bus can P P

be differentiated by their address. It contains 10

bit addressing mode. its 1st master send P P

start/repeated start condition, 2nd step, master P P

send 7 bit of particular slave device address out

of many devices.3rd step, if bit indicate 1 for
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read and 0 for write bit respectively. Then Figure 2: I2C Start & Stop Condition
4thstep, acknowledgement bit indicate that slave
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device address received successfully.5th step, P P

D. Acknowledgement
master sends data to slave device. 6th step P P

master received acknowledgement and then Master/slave receivers pull data line low for one
master sends a stop condition that indicate no clock pulse after reception of a byte. Master
more data or address will there. Finally stop the receiver leaves data line high after receipt of the
transaction. [1][2] last byte requested. Slave receiver leaves data
line high on the byte following the last byte it
can accept.(Figure3).Receiver leaves data line
high for one clock pulse after reception of a
byte.( Figure4) [2]

Figure 1: I2C Frame Format

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C. Start & Stop Condition Figure 3: Acknowledgment Reception

Every data/address transfer in this protocol first

requirement is start condition. START
condition indicates that SCL must be high rising
edge/state. And SDA line must follow the

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 International Journal of Scientific Engineering and Applied Science (IJSEAS) - Volume-1, Issue-3, June 2015
ISSN: 2395-3470
www.ijseas.com

state of the SCL line because all masters started

counting their HIGH period. So, the first master
to complete its HIGH period pulls the SCL line
LOW again. In that way, a synchronized SCL
clock will be generated with their LOW period
determined by master with its longest clock
LOW period, and their HIGH period
Figure 4: Negative Acknowledgement determined by one at the shortest clock HIGH
Reception period.[1]
D. Data stability

Every transfer of data byte direction flow is

MSB bit to LSB bit. Data should be consider
valid if SCL state is high. So SDA signal must
be remain stable during this period. [2]

Figure 6: clock synchronization

F. Arbitration

Figure 5: Data validity In I2C protocol, only master can involve in

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arbitration. Slaves are not involved in

E. Clock Synchronization arbitration. Master initiate transfer only and
only when bus is idle. Two masters may initiate
When two masters begin transmitting on a free a START condition within the minimum hold
bus at a same time then there must be a time of the I2C bus START condition for which
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procedure to decide which takes control and gives in a valid START condition on it.
which not. This is done by the clock Arbitration is needed to check which master
synchronization and arbitration procedure. will complete their transmission as early as
possible. There is no data lost in it. The
In clock synchronization, wired-and connection advantage is that two master can complete its
can be performed in i2c interface to SCL line. transmission without causing any hazard or
During high to low transition on SCL line start error. Arbitration procedure keeps sending
counted off their low period of concerned pattern bit by bit. When the SCL is gone high it
master. If master clock goes LOW, Then it also will also verify SDA level for which is sent. For
holds the SCL line until the clock remains the the first time a master try to initiates or generate
HIGH state. However, if another clock will a HIGH period, but that will be detecting the
remain at its LOW period, then during the LOW SDA level also gone LOW, the master knows
to HIGH shift of the clock it may not change that it will be lost the arbitration procedure and
the state of the SCL line. So, master held the turns off its SDA output driver. Another master
SCL line LOW with much long LOW period. goes to finish their entire transaction. If a
After that the shorter LOW period enters the master also incorporates a slave function and it
HIGH wait-state during this time by master. loses its arbitration during its address, there is
possible that the possibility of winning masters
When whole masters concerned about counted may attempt to address the master. There will
off their LOW period, so the clock line will be be losing master must be therefore switch over
release and goes HIGH. Then, there is no instantly to their slave mode. Figure shows the
difference between the master clocks & the arbitration procedure for all the masters. For the

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 International Journal of Scientific Engineering and Applied Science (IJSEAS) - Volume-1, Issue-3, June 2015
ISSN: 2395-3470
www.ijseas.com

moments there can be dissimilarities between We can also receive acknowledgement from
the internal data level of the master initiating slave. Whole operation can perform in
DATA1 and also actual level on the SDA line, bidirectional way because Slave may be master
and the DATA1 output could be also switched or master Slave. Address and data will be
off. That won’t affect any of the data transfer generated on SDA line also correlating to the
initiated by the winning master. Since Final SCL line. All devices of (slaves) connected to
control of the I2C-bus is decided on address and the I2C bus should be follow the wired- and
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data sent by true competing masters, there condition. If the I2C bus is idle than it goes to
won’t be centralize master inside it, nor any high impedance state. Whether the BUS is
higher priority master given on the bus.[1][3] ‘high’, the Master instantly captures the I2C bus
by pulling down the BUS line to a ‘low’ state.
whether two masters trying to get the bus at the
same time, then the most winning one master
control will be decided by following the I2C
arbitration logic.[1] Functional block diagram
is described as below.

Figure 7: arbitration of two master

G. Clock stretching

Clock stretching is some time pause a

transaction by holding the SCL line LOW at Figure 8: Functional Block Diagram
some duration. So the transaction won’t
continue until & unless the line will be released
A. Master/Slave Top Level Block
HIGH. Generally Clock stretching is usually not
for multiple slaves. So it is optional and In fact, Master basically Consist five Operations like
most of the slave devices are not include an initiator for start and stop condition, Address
SCL driver so they are not chances to stretch for particular Slave device, Write data to Slave
the clock. For example some device may send vice versa, Read data from Slave vice versa,
data at a faster rate but need more time to store Clock generator.
it So slave then hold SCL line low after
reception and receive acknowledgment of a
byte to force the master enter into a wait state
until particular slave is ready for the next byte
of transfer in a type of handshake procedure.
[1][4]
III. DESIGN & IMPLEMENTATION OF
THE IP

In I2C Protocol, we have been design

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master block and slave block. In I2C protocol, P P

Master can be work as a Slave same as Slave Figure 9: Master /Slave Top module
can be work as Master respectively. In Design, I Table1 indicates the pin and port connection of
have implemented format of the I2C frame. P P
I2C Master/Slave.
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I2C.Master can generate a start and stop

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condition, send address or data towards slave.

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 International Journal of Scientific Engineering and Applied Science (IJSEAS) - Volume-1, Issue-3, June 2015
ISSN: 2395-3470
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Port width mode Description ack_error 1 Buffer 0: no

name acknowledge
Clk 1 In System clock. errors.
reset_n 1 In Asynchronous 1: at least one
active low reset. acknowledge
Ena 1 In 0: no transaction error occurred
is initiated. during the
1: latches in transaction.
addr, rw, and ack_error clears
data_wr to itself at the
initiate a beginning of
transaction. If each transaction.
ena is high at the Sda 1 In out Serial data line
conclusion of a of I2C bus.
transaction (i.e. Scl 1 In out Serial clock line
when busy goes of I2C bus.
low) then a new
address, Table 1: Pin-port description
read/write 2
B. I C Master/Slave state machine
command, and
data are latched I2C master and slave state machine
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in to continue explained in Figure10 that is generate all

the transaction. mechanism of I2C-bus protocol. If any address
Addr 7 In Address of of the device is detected so enable signal goes
target slave. high and generate the start condition. Before
Rw 1 In 0: write that it will first enter to a ready state. If the start
command. condition is done successfully then it will go to
1: read command state. Command state remains as it is
command. if bit count is not equal to 0. It means last bit is
data_wr 8 In Data to transmit not received; then it will communicate the
if rw = 0 (write). address and rw command towards the bus. If rw
data_rd 8 Out Data received if bit is 0 then write Operation else read operation.
rw = 1 (read). If bit count is 0 (last bit received) of any rw
Busy 1 Out 0: I2C master is operation than goes to slv_ack1 state that is
idle and last read used to get and verifies the correctness slave’s
data is available acknowledge. Once read write operation
on data_rd. complete, then master will store and verifies the
1: command has correctness of slave response (slv_ack2 state)
been latched in for writing & mstr_ack state for reading
and transaction respectively. Whether enable signal generates
is in progress. another command, then master instantly switch
with second write (wr ) & read (rd ) state
whether command (cmd state)is the same as
with previous than rw state must be
interchangeable. Whether Command state is not
same as previous one, If any new slave address
is detected then master will generate a repeated
start condition(start state) as per the I2C
specification. If master finish a read & writes
operation also ena signal is not generating any

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 International Journal of Scientific Engineering and Applied Science (IJSEAS) - Volume-1, Issue-3, June 2015
ISSN: 2395-3470
www.ijseas.com

more command, then the master will issues stop IV.IMPLEMENTATION RESULTS
condition (stop state) and go back to We have done the simulation of
the ready state. In slave state machine only state complete I2C frame format on Xilinx ISE
operation of slave acknowledgement and master simulator. Also we cross check the Design work
acknowledgement will change nothing else. as per the FSM or not. This design is for I2C P P

master to slave communication. The simulation

waveform results indicate how data and address
transmission are occurring.

Figure 12: Master to slave Communication.

V.APPLICATIONS
I2C Protocol can be used in many devices
like computer camera, EEPROM, Audio-Video
recording devices. The example is given below.
Figure 10: I2C Master Finite state machine
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Only two wires can connect so many devices
but at a time one will be activate.[1]

Figure 13: Example of I2C Devices

CONCLUSION

In a nutshell, The I2C master is basically

includes programmable logic that can be used to
communicate with I2C slaves bypass to a
Figure 11: I2C Slave Finite machine State parallel interface. This protocol can be work as
Diagram a NXP I2C specification only for single master

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 International Journal of Scientific Engineering and Applied Science (IJSEAS) - Volume-1, Issue-3, June 2015
ISSN: 2395-3470
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buses and also added feature of clock

stretching.

MOTIVATIONAL WORK

This I2C can be work as a multi master and

multi slave. The idea is that we can use
multiplexer and de-multiplexer to select
particular master and slave selection. We can
also verifying test cases using system verilog
environment and check all phases in universal
verification methodology. Finally check the
ASIC backend Flow & Design will be ready for
Tap out.

REFERENCES

[1]THE I2C BUS SPECIFICATION

VERSION 6.0 4th April, 2014, Philips
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Semiconductors.

[2]M. Alassir, J. Denoulet, O. Romain & P.

Garda: A systemc AMS Model of an I2C
Bus Controller.

[3]P.Venkateswaran, Madhumita Mukherjee,

Arindam Sanyal, Snehasish Das and
R.Nandi: Design and Implementation of
FPGA Based Interface Model for Scale-Free
Network using I2C Bus Protocol on Quartus
II 6.0.

[4]Peter Corcoran: Two wires and 30 years.

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