& MOTOROLA SEMICONDUCTORS Pron Coed SN74LS783/ MC6883 SN74LS785 Advance Information SYNCHRONOUS ADDRESS MULTIPLEXER The SN74LS783/MC6883 and SN74LS785 bring together the MC6809E (MPU), the MC6847 (Color Video Display Generator) and dynamic RAM to form a highly effective, compact and cost effec- tive computer and display system. ‘The SN74LS783/MC6883 is designed to support 4K x 1, 16K x 1 and 64K x 1 (128 column refresh) dynamic RAMs. The SN74LS785 has been modified to support the above listed prod- Ucts as well as 16K x 4 and 64K x 1 (256 column refresh) dynamic RAMs. A further enhancement allows the LS785 to support low power dynamic ROMs (such as MCM68364) without additional logic. ‘© MC6s09E, C6800, MC6B01E, MC68000 and MC8847 (VDG) Compatible ‘© Transparent MPUVDGIRefresh ‘© RAM size — 4K, 8K, 16K, 32K or 64K Bytes (Dynamic or Static) ‘© Addressing Range — 96K Bytes © Single Crystal Provides All Timing ‘© Register Programmable: VDG Addressing Modes VDG Offset (0 to 64K) RAM Size Page Switch MPU Rate (Crystal = 16 or ~ 8) MPU Rate (Address Dependent or Independent) © System “Device Selects" Decoded ‘On Chip’ ‘© Timing is Optimized for Standard Dynamic RAMS © +5.0.V Only Operation © Easy Synchronization of Multiple SAM Systems © DMA Mode TYPICAL SYSTEM BLOCK DIAGRAM Device Selects 8 SN74LS138 EEE ‘80-52 ‘SN74LS783/ Miceas3 or SN74LS785 ‘SAM TV Display Section is Optional Address [AO-ATS: oma To ROMs and | MceB09E vo MPU 20-27 CAS. RAS WE| DYNAMIC RAM 4K, 8K, 16K BK oF 6A agzal Data Do-D7 SYNCHRONOUS ADDRESS MULTIPLEXER LOW POWER SCHOTTKY YH" SUFFIX PLASTIC PACKAGE CASE 711 Y ‘J SUFFIX ‘CERAMIC PACKAGE CASE 734 PIN ASSIGNMENT 1g Voc 40 2g Ai2f3 39 3q A135 38 aq ara 37 sc A155 36 6 27 36 (RAST) 7 2655 34 eq 2515 33 7 24k 32 we 23 31 nq 2255 30 rq 215 29 3c 20/5 28 “wo sof 27 so si 26 6 8255 25 vo a7 24 6 AGE 23 2a ASE 22 20 46nd Aah 21 ‘This document contains information on @ new prodvet. Specifications and information herein re subject to change without notice. ‘MOTOROLA ING, 1984 "ADI-S95R2CURSE KI ERM RYE) MAXIMUM RATINGS (Ta 25°C unless otherwise noted.) Rating Symbol | Value Unit Power Supply Voltage Vec_|-0.8to +7.0| _vde Input Voltage (Except Oscin) vi | 0510 | vac Input Current (Except Oscin) | -30t0 +50] ma ‘Output Voltage Vo [-058to +7.0| Vde Operating Ambient Temperature Range Ta_| Oto +70 °c Storage Temperature Range Tstg_|-65to +150[ “Cc Input Voltage Oscin Vidscin | -0.5 to Vec| Vac Input Current Oscin Hosein [=0.5 to +5.0| mA GUARANTEED OPERATING RANGES Parameter ‘Symbol Min Typ, Max Unit ‘Supply Voltage Vec. 475 50 5.25 Vv Operating Ambient Temperature Range Ta 0 25 75 cy Output Current High Tou mA. 'RASO, RAST, CAS, WE = - -10 All Other Outputs = = 02 ‘Output Current Low Tow mA ASO, RAST, CAS, WE = = 80 valk = = 08 All Other Outputs = = 40 DC CHARACTERISTICS (Unless otherwise noted specifications apply over recommended power supply and temperature ranges.) Characteristic Symbol [Min Tye Max Units Input Voltage — High Logic State Vin 2.0 = = v Input Voltage — Low Logic State Vi. = = 08 v Input Clamp Voltage Vik = = 15 v (ec = Min, lin = ~18 mA) All Inputs Except Oscin Input Current — High Logic State at Max Input Voltage 1 ry (cc = Max, Vin = 5.25 V) VCIk Input - = 200 (ec = Max, 5.25 V) DAO Input - = 100 (Voc = Max, Vin = 5.25 V Oscin = Gnd) Oscout Input - = 250 (VGC = Max, Vin = 7.0 V) All Other Inputs Except Oscin = = 100 Input Current High Logie State All Inputs Except VCIk, iH uA (ec = Max, Vin = 27 V) DAO Oscjn, Oscout = = 20 Input Current — Low Logie State Me mA (Vcc = Max, Vin = 0.4 V) DAO Input = = -12 (VCC = Max, Vin = 0.4 V) VCIk Input = -30 60 (ee 0.4 V, Oscjn = Gnd) Oscout Input - - -8 Wee 0.4 V) All Other Inputs Except Oscin = = -4 ‘Output Voltage — High Logic St Vv (ec = 1.0 mA) RASO, RAS, CAS, WE Vouic) 3.0 - - (ec 0.2 mA) E, Vouie) |Ycc - 0.75] — = (ee =0.2 mA) All Other Outputs. Vou 27 = = Output Voltage — Low Logie State _ Vv (Vcc = Min, lol = 8.0 mA) RAS E Vouie) - - 05 (ec = Min, lol = 4.0 mA) E, Q Outputs Vouie} = - 05 (ec = Min, lol = 0.8 mA) VCIk Output Vou) - - 06 (ec = Min, loc = 4.0 mA) All Other Outputs Vo = = 05 Power Supply Current lec. = 180 230 mA. Output Short-Circuit Current los 30. = 225 mA. ® MOTOROLA Semiconductor Products Inc. 2SN74LS783/MC6883 ¢ SN74LS785 AC CHARACTERISTICS (4.75 V=Vcc<5.25 V and 0| a3 19 BE | a2 18 al 7 a0 16_| Least Significant Bit RW 15 | MPU READ or WRITE. This signal comes directly from the MPU and is used to enable writing to the SAM control register, dynamic RAM (via WE), and to enable device select #0. Oscin 5_| Apply 14.31818* MHz erystal and 2.5-30 pF trimmer to ground, See page 12. DAO 8 | Display Address DAO. The primary function of this pin is to input the least significant bit of @ 16-bit video display address. The more significant 16-bits are outputs from an internal 16-bit counter which is clocked by DAO. The secondary function of this pin isto indirectly input the 3 logic level of the VOG “FS” (field synchronization pulse) for vertical video address updating, 8 =| 7s 9 | Horizontal Synchronization. The primary function of this pin is to detect the falling edge of 8 \VDG “HS” pulse in order to initiate eight dynamic RAM refresh cycles. The secondary function is to reset up to 4 least significant bits of the internal video address counter. vetk 7. | VDG Clock. The primary function of this pin is to output a 3.579545 Miz square wave** to the VDG "Cik” pin. The secondary function resets the SAM when this VCik pin is pulled to logie 0" level, acting as an input. Oscour | 6 | Apply 1.5 kM resistor to 14.31818* MHz crystal and 33 pF capacitor to ground. See page 12. s2 25 | Most Significant Bit (Device Select Bits). The binary value of S2, S1, SO selects one of eight g| s1 26 | “"chunks"’ of MPU address space (numbers 0 through 7). Varying in length, these “chunks” 3 provide efficient memory mapping for ROMs, RAMs, Input/Output devices, and MPU Vectors. 3 (Requires 74LS 138-type demultiplexer). so 27_| Least Significant Bit ele 14 | E (Enable Clock) “E” and “A” are 90° out of phase and are both used as MPU clocks for the 2: MC6809E. For the C6800 and MC68O1E, only "E" is used. "Eis also used for many MC6B00 2l2S peripheral chips. = a 13_| QtQuadrature Clock) 3 zt 35 | Most Significant Bit 8) | zor 34 | First, the least significant address bits from the MPU or "VDG" are presented to Z0-Z5 (4K 8, 8] 25 33 | x 1 RAMs) or 20-26 (16K x 1 RAMs) or Z0-Z7 (64K x 1 RAMs). Next, the most significant 3 8) zat 32 | address bits from the MPU or “VDG" are presented to Z0-Z5 (4K x 1 RAMs) or Z0-Z6 = 3] zor 31 | (16K x1 RAMs) or 20-27 (64K x 1 RAMS). Note that for 4K x 1 and 16K x 1 RAMs, 27 (Pin | 22 30 | 35) is not needed for address information. Therefore, Pin 35 is used for a second row zit 29 | address select which is labeled (RAS1).. zor 28 _| Least Significant Bit RASit | 35 | Row Address Strobe One. This pulse strobes the least significant 6,7 or 8 address bits into 7 dynamic RAMs in Bank #1 = £| RASGt | 12 | Row Address Strobe Zero. This pulse strobes the least significant 6,7 or 8 address bits into Se) dynamic RAMs in Bank #0. 8| cast 11 | Column Address Strobe. This pulse strobes the most significant 6,7 or 8 address bits into dynamic RAMs. Wer 10_| Write Enable. When low, this pulse enables the MPU to write into dynamic RAM, 14.31818 MHz is 4 times 3.579545 MHz television color subcarrier. Other frequencies may be ‘*When VDG and SAM are not yet synchronized the "square wave" will stretch (see page 10.) + Due to fast transitions, ferrite beads in series with these outputs may be necessary to avoid high frequency (~ 60 MHz) resonances. 10d. (See page 12) & MOTOROLA Semiconductor Products Inc. 4be. mao mom m0 MOTS = 4lVY Naw 40} SWHOJ3AVM ONINLL — Z aNd Semiconductor Products Inc. 5 a & MOTOROLAASvd = aLvY naw 40} sWHOJaAVM DNIWLL — € 3uNDH 6 Semiconductor Products Inc. a ®& MOTOROLAFIGURE 4 — SAM BLOCK DIAGRAM s2 st so Voc Gnd Mf) fi 111 = SFFCO- FOF ress Refresh Fetresh Decode Request Grant of Refresh Counter cpl ose « 16 ten ™ | az — [os_os a4 a3 a2 1 00 ous i togie f_ ___| - % | | | | ¥ y ps pela ee cs ca es ce er co Control Register 9 a asc} 4 ois}? 6 ‘ [Nol ats. P| awd | are euje— 2 Fs anc} Aol ais ora { “2 + fa aT} —4 | a2 ore 2 8 Joao and an anh 2 aot tml aro viol 2 A —, ac | 49 20 ef o2 Fo i: 3 aq ]As (See page atorsignar 88 Lf =2] 3 ves routing and timing) = é a} —4 oa ar fez] § preqer Ring 8 SR verk as] ol as as }+f-2] 3] 22} —Jve H q —+,°|22 as | As «peek " ey as} | aa «eek > HER ad 49 a2 jf 2 m os r my xq >| a2 o je -2 Mo Co [Automatic aq “Ar Br Yon ay | {internal ae Vcc! no >| L__f% qG a0 80 KON pcroch Ro 27 26 zs 24 2 22 21 20 | AeUGeh ry pip Siete A 3 t liponer el it axa Potarity ae [Select (AO-Aa) af2 _ . nw AW “by window RAST E Master p> Start ah : p= Timing " 0 Select a= Bosc m 3 +3 898° sosc o #f8 ‘8 = be 1 oscous yy yyy yy y | —aaF Doo dou min Dean RAD mans GE WE Dots indicate which internal signals reset logic blocks ‘Thee signaaogic not used by LS782 & MOTOROLA Semiconductor Products Inc. 7‘SAM BLOCK DIAGRAM DESCRIPTION MPU Addresses (A0-A15): These 16 signals come directly from the MPU and are used to directly address up to 64K memory locations (K = 1024) or to indirectly address up to 96K memory locations, by using a paging bit “P” (see pages 17 and 18 for memory maps). Each input is approximately equivalent to one low power Schottky load. VDG Address Counter (B0-B15) These 16 signals are derived from one input (DAO) which is the least significant bit of the VDG address. Most of the counter is simply binary. However, to duplicate the various addressing modes of the MC6847 VDG, ADDRESS MODIFIER logic is used. Selected by three VDG mode bits (V2, V1, and VO) from the SAM CONTROL REGISTER, eight address modifications are obtained as shown in Figure 5. Also, notice that bits B9-B15 may be loaded from bits FO-F6 from the CONTROL REGISTER. This allows the starting address of the VDG display to be offset (in 1/2K increments) from $0000 to $FFFFt. B9-B15 are loaded when a VERTICAL, PRE-LOAD (VP) pulse is generated. VP goes active (high) when HS from the VDG rises if DAO is high (or a high impedance). This condition should occur only while the TV electron beam is in vertical blanking and is simply imple- mented by connecting FS and MS together on the MC6847. The VP pulse also clears bits B1-B8. _ Finally, a HORIZONTAL RESET (HR) pulse may also affect the counter by clearing bits B1-B3 or B1-B4 when HS from the VDG is LOW (see Figure 5). The HR pulse should occur only while the TV electron beam is in horizontal blanking. In summary, DAO clocks the VDG ADDRESS COUNTER; HR initializes the horizontal portion and VP initializes the vertical portion of the VDG ADDRESS COUNTER. REFresh Address Counter (00-07) A seven bit binary counter (the LS785 uses an 8-bit counter) supplies bursts of eight* sequential addresses triggered by a HS high to low transition. Thus, while the TV electron beam is in horizontal blanking, eight sequential addresses are accessed. Likewise, the next eight addresses are accessed during the next horizontal blanking period, etc. In this manner, all 128 addresses are refreshed in less than 1.1 milliseconds. Address Multiplexer: Occupying a large portion of the block diagram in Figure 4, is the address multiplexer which outputs bits Z0-Z7 (as addresses to dynamic RAM’s). Inputs to the address multiplexer include the VDG address (B0-B15) the REFresh address (CO-C6) and the MPU address (A0-A15) or (A0-A14 plus one paging bit “P"). The paging bit “P” is one bit in the SAM CONTROL REGISTER that is used in place of A15 when memory map TYpe #0 is selected (via the SAM CONTROL, REGISTER “TY” bit) igure 6 shows which inputs are routed to Z0-27 and when the routing occurs relative to one SAM machine cycle. Notice that 27 and RAST share the same pin. 27 is selected if “M1” in the SAM CONTROL REGISTER IS HIGH (Memory size = 64K\) Address Decode: At the top left of Figure 4, is the Address Decode block. Outputs $2, S1, and SO form a three bit encoded binary word(S). Thus $ may be one of eight values (0 through 7) with each value representing a different range of MPU addresses. (To enable peripheral ROM’s or VO, decode the $2, S1, and SO bits into eight separate signals by using a 74LS138, 74LS155 or 74LS156.) On the LS783, the S2, $1 and SO outputs are not gated with any timing signals. The LS785 forces the S outputs HIGH if accessing ROM (see Memory Map, Figures 14-16) when the E clock is LOW and the Q clock is HIGH (see Timing Diagram, Figures 2-3). This logic implementation allows the LS785 to easily interface with inexpensive “dynamic” ROMs such as MCM68364. ‘Along with the A5-A15 inputs is the MEMORY MAP TYpe bit (TY). This bit is soft-programmable (as are all 16 bits in the SAM CONTROL REGISTER), and selects one of two memory maps. Memory map #0 is intended to be used in systems that are primarily ROM based. Whereas, memory map #1 is intended for a primarily RAM based system with 64K contiguous RAM locations (minus 256 locations). The various meanings of S2, $1, SO are tabulated in Figure 16 (page 19) and again on pages 17 and 18. In addition to $2, S1, and SO outputs is a decode of $FFCO through $FFDF which, when gated with E and RW, results in the write strobe for the SAM CONTROL REGISTER. SAM Control Register ‘As shown in Figure 4, the CONTROL REGISTER has 16 “outputs”: VDG Addressing Modes: V2, V1, VO MPU Rati R1, RO VDG Address OFFset: F6, F5, F4, F3, F2,F1,F0 | Memory Size (RAM): M1, Mo 32K Page Switch:*** Pp Memory Map TYpe: tv When the SAM is reset (see page 10), all 16 bits are cleared. To set any one of these 16 bits, the MPU simply writes to a unique** odd address (within SFFC1 through $FFDF). To clear any one of these 16 bits, the MPU simply writes to a unique** even address (within $FFCO through $FFDE). Note that the data on the MPU data bus is irrevelant. Inputs to the control register include Ad, A3, A2, A1 (which are used to select which one of 16 bits is to be cleared or set}, AO (which determines the polarity ... clear or set), and R/W, E and SFFCO-SFFDF) (which restrict the method, iming and addresses for changing one of the 16 bits). For more detailed descriptions of the purposes of the 16 control * IFRS is hold tow longer than 8 us, then the number of sequential addresses in one refresh “BURST” is proportir which BS is low. *+ See pages 17 oF 18 for specific addresses. + The P bits also used to select 16K x 4 bt dynamic RAM operation inthe LS786. See the Page switch definition inthe Programming Guide section. ‘In tis document, the "S” symbol always preceeds hexidecimal characters ()) MOTOROLA Semiconductor Products Inc. 8 1 the time interval duringbits, refer to related sections in the BLOCK DIAGRAM DESCRIPTION (pages 8 through 12) and the PROGRAMMING GUIDE (pages 14 through 18). + See pages 17 o 18 for specific addresses. FIGURE 5 — VDG ADDRESS MODIFIER ‘Mode Division Variables Bits Cleared by HS (low) v2 vivo x Y oo oO 1 12 | BI-B4 oo 1 3 1 81-83 o 1 0 1 3 | BI-Ba o 4 41 2 1 BI-B3 1 0 0 1 2 ‘| Bree 1 ot 1 1 Bi-83 1 1 0 1 1 Bi-B4 at 1 1 None (DMA MODE} FIGURE 6 — SIGNAL ROUTING for ADDRESS MULTIPLEXER ‘Memory Size Signal | RowiGolumn ‘Signals Routed to 20-27 Timing Mi_MO| Source zm [we] 2 | zm | 2 | 2] 21 | 20 | (Figure2) 4KO 0 0 | MPU | ROW @ [as [as | aa [as | az | ar [ao | TA COL @ [tow] an | aw | as | as | A? | AB | TACTF voG ROW @ | se | os | 8s | es | o2 | oi | 60 | TRT2 COL @ [tow] en | so | es | es | a7 | ee | 27 REF ROW @ [ce [cs [cs [cs | ce [cr | coo | tt COL @ | tow | tow | tow | tow | tow | tow | tow | 12-17 1eKxt 0 1 | MPU | ROW @ [as | as | as | as | a2 | ar | ao | TTA cou, @ [as | az an | ato | as | As | A? | TATE voG ROW @ | ee [es | sa | 63 | 62 | 61 | 60 | TRT2 COL @ | eis | oz | em | sto | 69 | es | a7 | 217 REF ROW @ [ce [os [cs [os [co [or [oo | mr COL @ | cow | tow | tow | tow | tow | tow | tow | 12-17 1eKx4 0 1 | MPU | ROW ar_| as | as | aa | as | Az | A1_| AO | TTA (Page bit = 1) cou. @ | ais | a [ am | ato [as | as [a7 | TATF vos [_ROW 7 | 66 | 5 | 84 | 83 | 2 | 61 | 80 | TRT2 oy COL @ [sis | pz | e1 | a0 | eo | es | o7 | 27 only available REF ROW o [ce [cs [cs [cs | c2 [or [oo | mr eee col. tow _| cow | tow | tow | tow | tow | Low | tow | 12-17 ‘64K (dynamic) MPU |_ROW ay | As | as | aa [as | a2 | At_| AO | TATA 1 0 cou paws | ata | ais | aiz | Att | Ato | Aa | AS | TATE voG ROW e7 | 86 | es | 84 | es | 82 | or | Bo | TRT2 cou eis | 614 | B13 | Biz | en | so | eo | Be | 1217 REF ROW c@ [ce [cs [cs [cs | c2 [cr | co | ter COL tow | tow | tow | Low | tow | tow | tow | tow | t2-T2 ‘4K (static) mPu |_ROW ar [as | as | aa | as | a2 | ai_| AO | 17-19 14 COL paisa | ata | ars | ai2 | att | ato | as | As | T9-1F vos [_ROW 7 | 66 | 65 | 84 | 3 | 2 | 61 | 60 | RTI COL Bis_| era | ers | B12 | B11 | B10 | es | es | THT7 REF ROW c@ [ce | os | ca | cs | c2 | cr | co | TT COL tow | tow | vow | tow | tow | Low | tow | tow | _t-17 {© When using 4K x 1 RAMs, two banks of eight IC's are allowed. This accounts for Addresses $0000-1FFF. Also, this same RAM can be addressed at $2000-S3FFF, $4000-S5FFF and $6000-$7FFF (227 functions as FAST and its level is address dependent. For example, when using two banks of 16K x 1 RAMs, FASO is active for addresses '$0000 to $3FFF and RAST is active for addresses $4000 to $7FFF, If Map TYpe ~ 0, then page bit "P is the output otherwise ATS). Ths is 9 “don’t care” situation for 16K x 4 MOS RAM inputs. @C7 = Low on 18783. & MOTOROLA Semiconductor Products Inc. >ESP CIRS ERI eM RD) Internal Reset By lowering Vcc below 0.6 volts for at least one econd, a complete SAM reset is initiated and is completed within 500 nanoseconds after Vcc rises above 4.25 volts. NOTE: In some applications, (for example, multiple “‘VDG-RAM” systems controlled by a single MPU) multiple SAM ICs can be synchronized as follows: © Drive all SAM's from one external oscillator. © Stop external oscillator. * Lower Vcc below 0.6 volts for at least 1.0 millisecond. ® Raise Vcc to 5.0 volts. ‘© Start external oscillator. © Wait at least 500 nanoseconds. Now, the E” clocks from all SAM’s should be in-phase. External Reset When the VCik pin on SAM is forced below 0.8 volts for at least eight cycles of “oscillator-out”, the SAM becomes partially reset. That is, all bits in the SAM control register are cleared. However, signals such as RAS, CAS, WE, E or Q are not stopped (as they are with an internal reset), since the SAM must maintain dynamic RAM refresh even during this external reset period. Figure 7 shows how VCIk can be pulled low through diode D1 when node “A is low.* When node “A” is high, only the backbiased capacitance of diode D1 loads the 3.58 MHz on VCIk. Diode D2 helps discharge C1 (Power-on-Reset capacitor) when power is turned off. Diode D3 allows the MPU reset time constant R2C2 to be greater than the SAM reset time constant. Thereby, ensuring release of the SAM reset prior to attempting to program the SAM control register. FIGURE 7 — EXTERNAL RESET CIRCUITRY +5.0V +5.0V 100 ka Manus! System -f Reset Switch’ Volk clk SAM voc MPU cess Mices47 MCB803E VDG Synchronization In order for the VDG and MPU to share the same dynamic RAM (see page 13,) the VDG clock must be stopped until the VDG data fetch and MPU data fetch are synchronized as shown in Figure 12. Once synchronized, the VDG clock resumes its 3.579545 MHz rate and is not stopped again unless an extreme temperature change (or SAM reset) occurs. When stopped, the VDG clock remains stopped for no more than 32 Oscgut cycles (ap- proximately 2 microseconds.) In the block diagram in Figure 4, DAO enters a block labeled VDG Timing Error Detector. If DAO rises between time reference points** ta and zc, then Error is high and VCIk is the result of dividing BOSC (Buffered Oscoyt ~ 14 MHz) by four. However, if DAO rises outside the time Window za to 7c, then Error goes LOW and the VDG stops. A START pulse at time reference point 7g (center of Window) restarts the VDG . . . properly synchronized. 2 diode with sufficiently low forward voltage drop to meet Vit requirement at VCIk. timing diagrams on page 6 and 6. & MOTOROLA Semiconductor Products Inc. 10SN74LS783/MC6883 © SN74LS785 Changing the MPU Rate (by changing SAM control register bits RO, R1). Two bits in the SAM control register determine the period of both “E” and “Q” MPU clocks. Three rate modes are implemented as follows: RATE MODE R1_RO ‘SLOW (0 0 | The frequency of “” (and “Q") is f crystal + 16. This rate mode is automatically selected when the SAM is reset. Note that system timing is least critical in this "SLOW" rate mode. AD. (01 _| The frequency of “€” (and “Q") is either f crystal ~ 16 or f crystal + 8, depending on the address (Address Dependent) | the MPU is presenting. FAST 1X | The frequency of E”" (and “Q") is f crystal + 8. This is accomplished by stealing the time that is normally used for VDG/REFRESH, and using this time for the MPU. Note: Neither VDG display nor dynamic RAM refresh are available in the “FAST” rate mode. (Both are available in SLOW and A.D. rate modes). When changing between any two of the three rate modes, the following procedures must be followed to ensure that MPU timing specifications are met: RATE MODE SLOW sw Sai _ This direct pathis AD Sequence #1 Tot allowed except by | Fast . “See Below! er varaware reset] Set RO, then CLEAR R1 May be ANY address from $0000 to $7FFF. SEQUENCE #1: 7D 00 00 TST #$0000 .. . Synchronizes STA instruction to write during T2-TG (See Figure #8).* 21.00 BRNOO 87 FF D6 STA #$FFD6 ... Cl rs bit RO ‘Note: "TST" instruction affects MCBSO9E condition code register. Changing the MPU Rate (In Address Dependent Mode) When the SAM control register bits ““R1", and “RO” are programmed to “0” and "1", respectively, the Address Dependent Rate Mode is selected. In this mode, the + 16 MPU rate is automatically used when addressing within $0000 to $7FFF* or $FFOO to $FF1F ranges. Otherwise the + 8 MPU rate is automatically used. (Refer to Figure 8 for sample “E” and “Q" waveforms yielding + 8 to + 16 and = 16 to + 8 rate changes). This mode often nearly doubles the MPU throughput while still providing transparent VDG and dynamic, RAM refresh functions. For example, since much of the MPU’s time may be spent performing internal MPU functions (address = $FFFF)**, accessing ROM (address = $8000 to $FEFF) or accessing I/O (address = $FF20 — $FF5F), the faster f crystal + 8 MPU rate may be used much of the time. Note: The VDG operates normally when using the SLOW or A.D. rate modes, However, in the FAST rate mode, the VOG is not allowed access to the dynamic RAM. FIGURE 8 — RATE CHANGE E AND Q WAVEFORMS. fast slow fast uy om “slow” address detected here “When using Memory Map 0, addresses $0000 to $7FFF may access Dyt ‘+The MCB809 outputs $FFFF on AO-A1S when no other valid addresses are being presented. ® MOTOROLA Semiconductor Products Inc. "SN74LS783/MC6883 © SN74LS785 Oscillator In Figure 4, an amplifier between Oscjy and Oscgyt provides the gain for oscillation (using a crystal as shown in Figure 9.) Alternately, Pin 5 (Oscin) may be grounded while Pin 6 (scout) may be driven at low-power Schottky levels as shown in Figure 10. Also, see Vy, Vi_ on page 2. AC Specifications* scour ‘Max Typ Min [Units tpH(Ose) | — 30 22 ns tpL (Ose) = 30 22 ns teye(Ose) |_ — 70 62.4 ng FIGURE 9 — CRYSTAL OSCILLATOR eee ‘Suggested Component Values Freq. mz | cvs | cre | aie | Hoe as-ao| a3 | 15 : ce | pe | ka [7 100K] 10K 26-30] 33 | 1.5 . re.0000 7°29 | Se | a |~ 100K] 10K SAM Mceae3 14,31818| Recommended Crystal Paramet 14.31818 MHa* 16.0000 MHz* a ll B Rg 10a = 200) won +200 co | 8.0pF= 1.8 pF | 6.0pF = 1.09F ; ct] 0.0248 f= 16% | cate nF = to SOE SL, ut 5.05 mi 2.1m @ ox = 10K 40K = 10K Calibration Tolerance: 0.002% at 26°C Temperature Tolerance: 0.001% 0°C to 70°C FIGURE 10 — TTL CLOCK INPUT 5 Oscin ra (Ra = 200 0 Typ, 50.0 Min) Bo Osc0u Ot) 741800 (Used as an input) ‘Typical input capacitances are 3.0 pF for Pin 5 and 5.5 pF for Pin 6. "Optimum values depend on characteristics of the crystal (X1). For many applications, VCIk must be 3.57954 MHz = 50 He! Hence, scout must be made similarly “drift resistant” (by balancing temperature coeficients of X1, CV, CF, RY, R2 and Ra). ‘*Speatially cut for the SAM are International Crystal Manufacturing, Inc. Crystals (#167568 for 14.31818 MHz or #167569 for 16.0 MHz) However, other crystals may be used. ® MOTOROLA Semiconductor Products Inc. 12THEORY OF OPERATION Video or No Video Although the SAM may be used as a dynamic RAM controller without a video display*, most applications are likely to include a MC6847 video display generator (VDG). Therefore, this document emphasizes use of the SAM with MC6847 systems. Shared RAM (with interleaved DMA) To minimize the number of RAM and interface chips, both the MPU and VDG share common dynamic RAM. Yet, the use of common RAM creates an apparent difficulty. That is, the MPU and VDG must both access the RAM without contention. This difficulty is overcome by taking advantage of the timing and architecture of Motorola MPU's (MC6800, MC6801E, MC6809E, MC68000). Specifically, all MPU accesses of external memory always occur in the latter half of the machine cycle, as shown below: FIGURE 11 — MOTOROLA MPU TIMING (One Machine Cycle opr mT J 1 r Y MPU Address MPU Data MPU Address MPU Data Window Window Similarly, the MC6847 (non-interlaced) VDG transfers a data byte in a half machine cycle (E or 2). Thus, when properly positioned, VDG and MPU RAM accesses interleave without contention as shown belo FIGURE 12 — MOTOROLA MPU WITH VDG TIMING VDG Data VDG Data VDG Address ise voG fees winson ‘€’ Clock (Approx. MHz) MPU Half |_voe! on} —_ —y--—_ Mpu cman oes MPU Data MPU Address. MPU Data Window Window This Interleaved Direct Memory Access (IDMA) is synchronized via the MC6883 by centering the VDG data window half-way between MPU data windows.** The result is a shared RAM system without MPU/VDG RAM access contention, with both MPU and VDG running uninterrupted at normal operating speed, each transparent to the other. RAM Refresh Dynamic RAM refresh is accomplished by accessing eight*** sequential row addresses every 64*** microseconds until all addresses have been accessed. To avoid RAM access contention between REFRESH and MPU, each of the refresh accesses occupies the “VDG half” of the interleaved DMA (IDMA). Furthermore, refresh accesses occur only during the television retrace period (at which time the VDG doesn’t need to access RAM). In summary, the VDG, MPU and SAMs Refresh Counter all transparently access the common dynamic RAM without contention or interruption. Why IDMA? Use of the interleaved direct memory access results in fast modification to variable portions of display RAM, by the MPU, without any distracting flashes on the screen (due to RAM access contention). In addition, the MPU is not slowed down nor stopped by the SAM; thereby, assuring accurate software timing loops without costly additional hardware timers. Furthermore, additional hardware and software to give “access permission” to the MPU is eliminated since the MPU may access RAM at any time. *Only 1 pin, (DAO) out of 40 pins is dedicated to the video display +See VDG synchronization (page 10) for more detail "When not using @ MCBSA7, HS may be wired low for continuous transparent refresh ® MOTOROLA Semiconductor Products Inc. 13PCRS ERI eke LRSYL Ld “Systems On on” Concept Total Timing For most applications, the SAM can supply complete system timing from its on-chip precision 14.31818 MHz oscillator. This includes buffered MPU clocks (E and Q), VDG clock, color subcarrier (3.58 MHz), row address select (RAS), column address select (CAS) and write enable (WE). Total Address Decode For most applications, the SAM plus a “1 of 8 decoder” chip completely decodes /0, ROM and RAM chip selects without wasting memory address space and without needlessly chopping-up contiguous address space. Chip selects are positioned in address space to allow three types of memory (RAM, local ROM and cartridge ROM) independent room for growth. For example, RAM may grow from address $0000-up, cartridge ROM may grow from address SFEFF- down and local ROM may grow from $BFFF-down. Alternately, if the application requires minimum ROM and maximum contiguous RAM, a second choice of two memory maps places RAM from $0000 to $FEFF. (See Figures 14-16.) In both memory maps all /O, MPU vectors, SAM control registers, and some reserved address spaces are efficiently contained between addresses $FFOO and SFFFF. How Much RAM? Using nine SAM pins (Z0-Z7 and RAS0) the following combinations require no additional address logic. FIGURE 13 — RAM CONFIGURATIONS. Address: Chip Select se isB PSLATSEIZIZD so banks of 4K x 8 (like MCM4027's) 252423222120 . 1. RASH (=z7) f- One or two banks of 4K x tke . 26282429222120 . FASO One or two banks of 16K x 8 (ike MCMA116's) 2282423222120... bese RASH (=27) ZVABISLAZIZIZVZ0 . RASB One bank of 64K x 8 (like MCM6665') or one bank of 16K x 4 (like TMS4416's) PROGRAMMING GUIDE SAM — Programmability ‘The SAM contains a 16-bit control register which allows the MC680SE to program the SAM for the following options: VDG Addressing Mode....... 3-bits VDG Address Offset 7-bits 32K Page Switch 1-bit MPU Rate... .. 2-bits Memory Size. seceees 2bits Map Type . ; ss. Tbit Note that when the SAM is reset by first applying power or by manual hardware reset,t all control register bits are cleared (to a logic “0”). VDG Addressing Mode Three bits (V2, V1, VO) control the sequence of DISPLAY ADDRESSES generated by the SAM (which are used to scan dynamic RAM for video information). For example, if you wish to display Dynamic RAM data as INTERNAL ALPHAN- UMERICS VIDEO, you should program? the MC6847 for the INTERNAL ALPHANUMERICS MODE and CLEAR BITS V2, V1 and V0 in the SAM. The table on the following page summarizes the available modes: + See Figure 7 for manual reset circuit + Typically, part of a PIA (MC6821) at location $FF22 is used to control MC8847 modes. (See MCE847 Data Sheet.) & MOTOROLA Semiconductor Products Inc. 14SN74LS783/MC6883 © SN74LS785 MC6847 Mode ‘SAM Mode. ‘Met Mode Type GA_| cmat | ome | exti_| css v2 vu vo Internal Alphanumerics o x x 0 x 0 0 0 External Alphanumerics 0 x x 1 x o o 0 ‘OSemigraphics — 4 oO x x 0 x o o oO ‘Semigraphics — 6 0 x x 1 x ° ° oO ‘Semigraphics — 8 oO x x 0 x ° 1 oO ‘Semigraphics — 12" o x x 0 x 1 0 oO ‘Semigraphics — 24* 0 x x 0 x 1 1 oO Full Graphics — 1C 1 ° 0 o x oO o 1 Full Graphics — 1R 1 ° ° 1 x o 0 1 Full Graphics — 2C 1 0 1 oO x oO 1 o Full Graphics — 2R i ° 1 1 x 0 1 1 Full Graphics — 3¢ 1 1 ° 0 x 1 0 ° Full Graphics — 3R 1 1 0 1 x 1 oO 1 Full Graphics — 6C 1 1 1 o x 1 1 0 Full Graphics — 6R 1 1 1 1 x 1 1 0 Direct Memory Accesst x x x x x 1 1 i * 88, $12, & S24 modes are not described in the MC6E47 Data Sheet. See appendix “A” + DMA s identical to 68 except as shown in Figure 5 on page 8. + The function of these control bts differs on the T1 version ofthe 6847. See the MC6847T! data sheet for details, VDG Address Offset Seven bits (F6, F5, F4, F3, F2, F1 and FO) determine the Starting Address for the video display. The “Starting Address” is defined as “‘the address corresponding to data displayed in the Upper Left corner of the TV screen.” The “Starting Address” is shown below in binary: rel rs[ rat rs[r2[r[rloloflol[oj;o[o[olo|o Kw } ost Least Significant Significant —~ an ai Note that the “Starting Address” may be placed anywhere within the 64K address space with a resolution of 1/2K (the size of one alphanumeric page). Page Switch One bit (P1) is used “in place of” A15 from the MC6809E in order to refer access within $0000-$7FFF to one of two 32K byte pages of RAM. For systems using the LS783 and 32K bytes of RAM or less, the Page bit serves no useful function and is a “don’t care.” The LS785 uses the Page bit in conjunction with the memory size bits to determine whether 16K x 1 or 16K x 4 DRAM is being accessed. P1 is set for 16K x 4 and cleared for 16K x 1. The Page bit must also be cleared for the LS785 to function with 4K x 1 DRAMSs. & MOTOROLA Semiconductor Products Inc. 15ols KCC RY LL) MPU Rate Two bits (R1, RO) control the clock rate to the MC6809E MPU. The options are: RATE (FREQUENCY OF “E” CLOCK) Ri [Ro (0.9 Miz (Crystal Frequency + 16) Slow (0.9/1.8 MHz (Address Dependent Rate) 1.8 MHz (Crystal Frequency = 8) Fast xe (Typical Crystal Frequency = 14.31818 MHz) In the “address dependent rate” mode, accesses to $0000-S7FFF and $FFO0-$FF1F are slowed to 0.9 MHz (crystal frequency + 16) and all other addresses are accessed at 1.8 MHz (crystal frequency ~ 8). Note: “‘Slow” (0.9 MHz) operation can be accomplished using 1.0 MHz MC6803E and MC6821 devices. For “Fast” (1.8 MHz) operation, 2.0 MHz MC68BO09E and MC68B21 devices must be used. Memory Size ‘Two bits (M1 and M0) determine RAM memory size. the options are: SIZE m1] Mo (One or two banks of 4K x 1 dynamic RAMs One or two banks of 16K x 1 dynamic RAMs One bank of 16K x 4 dynamic RAMs© One bank of 64K x 1 dynamic RAMS Up to 64K static RAM* ‘D This option e only available when using the LS785, * Requires a latch for demultiplexing the RAM address IMPORTANT! Note: Be sure to program the SAM for the correct memory size before using RAM (i.e., for a subroutine stack). Map Type One bit (TY) is used to select between two memory map configurations. Refer to Figures 14~16 for details. Early versions of the LS783 did not allow the “Fast” MPU rate to be used in conjunction with Map Type “TY = 1. Devices manufactured after January 1, 1983 allow both “Fast” and “Slow” MPU rates to be used with Map Type “TY = 1.” (Date of manufacture is marked on devices as YYWW where YY is the year and WW is the week of manufacture) Writing To The SAM Control Register Any bit in the control register (CR) may be set by writing to a specific unique address. Each bit has two unique addresses . .. writing to the even # address clears the bit and writing to the odd # address sets the bit. (Data on the data bus is irrelevant in this procedure.) The specific addresses are tabulated in Figures 14~16, If desired, a short routine may be written to program the SAM CR “a word at a time.” For example, the following routine copies “B” bits from “A” register to SAM CR addresses beginning with address “X.” ‘SAMI 46 ROR A 76543210 24 08 += BCC. «-SAM2 30 01 INX (LEAX1,X) A780 STA OX" 2002 BRA__SAM3 SAM2 A781 STA_OX** ‘SAM3 5A DEC B 26 «F2 BNE SAMI 39, RTS. & MOTOROLA Semiconductor Products Inc. 16FIGURE 14 — MEMORY MAP (TYPE #0) course FINE Mcesose| 2, McesosE = =—»-4_8 _, Address | Si, SoMCSB09E - Vectors, Bite’ Label Definitions SAM ‘cs ‘SFFFF Control, vo 'SFFOO Rome"* (s=3) Is Reserved + >02 P50 Oaks 55, Pega 4 oa) > > 10 SN7aLS156 3 Gap) enc 82 % 2 Opp) > 1a] ins] she From 18783 = 3 T Grp) Pene si>—Say 9 750V S0>—y4 "0 TOi2—>— I), AM READ ee & MOTOROLA Semiconductor Products Inc. 2iy EXT NL RY) APPENDIX C VDG/SAM Video Display System Offers 3 New Modes by Paul Fletcher There are three new modes created when the VDG and SAM are used together in a video display system. These modes offer alphanumeric compatibility with 8 color low-to-high resolution graphics, 64H x 64 V, 64H x 96 V, 64H x 192 V. The new modes $8, $12, and S24 are created by placing the VDG in the Alpha Internal mode and having the SAM in a 2K, 3K or 6K full color graphics mode. In all modes the VDG's S/A and Inv. pins are connected to data bits DD7 and DD6 to allow switch- ing on the fly between Alpha and Semigraphics and between inverted and non-inverted alpha. This method is used in most VDG systems to obtain maximum flex- ibility. The three modes divide the staridard 8*12 dot box used by the VDG for the standard alpha and semigraph- ics modes into eight 4*3 dot boxes for the S8 mode, twelve 4*2 dot boxes for the S12 mode, and twenty- four 4*1 dot boxes for the S24 mode. Figure 17 shows the arrangement of these boxes. One byte is needed to control two horizontally consecutive boxes. It therefore takes four bytes for the S8, six bytes for the S12, and 12 bytes for the S24 mode to control the entire 8*12 dot box. These two horizontally consecutive boxes have four combinations of luminance controlled by bits BO- 83. For convenience B2 should be made equal to 80 and B3 should be made equal to B1. This eliminates a screen placement problem which would cause other codes to change patterns when moved vertically on the screen. The illuminated boxes can be one of eight colors which are controlled by B4-B6 (see Figure 18). The bytes needed to control all the boxes in the 8*12 dot box must be spaced 32 address spaces apart in the display RAM because of the addressing scheme originally used in the VDG and duplicated by the SAM. This means to place an alphanumeric character on the TV screen it requires 4, 6, or 12 bytes depending on the mode used. These bytes are placed 32 memory locations apart in the display RAM (see Figure 18). This multiple byte for- mat allows the mixing of character rows of different characters in the same 8*12 dot box creating new char- acters and symbols. It also allows overlining and un- derlining in eight colors by switching to semigraphics at the correct time. These new modes optimize the memory versus screen density tradeoffs for RF performance on color ‘TVs. This could make them the most versatile of all the modes depending on the users creativity and the soft- ware sophistication. MOTOROLA Semiconductor Products Inc. 22CTR I Ot ELL Scan Lines. ss Scan Lines $12 Scan Lines S24 FIGURE C1 — DISLAY MODES S8, $12, S26 isible Dot Correlation }<__s—_>| eft” Right Address Byte $xx00 ($01) $xx20 (801) | 54 ig the 2 voc “Asci” '$xxao ($01) { Cod8 for ‘A’ $xX60 (S01) © Alphanumeric Compatible | oo Left Right ..4 Red | Red | $xxo0 (sar) aiue | on |Sxx20 (SAA) ont _| Green | sxxao (sas) 2 Orange | Orange | SxX60 (SFF) on | or |sxxeo (sao) Yetow | Yellow | $xxA0 (S9F) © Options: One of @ colors for Lor Ror both. Off = Black — Biua_[ Bue} sxxo0 sar) Black] Black §xx20 ($00) Black |3xxa0 (S80) ef sxxe0 (514) “Code fe] sxxeo ($18). fr Tal 1 sxxao isie) et sxxc0 (s18) ( vos aI Tel 1 sxxeo (818) » code et Tt fat tsxio0 sia) ( for x LT Het sxi20 (si) lack | Black_|8x 140 ($80) [Green] $x160 (S8F) © Underline, Overline ‘* Mix Character Dot Rows *** charactors will always romain in standard VDG positions. & MOTOROLA Semiconductor Products Inc. 23SP ZIRSY Ld SN74LS783/MC6883 800s ZaPD 1 SIP) s@xoq 10p £ x p40 mos Uy 0900s | A smoy 91 x “H48UD Ze = eUdIy syp018 8s 10 9 x 99 = 1wes sexo 10p smou 91 UoRnjosoy x Jo mos pie ue910§ AL { 40 Moy 240 s0xoq 10p € x Jo mos puz wor H ozoos ; ze svez sy0018 8s 40 ste) sexoq 10p. suWUn|OD Ze = £ x 40 mor 81 uunjoo t ost | dey A1owew 99105 8s ‘eer ewosew folilile 1 af T te =a wera [afofuls oa foo apo: eax wea fofofr]s peo fiosw ra HO | 40109 | = 0 L pew tyeyofe. oo o eudiv) x} xX] x | xX |x] x Jauilwis ena fofrfols on 7 wes [or] [zr fer [oof ia |zo] x sooo} wo | = | 1 | o mora [a fofo|s oa rr) 37 weep fofolo|+ <—'s —>| wo | uo o | o eva [x{x]x fo v og'ze | te'ea 0109, | 09 | 19} 29) x7 S7TAWWXa AVWHOS AVTESIO BS — 29 BUNDLE (p) (9) (a) 8s Semiconductor Products Inc. 24 —_——— & MOTOROLAPr ex [ett ke er} FIGURE 18 — EQUIVALENT OF OSCILLATOR INPUT AND OUTPUT Yee Oscour Voc y Vec' mw FIGURE 19 — DAO INPUT vec Veo Vec Dao. FIGURE 20 — VCik INPUT/OUTPUT Veo VCik Vee Veo Veo FIGURE 21 — E AND Q OUTPUTS Veo 9 9 Vec FIGURE 22 — TYPICAL INPUT Veo Veo FIGURE 23 — TYPICAL OUTPUT Vee: MOTOROLA Semiconductor Products Inc. 25FIGURE 24 — LOW COST me ewoe VY as at She She “he 5 as a a ano sof soft a est [x st fe ce ie n a cso [2 cso [2 fs fs : as wos esi 7 o o 20 rool ree fe fs . me wer TO mere 3 a a ae wl e as i. ol , j ook dyugee es 935 oF i wh tos ‘ono }® 27 oA0 ven Som 3 bs ives 90 7 an nia Sy yy HY SY = Neg LLessv rahe heel sels a 3) TRG AS AG AS A A A RASTAS WE fn al | + RAMs micme116B-20""* = ce [J =| aoe s] y feo al Is alos, Rol a” alos ] & cond 7} fea nl ze aoe 3] fete dg cond ale ne wa] Efe oohu lS fig ae af a i ee ef a er sn SE | aloo fg poole al, ofa Yeo vee vas cy Ta Ee ce ie ty i zs Keane ‘This pin number on 8 different RAM chips is connected to this point. “See text... page 16. ***Any RAM configuration supported by LS789 or LS786 may be used. M5847 Mode Contra & Misc LO connect hare ® MOTOROLA Semiconductor Products Inc. 7RTE ERI ORD Cedi OUTLINE DIMENSIONS N SUFFIX PLASTIC PACKAGE CASE 711-03 MILLIMETERS] um min max. Biee | 52.45 Taye | 1622 [ 0540-0860 ae soe Utss | 0-700 ‘096 058 | ooie| ooze Nor |-182 | 0.000 0060. 254 BSC asc “18s [210 | 0065 | 0.085 B.20| 038 [0.08 ors Yar 343 Poe} ons is7485C_| 0600 650 [eC ‘srl 197 Loom ooo J SUFFIX CERAMIC PACKAGE CASE 734.04 [MiLLimeTeRs| —WcHES —] MIN | MAX | WIN | MAX] wisi] 5326 | 2020 | 2095, 120 1549 | 0600 | 0610 406 | 588 036 | 0856 one zr] 165 | 0060 | 0.055 | 2s06sc_| 0.100880 0.20 [050 | 006 | 0077 316 | 406 | 0.126 {0.160 isz¢asc | O6008SC wise se | 150 asi | 127 | 0026 | ooo ‘Wotorola reserves the right fo make changes without further notice to any products herein to Improve reliability, function or design, Motorola does liability rising out ofthe application or use of any product or circuit described herein: nether does it convey any license under its or the rights [are registered trademarks of Motorola, Inc. Motorola Inc. isan Equal Employment Opportunity/ Attirmative Action Employer. others Motorola and a & MOTOROLA Semiconductor Products Inc. BOX 20012 « PHOENIX, ARIZONA 85036 # A SUBSIDIARY OF MOTOROLA INC. — 28 som