ARITHMATIC LOGICAL UNIT

(ALU)
 CHAPTER 1: INTRODUCTION

An arithmetic logic unit (ALU) is a key component of a computer’s central processor unit.
The ALU performs all arithmetic and logic operations that must be performed on instruction
words. The ALU is split into two parts in some microprocessor architectures: the AU and the LU.
In the computer system, ALU is a main component of the central processing unit, which
stands for arithmetic logic unit and performs arithmetic and logic operations. It is also known as
an integer unit (IU) that is an integrated circuit within a CPU or GPU, which is the last component
to perform calculations in the processor. It has the ability to perform all processes related to
arithmetic and logic operations such as addition, subtraction, and shifting operations, including
Boolean comparisons (XOR, OR, AND, and NOT operations). Also, binary numbers can accomplish
mathematical and bitwise operations. The arithmetic logic unit is split into AU (arithmetic unit)
and LU (logic unit). The operands and code used by the ALU tell it which operations have to
perform according to input data. When the ALU completes the processing of input, the
information is sent to the computer's memory

The calculations needed by the CPU are handled by the arithmetic logic unit (ALU); most of the
operations among them are logical in nature. If the CPU is made more powerful, which is made
on the basis of the ALU is designed. Then it creates more heat and takes more power or energy.
Therefore, it must be moderation between how complex and powerful ALU is and not be more
costly. This is the main reason the faster CPUs are more costly; hence, they take much power and
destroy more heat.
Although the ALU is a major component in the processor, the ALU's design and function may be
different in the different processors. For case, some ALUs are designed to perform only integer
calculations, and some are for floating-point operations. Some processors include a single
arithmetic logic unit to perform operations, and others may contain numerous ALUs to complete
calculations.

The operations performed by ALU are:

Logical Operations: The logical operations consist of NOR, NOT, AND, NAND, OR, XOR, and more.
Bit-Shifting Operations: It is responsible for displacement in the locations of the bits to the by
right or left by a certain number of places that are known as a multiplication operation.
Arithmetic Operations: Although it performs multiplication and division, this refers to bit
addition and subtraction. But multiplication and division operations are more costly to make. In
the place of multiplication, addition can be used as a substitute and subtraction for division.

1.1 Advantages of ALU

ALU has various advantages, which are as follows:
1. It supports parallel architecture and applications with high performance.
2. It has the ability to get the desired output simultaneously and combine integer and
floating-point variables.
3. It has the capability of performing instructions on a very large set and has a high range
of accuracy.
4. Two arithmetic operations in the same code like addition and multiplication or addition
and subtraction, or any two operands can be combined by the ALU. For case, A+B*C.
5. Through the whole program, they remain uniform, and they are spaced in a way that they
cannot interrupt part in between.
6. In general, it is very fast; hence, it provides results quickly.
7. There are no sensitivity issues and no memory wastage with ALU.
8. They are less expensive and minimize the logic gate requirements.
1.2 Disadvantages of ALU
The disadvantages of ALU are discussed below:
1. With the ALU, floating variables have more delays, and the designed controller is not easy
to understand.
2. The bugs would occur in our result if memory space were definite.
 3. It is difficult to understand amateurs as their circuit is complex; also, the concept of
pipelining is complex to understand.
4. A proven disadvantage of ALU is that there are irregularities in latencies.
5. Another demerit is rounding off, which impacts accuracy

In this project we have taken basic operations we have used 8-bit accumulator along with
8- bit auxiliary register as inputs and 8-bit output register along with the 9-bit of status register
(The size of the inputs and output are user defined). The status register has the following flag bits
in order of 4-bit overflow falg, carry flag, barrow flag, zero flag, done flag for shifter block and
done flag for code converter block. Here in general zero flag will be affected when ever the output
result of any operation is all zeros.
Zero Flag - 1- indicates the result is all zeros.
0- indicates the result is non-zero.
Status register:
Status Register Bit Position Flag
0 Code Convertion Done
1 Shifting Done
2 Zero Flag
3 Barrow Flag
4 Carry Flag
5 Over Flow 0
6 Over Flow 1
7 Over Flow 2
8 Over Flow 3
 CHAPTER 2: DESIGN BLOCKS
Our design comprises of 7 basic sections.
1. Opcode Decoder
2. Arithmetic Block
3. Logical Block
4. Comparator Block
5. Shifter Block
6. Code Conversion Block
7. Result Fetching Block
Section 2 to 6 having one dedicated output register each for output as well as for status. At
any point of time, although multiple operations may be issued to the ALU in parallel,
simultaneously only those operations may execute that run on independent block sections of the
ALU. Thus, on the basis of the issued operation, the respective output is fetched from the sectional
output register and delivered to the final 8bit result register. It is recomended to reset all the
registers before starting of any operations.

2.1 Opcode Decoder:

The proposed design consists of a primary opcode decoder unit which activates the
respective function block on the basis of the instruction opcode executed by the processor and
forwarded to the ALU block. All the circuits are active low enabled and system can go to initial
condition by active low control input 'init' at any time. The respective active low output lines will
feed the enable lines of respective function blocks. The decoder is a 4:16 unit i.e. it takes 4 bits
opcode as input and in turn activates the respective function block to perform the desired
operation. Using a case implementation statement, we can select and activate the respective
function block for the required operation.
The opcodes for the various operations is as follows:

S. No. Operations Opcode

1. Adder 0001

2. Subtractor 0010

3. Multiplier 0011

4. Divider 0100
 5. AND 0101

6. OR 0110

7. NOT 0111

8. NANAD 1000

9. NOR 1001

10. XOR 1010

11. Refresh 1011

12. 8 bit Comparator 1100

13. Shifter 1101

14. Code Conversion 1110

15. Status 1111

We have left the 0000 case for future operations.

2.2 Arithmetic Block:

This block is used to implement arithmetic operations such as Addition, Subtraction,
Multiplication and division. The Accumulator and the auxiliary B register feed as inputs to this
block. The outputs of results and respective flags are stored in respective output registers.
The block diagram of arithmatic block is as follows:
 2.2.1 Adder:
This is the basic addition of two – 8 bit numbers. The output is 8 bit of sum and carry bit
in flag register.
Eg: 1st input (8-bit)= 1111 1111
2nd input (8-bit)= 1111 1111
The sum of above two numbers is = 1 1111 1110: here msb bit is carry bit and
remaining 8 bits are sum output. After the addtion operation the status register [4] bit – carry
flag will be affected.
Carry Flag - 1- indicates there is a carry occured after the addition.
0- indicates there is no carry.
Eg2: accumulator=11001011(203), auxilary_register=10101010(170), sum=01110101(117),
status register =000010000( 16)

2.2.2 Subtractor:
Here the substraction between two 8-bit numbers will be performed. The result difference
is of 8-bit length along with the barrow (ba) flag bit. After the substraction operation the status
register [3] bit – barrow flag will be affected. Barrow flag 1- indicates there is a barrow while
substratcion operation and 0- indicates there is no barrow.
Eg: 1st input (8-bit) A= 0111 1111
2nd input (8-bit) B= 1111 1111
 The difference between the above two numbers is A-B=1000 0000 and Barrow is
1.
Eg2: accumulator=11001011(203), auxilary_register=10101010(170), opcode=0010(2), output
=00100001( 33), status register=000000000( 0)
2.2.3 Multiplier:
Here the multiplication of two 4-bit numbers will be performed. The result is of 8-bit width.
If width of the product is more than 8- bits (if the width of multiplier & multiplicant is more than
4-bit), the lsb 8- bits of product will be stored in the output register and Overflow 3 bit of- (MSB
of status register) status register will be active high, which represents that the multiplication
product is having more than 8-bit length.
Eg: accumulator=11001011(203), auxilary_register=10101010(170), output
=11001110(206), status register=100000000(256) , here status msb bit indicates that the
product is more than 8- bit width.

Output register Bit Position Bit position

0 Product 0-bit (LSB)
1 Product 1-bit
2 Product 2-bit
3 Product 3-bit
4 Product 4-bit
5 Product 5-bit
6 Product 6-bit
7 Product 7-bit

Status Register Bit Position Flag indication

0 Code Convertion Done

1 Shifting Done

2 Zero Flag

3 Barrow Flag

4 Carry Flag

5 Over Flow 0

6 Over Flow 1

7 Over Flow 2
Multiplication product is having more width than
output register and the LSB 8-bits of product are in
8 output register.
 2.2.4 Divider:
The division operation takes the input of two 8-bit numbers as divisor & divident and
results the 8-bit quotient of integer type only. As we are dealing with the integer type only. It is
recomended to use integer type data only. In this regard, we have not taken any flag bits to change
except the Zero flag, when the division operation is performed and the quotient is 0 then the zero
flag will be set to 1 otherwise set to 0. The result is taken floor value of quotient.
Eg: accumulator=11001011(203), auxilary_register=10101010(170),
output=00000001( 1), status register=000000000(0)

2.3 Logical block:

This block comprises of basic logic gate units such as AND, OR, NOT, XOR, etc. Such bit-
wise operations on data o12perands are served by this block. Outputs are stored in respective
latches. The entire logical block comprises of one dedicated output register. Based on the opcode
the respective output will be delivered to the final output.
The block diagram of logical block is as follows:

2.3.1 AND operation:

 The bitwise AND operation will be performed between two 8- bit operands and the result
is 8-bit output register and the flag bit – zero flag (status register[2] bit) will be affected by this
operation.
Eg: The bitwise AND operation between (1111 0101) & (0000 1101) results – output y=
0000 0101 and status register=000000000.
Zero Flag=1 – the result consists of all zeros
Zero Flag=0 – the result is non-zero

2.3.2 OR operation:
The bitwise OR operation will be performed between two 8- bit operands and the result
is 8-bit output register and the flag bit – zero flag (status register[2] bit) will be affected by this
operation.
Eg: The bitwise OR operation between (1111 0101) & (0000 1101) results – output
y=1111 1101 and status register=000000000.
Zero Flag=1 – the result consists of all zeros
Zero Flag=0 – the result is non-zero

2.3.3 NOT operation:

The bitwise NOT operation will be performed on 8- bit accumulator and the result is 8-bit
output register and the flag bit – zero flag (status register[2] bit) will be affected by this operation.
Eg: The bitwise NOT operation of (1111 0101) results – output y= 0000 1010 and status
register=000000000.
Zero Flag=1 – the result consists of all zeros
Zero Flag=0 – the result is non-zero
2.3.4 NAND operation:
The bitwise NAND operation will be performed between two 8- bit operands and the result
is 8-bit output register and the flag bit – zero flag (status register[2] bit) will be affected by this
operation.
Eg: The bitwise NAND operation between (1111 0101) & (0000 1101) results – output y=
1111 1010 and status register=000000000.
Zero Flag=1 – the result consists of all zeros
Zero Flag=0 – the result is non-zero
2.3.5 NOR operation:
 The bitwise NOR operation will be performed between two 8- bit operands and the result
is 8-bit output register and the flag bit – zero flag (status register[2] bit) will be affected by this
operation.
Eg: The bitwise NOR operation between (1111 0101) & (0000 1101) results – output y=
0000 0010 and status register=000000000.
Zero Flag=1 – the result consists of all zeros
Zero Flag=0 – the result is non-zero
2.3.6 XOR operation:
The bitwise XOR operation will be performed between two 8- bit operands and the result
is 8-bit output register and the flag bit – zero flag (status register[2] bit) will be affected by this
operation.
Eg: The bitwise XOR operation between (1111 0101) & (0000 1101) results – output y=
1111 1000 and status register=000000000.
Zero Flag=1 – the result consists of all zeros
Zero Flag=0 – the result is non-zero
2.4 Comparator Block:
This block consists of combinational circuit HDL code which performs bit matching and
comparisons. Respective outputs may be used to branch instructions on basis of a comparison.
Similarly, numerically larger or smaller indications on respective operands may be used. In case
of equal comparison match, the accumulator as well as the carry bit is set to zero, and the
respective Zero flag is set.
In case if the operand in the accumulator is larger, the MSB of the result 8 bit is set, and so 8’h80
is resulted on the output. Otherwise 8’h01 resulted on the output.
The block diagram of comparator block is as follows:
Eg1: Equality Case: accumulator=11001011(203), auxilary_register=11001011(203), output
=00000000( 0), status register=000001000( 8) (zero flag is set)
Eg2: A<B case: accumulator=11001011(203), auxilary_register=11111111(255),
output=00000001( 1), status register=000000000( 0)
Eg2: A>B case: accumulator=11001011(203), auxilary_register=10100011(163), output
=10000000(128), status register=000000000( 0)
2.5 Shifter/Rotate block:
This block consists of basic shifters and mechanisms for bit rotation. Provisions for
updates in respective flag bits after each operation may be provided in future improved versions.
In case of these operations, as they accept only one 8-bit operand, thus the type of rotation and
the type of shifting/rotation command may be specified explicitly by means of the b-register bus
mapped to the onboard DIP switches. The higher 4 bits of the b-register bus i.e. 7:4 bits specify
the number by which the bits have to rotate as per the command in a bitwise fashion. The lower
4 bits of the b register bus i.e. 3:0 bits specify the particular command which is to be executed for
the respective shifter section.
The reference for shift/rotate selection is as follows:
Shifting/Rotating operation Opcode (B[3:0))
Shift right through carry 0000
shift left through carry 0001
Rotate right 001x: (any of 0010 & 0011)
01xx: (any one of 0100,
Rotate left 0101,0110,0111)
 Shift left through carry: opcode B[3:0]=0001 for this operation. In this operation the
accumulator data will be shifted left and the lsb bit will be padded by the carry flag bit. If carry
bit=1 , 1’s will be padded and if carry bit=0, 0’s will be padded.
Shift rotate through carry: opcode B[3:0]=0000 for this operation. In this operation the
accumulator data will be shifted right and the lsb bit will be padded by the carry flag bit. If carry
bit=1 , 1’s will be padded and if carry bit=0, 0’s will be padded.
Rotate right: opcode B[3:0]=001X: (any of 0010 & 0011) for this operation. In this
operation the accumulator data will be rotated right. The lsb bit will be transfered to the msb bit
position and then shifted right.
Rotate left: opcode B[3:0]=01XX: (any one of 0100, 0101,0110,0111) for this operation. In
this operation the accumulator data will be rotated left. The msb bit will be transfered to the lsb
bit position and then shifted left.
Other than the above opcodes for remaining opcodes when (B[3]=1) the output taken as
0’s and we can use these for other operations in future as enhancement.
In all the operations the flag bit – shifting done (Status register [1]-bit) and Zero flag will be
affected.
If shifting done=1: the shifting/rotation operation is performed and finished.
If shifting done=0: the shifting/rotation operation is not performed.
If Zero flag=1: the output after the shifting/rotation operation is all 0’s.
If Zero flag=0: the output is non-zero.
Eg1: Shift right through carry: accumulator=11001011(203), auxilary_register=01010000( 80),
carryflag=0, output=00000110( 6), status register=000000010( 2).
Eg2: shift left through carry: accumulator=11001011(203), auxilary_register=01010001( 81),
output=01100000( 96), status register=000000010( 2).
Eg3: Rotate right: accumulator=11001011(203), auxilary_register=01010010( 82),
output=01011110( 94), status register=000000010( 2)
Eg4: Rotate left: accumulator=11001011(203), auxilary_register=01010100( 84),
output=01111001(121), status register=000000010( 2).
The block diagram of shifter block is as follows:

2.6 Code Conversion:

This block consists of basic 4 bit-binary code conversions with flag bit 'Done' indicator.
The LSB [3:0] from the b-register provide the type of code conversion. As the specifications has
not given specific location of the data to be converted consider the MSB [7:4] from the b-register
provide the 4-bit data to be converted.This block has the option to select the 8-bit value either
from the external switches or the shift result but only one at a time based on the shifting done
flag of final status register.
If Shifting done flag bit=1 the shift result will be selected as input and if the flag is 0 then
the input will be taken from external switches.
The reference for code selection is as follows:
Convertion Opcode
Bin to Gray 0001
Bin to xs-3 0010
Bin to xs-5 0011
 Bin to BCD 0100
Other than above opcodes remaining opcodes may be used for future operations and in
this project for the remaining opcodes no operation is taken (output is all zeros). After enabling
the 'Done' signal, the result is stored in register and forwarded to the final output. Here the flag
bit Code Convertion Done (status register[0]- bit) and zero flag will be affected.
If Code Convertion Done=1: the Code convertion operation is performed and finished.
If Code Convertion Done=1: the Code convertion operation is not performed.
If Zero flag=1: the output after the code convertion is all 0’s.
If Zero flag=0: the output is non-zero.
Eg1: binary – xs3 conversion: accumulator=11001011(203), auxilary_register=10100010(162),
output=01000011( 67), status register =000000001( 1) : here input is taken from
auxilary_register.
Eg2: binary- xs3 conversion: accumulator=11001011(203), auxilary_register=10100001(161),
Shifter Output =00000010( 2), Code converter output =00110011( 51), status
register=000000011( 3) : here input is taken from output of shifter block.
Eg3: Binary- xs5 conversion: accumulator=11001011(203), auxilary_register=10100011(163),
output=01100101(101), status register=000000001( 1)
Eg4: Binary-BCD conversion: accumulator=11001011(203), auxilary_register=10100100(164),
output=00010000( 16), status register=000000001( 1).
Eg5: binary-Gray code conversion: accumulator=11001011(203),
auxilary_register=10100001(161), output=00001111( 15), status register=000000001( 1)
The block diagram of code converter is as follows:

2.7 Result Fetching Block:

In this block we take the outputs of all the above sections and farword them to the output based
on the opcode, status signal (decoder output for opcode-1111) and init signal.
2.7.1 Miscellaneous Signals:
init: This signal is used to enable the opcode decoder and reset the final output & final status
registers only.
Refresh (opcode- 1011): This signal is used to reset all the output registers and status registers
of all blocks.
Status (opcode-1111): This signal is used for recover the previous values of final output &
final status registers, whenever the outputs are resetted by using init. If refresh signal is used
there is no possibility for recovery.
Eg: let us consider the operations in order as follows:
“codeconversion -->init signal(activelow) --> init signal(active high) & status signal --> adder
operation --> init signal(active low)--> init (active high )& status signal”

the output is as follows:

1) code conversion: accumulator=11001011(203), auxilary_register=10100100(164),
opcode=1110(14), init=1, output=00010000( 16), status register=000000001( 1): code
conversion output
2) init signal(activelow): accumulator=11001011(203), auxilary_register=10100100(164),
opcode=1111(15), init=0, output=00000000( 0), status register=000000000: here both output
& status registers will be initialized to 0’s.
3) init signal(active high) & status signal: accumulator=11001011(203),
auxilary_register=10100100(164), opcode=1111(15), init=1, output=00010000( 16), status
register=000000001( 1): here previously obtained code conversion result will be forwarded to
output.
4) adder operation: accumulator=11001011(203), auxilary_register=10101010(170),
opcode=0001( 1), init=1, output=01110101(117), status register=000010001( 17): adder
operation is performed.
5) init signal(activelow): accumulator=11001011(203), auxilary_register=10101010(170),
opcode=0001( 1), init=0, output=00000000( 0), status register=000000000( 0): here both
output and status registers will be initialized to 0’s.
6) init (active high )& status signal: accumulator=11001011(203),
auxilary_register=10101010(170), opcode=1111(15), init=1, output=01110101(117), status
register=000010001( 17): here previously obtained adder result will be forwarded to output.

CHAPTER 3
BLOCK DIAGRAM
The all blocks are integrated and the whole block diagram is as follows:
 CHAPTER 4: CONCLUSIONS & ENHANCEMENTS

The ALU is designed based on the specifications given. By using this ALU we can
perform arithmatic operations like addition, substration, multiplication, division,with data size
of 8-bit, logical operations of bitwise-AND, bitwise-OR, bitwise-NOT, bitwise-NAND, bitwise-
NOR & bitwise-XOR operations, comparision of two 8- bit numbers, shifting/rotation
operations, converting the 4-bit binary number into Gray code, XS-3 code,XS-5 code,BCD code.
This ALU has some limitations. This ALU will give only integer type values when
division operation is performed. This design has flexibility that the bit size can be increased as
per the user perception. In this design the input registers and output registers are of same bit
width and for status register has one bit extra as compared to the remaining input & output
registers.
This design may be enhansed to perform floating point operations (division) with
considerable changes. As we have taken status bit to recover the previous value, it has got
protection from unexpected reset due to init signal. But limitation is that only previously
performed operation output is recovered. All the operations are combinational in nature. We may
introduce sequential elements like memories to enhance the speed of operation, size of the data
processed. The opcodes other than specified in code conversion block and shifter block may be
used for future specific operations.

REFERENCE:
EDA LINK: https://edaplayground.com/x/LcSQ