RISC, CISC, and ISA Variations

CS 3410
Computer System Organization & Programming

These slides are the product of many rounds of teaching CS 3410 by Professors Weatherspoon, Bala, Bracy, and Sirer.
iClicker Question (first alone, then pairs)
Which is not considered part of the ISA?

A. There is a control delay slot.

B. The number of inputs each instruction
can have.
C. Load-use stalls will not be detected by
the processor.
D. The number of cycles it takes to execute
a multiply.
E. Each instruction is encoded in 32 bits.
2
Big Picture: Where are we now?
compute
jump/branch
targets

A
memory register

D
alu
file

B
+4
addr
inst

PC control din dout

M
B
memory
imm

extend
new
forward
pc unit
detect
hazard Write
ctrl

ctrl

ctrl
Fetch Decode Execute Memory Back
IF/ID ID/EX EX/MEM MEM/WB 3
Big Picture: Where are we going?
C int x = 10;
compiler x = x + 15;

MIPS addi r5, r0, 10 r0 = 0

assembly addi r5, r5, 15 r5 = r0 + 10
assembler r5 = r15 + 15
addi r0 r5 10
machine 00100000000001010000000000001010
code 00100000101001010000000000001111
loader
CPU

32 RF 32
Circuits

Gates A
B
Transistors

Silicon 4
Big Picture: Where are we going?
C int x = 10;
compiler x = 2 * x + 15;
High Level
addi r5, r0, 10 Languages
MIPS
muli r5, r5, 2
assembly addi r5, r5, 15
assembler
00100000000001010000000000001010
machine 00000000000001010010100001000000
code 00100000101001010000000000001111
loader Instruction Set
CPU Architecture (ISA)

Circuits

Gates

Transistors

Silicon 5
Goals for Today
Instruction Set Architectures
• ISA Variations, and CISC vs RISC
• Peek inside some other ISAs:
• X86
• ARM

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Instruction Set Architecture (ISA)
Different CPU architectures specify different instructions

Two classes of ISAs

• Reduced Instruction Set Computers (RISC)
IBM Power PC, Sun Sparc, MIPS, Alpha
• Complex Instruction Set Computers (CISC)
Intel x86, PDP-11, VAX

• Another ISA classification: Load/Store Architecture

• Data must be in registers to be operated on
For example: array[x] = array[y] + array[z]
1 add ? OR 2 loads, an add, and a store ?
• Keeps HW simple à many RISC ISAs are load/store

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iClicker Question
What does it mean for an architecture to be called a
load/store architecture?

(A) Load and Store instructions are supported by the ISA.

(B) Load and Store instructions can also perform
arithmetic instructions on data in memory.
(C) Loads & Stores are the primary means of reading and
writing data in the ISA.
(D) Data must first be loaded into a register before it can be
operated on.
(E) Every load must have an accompanying store at some
later point in the program.

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ISA Variations
ISA defines the permissible instructions
• MIPS: load/store, arithmetic, control flow, …
• ARMv7: similar to MIPS, but more shift,
memory, & conditional ops
• ARMv8 (64-bit): even closer to MIPS, no
conditional ops
• VAX: arithmetic on memory or registers,
strings, polynomial evaluation, stacks/queues,
…
• Cray: vector operations, …
• x86: a little of everything
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Brief Historical Perspective on ISAs
Accumulators
• Early computers had one register!

Intel 8008 in 1972

EDSAC (Electronic Delay Storage

Automatic Calculator) in 1949

• Two registers short of a MIPS instruction!

• Requires memory-based addressing mode
- Example: add 200 // ACC = ACC + Mem[200] 10
Brief Historical Perspective on ISAs
Next step: More Registers
• Dedicated registers
- separate accumulators for mult/div instructions
• General-purpose registers
- Registers can be used for any purpose
- MIPS, ARM, x86
• Register-memory architectures
- One operand may be in memory (e.g. accumulators)
- x86 (i.e. 80386 processors)
• Register-register architectures (aka load-store)
- All operands must be in registers
- MIPS, ARM
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ISAs are a product of current technology
Machine # General Purpose Registers Architectural Style Year
• # of available registers plays huge role in
EDSAC
IBM 701
1
1
Accumulator
Accumulator
1949
1953

ISA design
CDC 6600
IBM 360
8
18
Load-Store
Register-Memory
1963
1964
DEC PDP-8 1 Accumulator 1965
DEC PDP-11 8 Register-Memory 1970
Intel 8008 1 Accumulator 1972
Motorola 6800 2 Accumulator 1974
DEC VAX 16 Register-Memory, Memory-Memory 1977
Intel 8086 1 Extended Accumulator 1978
Motorola 6800 16 Register-Memory 1980
Intel 80386 8 Register-Memory 1985
ARM 16 Load-Store 1985
MIPS 32 Load-Store 1985
HP PA-RISC 32 Load-Store 1986
SPARC 32 Load-Store 1987
PowerPC 32 Load-Store 1992
DEC Alpha 32 Load-Store 1992
HP/Intel IA-64 128 Load-Store 2001
AMD64 (EMT64) 16 Register-Memory 2003 12
In the Beginning…
People programmed in assembly and machine code!
• Needed as many addressing modes as possible
• Memory was (and still is) slow

CPUs had relatively few registers

• Register’s were more “expensive” than external mem
• Large number of registers requires many bits to index

Memories were small

• Encouraged highly encoded microcodes as instructions
• Variable length instructions, load/store, conditions, etc

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Reduced Instruction Set Computer (RISC)
John Cock
• IBM 801, 1980 (started in 1975)
• Name 801 came from the bldg that housed the
project
• Idea: Can make a very small and very fast core
• Known as “the father of RISC Architecture”
• Turing Award and National Medal of Science

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Reduced Instruction Set Computer (RISC)
Dave Patterson John L. Hennessy
• RISC Project, 1982 • MIPS, 1981
• UC Berkeley • Stanford
• RISC-I: ½ transistors & • Simple, full pipeline
3x faster
• Influences: Sun SPARC, • Influences: MIPS
namesake of industry computer system,
PlayStation, Nintendo

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RISC vs. CISC
MIPS = Reduced Instruction Set Computer (RlSC)
• ≈ 200 instructions, 32 bits each, 3 formats
• all operands in registers
- almost all are 32 bits each
• ≈ 1 addressing mode: Mem[reg + imm]
x86 = Complex Instruction Set Computer (ClSC)
• > 1000 insns, 1-15 bytes each (dozens of add insns)
• operands in dedicated registers, general purpose
registers, memory, on stack, …
- can be 1, 2, 4, 8 bytes, signed or unsigned
• 10s of addressing modes
- e.g. Mem[segment + reg + reg*scale + offset]
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The RISC Tenets
RISC CISC
• Single-cycle execution • many multicycle operations
• Hardwired control • microcoded multi-cycle
operations
• Load/store architecture • register-mem and mem-mem
• Few memory addressing • many modes
modes
• Fixed-length insn format • many formats and lengths

• Reliance on compiler • hand assemble to get good

optimizations performance
• Many registers (compilers • few registers
are better at using them)

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RISC vs CISC
RISC Philosophy CISC Rebuttal
Regularity & simplicity Compilers can be smart
Leaner means faster Transistors are plentiful
Optimize common case
Legacy is important
Code size counts
Micro-code!
“RISC Inside”
Energy efficiency
Embedded Systems
Phones/Tablets Desktops/Servers
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iClicker Question (alone first, then pairs)
What is one advantage of a CISC ISA?

A. It naturally supports a faster clock.

B. Instructions are easier to decode.
C. The static footprint of the code will be
smaller.
D. The code is easier for a compiler to
optimize.
E. You have a lot of registers to use.
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MIPS instruction formats
All MIPS instructions are 32 bits long, 3 formats

R-type op rs rt rd shamt func

6 bits 5 bits 5 bits 5 bits 5 bits 6 bits

I-type op rs rt immediate
6 bits 5 bits 5 bits 16 bits

op immediate (target address)

J-type 6 bits 26 bits
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ARMv7 instruction formats
All ARMv7 instructions are 32 bits long, 3 formats

R-type opx op rs rd opx rt

4 bits 8 bits 4 bits 4 bits 8 bits 4 bits

I-type opx op rs rd immediate

4 bits 8 bits 4 4 bits 12 bits
bits

opx op immediate (target address)

J-type 4 bits 4 bits 24 bits
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MIPS Control Dependence
while(i != j) {
if (i > j) In MIPS, performance suffers
i -= j; if code has a lot of branches
else
j -= i;
}
Loop: BEQ Ri, Rj, End // if "NE" (not equal), stay in loop
SLT Rd, Rj, Ri // (i > j) à Rd=1, (i ≤ j) à Rd = 0
BEQ Rd, R0, Else // Rd == 0 means (i ≤ j) à Else
SUB Ri, Ri, Rj // i = i-j;
J Loop
Else: SUB Rj, Rj, Ri // j = j-i;
J Loop
End: 3 NOP injections
due to delay slot
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ARMv7 Conditional Instructions
while(i != j) { ARM: avoids delays with
if (i > j) conditional instructions
i -= j;
else New: 1-bit condition
= ≠< >
j -= i; registers (CR)
}
Loop: CMP Ri, Rj // set condition registers
// Example: 4, 3 à CR = 0101
// 5,5 à CR = 1000
SUBGT Ri, Ri, Rj // i = i-j only if CR & 0001 != 0
SUBLE Rj, Rj, Ri // j = j-i only if CR & 1010 != 0000
BNE loop // if "NE" (not equal), then loop

Control Independence! 23
ARMv7: Other Cool operations
Shift one register (e.g., Rc) any amount
Add to another register (e.g., Rb)
Store result in a different register (e.g. Ra)

ADD Ra, Rb, Rc LSL #4

Ra = Rb + Rc << 4
Ra = Rb + Rc x 16

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ARMv7 Instruction Set Architecture
ARMv7 instructions are 32 bits long, 3 formats
Reduced Instruction Set Computer (RISC) properties
• Only Load/Store instructions access memory
• Instructions operate on operands in processor registers
• 16 registers

Complex Instruction Set Computer (CISC) properties

• Autoincrement, autodecrement, PC-relative addressing
• Conditional execution
• Multiple words can be accessed from memory with a
single instruction (SIMD: single instr multiple data)

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ARMv8 (64-bit) Instruction Set Architecture
ARMv8 instructions are 64 bits long, 3 formats
Reduced Instruction Set Computer (RISC) properties
• Only Load/Store instructions access memory
• Instructions operate on operands in processor registers
• 32 registers and r0 is always 0

Complex Instruction Set Computer (CISC) properties

• Conditional execution
• Multiple words can be accessed from memory with a
single instruction (SIMD: single instr multiple data)

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ISA Takeaways
The number of available registers greatly influenced the
instruction set architecture (ISA)

Complex Instruction Set Computers were very complex

+ Small # of insns necessary to fit program into memory.
- greatly increased the complexity of the ISA as well.

Back in the day… CISC was necessary because everybody

programmed in assembly and machine code! Today, CISC
ISA’s are still dominant due to the prevalence of x86 ISA
processors. However, RISC ISA’s today such as ARM have an
ever increasing market share (of our everyday life!).
ARM borrows a bit from both RISC and CISC.
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