OPA452

O PA
452 OPA
4 52
OPA
452 OPA453

SBOS127C – JULY 2000 – REVISED NOVEMBER 2003

80V, 50mA
OPERATIONAL AMPLIFIERS

FEATURES DESCRIPTION
● WIDE POWER-SUPPLY RANGE: The OPA452 and OPA453 are low-cost operational amplifi-
±10V to ±40V ers with high-voltage (80V) and high-current capabilities
● HIGH OUTPUT LOAD DRIVE: (50mA). The OPA452 is unity-gain stable and has a gain
50mA Continuous bandwidth product of 1.8MHz, whereas the OPA453 is opti-
mized for gains greater than 5 and has a 7.5MHz bandwidth.
● WIDE OUTPUT VOLTAGE SWING: 1V to Rail
The OPA452 and OPA453 are internally protected against
● FULLY PROTECTED:
over-temperature conditions and current overloads. Power
Thermal Shutdown
supplies in the range of ±10V to ±40V can be used. Unlike
Output Current-Limited
most other power op amps, the OPA452 and OPA453 have
● WIDE OPERATING TEMPERATURE RANGE: ensured specifications over the entire power-supply range.
–40°C TO +125°C
These laser-trimmed, monolithic integrated circuits provide
● PACKAGE OPTIONS: excellent low-level accuracy along with wide output swing.
TO220-7 Special design considerations assure that the product is
DDPACK-7 Surface-Mount easy to use and free from phase inversion problems often
found in other amplifiers.
APPLICATIONS The OPA452 and OPA453 are available in TO220-7 and
DDPAK-7 options. They are specified for a junction tempera-
● PIEZOELECTRIC CELLS
ture range of –40°C to +125°C.
● TEST EQUIPMENT
● AUDIO AMPLIFIERS
● TRANSDUCER DRIVERS
● SERVO DRIVERS

7-Lead 7-Lead 7-Lead

Straight-Formed Stagger-Formed DDPAK (FA)
TO-220 (TA) TO-220 (TA-1) Surface-Mount

1 2 3 4 5 6 7 1 2 3 4 5 6 7 1 2 3 4 5 6 7

VIN+ NC V+ Flag
VIN– V– VO

VIN+ NC V+ Flag VIN+ NC V+ Flag

VIN– V– VO VIN– V– VO

NOTE: Tabs are electrically connected to V– supply.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Copyright © 2000-2003, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

www.ti.com
ABSOLUTE MAXIMUM RATINGS(1) ELECTROSTATIC
Supply Voltage, V+ to V– ................................................................... 80V
Signal Input Terminals, Voltage(2) .................. (V–) – 0.5V to (V+) + 0.5V
DISCHARGE SENSITIVITY
Current(2) ...................................................... 5mA This integrated circuit can be damaged by ESD. Texas Instru-
Output Short-Circuit ................................................................. Continuous
Operating Temperature .................................................. –55°C to +125°C ments recommends that all integrated circuits be handled with
Storage Temperature ..................................................... –65°C to +150°C appropriate precautions. Failure to observe proper handling
Junction Temperature .................................................................... +150°C and installation procedures can cause damage.
Lead Temperature (soldering 10s, TO-220) ................................... 300°C
(soldering 3s, DDPAK) ..................................... 240°C ESD damage can range from subtle performance degrada-
NOTES: (1) Stresses above these ratings may cause permanent damage.
tion to complete device failure. Precision integrated circuits
Exposure to absolute maximum conditions for extended periods may degrade may be more susceptible to damage because very small
device reliability. (2) Input terminals are diode-clamped to the power-supply parametric changes could cause the device not to meet its
rails. Input signals that can swing more than 0.5V beyond the supply rails
should be current limited to 5mA or less.
published specifications.

PACKAGE/ORDERING INFORMATION
For the most current package and ordering information, see the
Package Option Addendum located at the end of this data
sheet.

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ELECTRICAL CHARACTERISTICS: OPA452; VS = ±10V to ±40V
Boldface limits apply over the specified junction temperature range, TJ = –40°C to +125°C.
At TJ = +25°C, RL = 3.8kΩ connected to ground, and VOUT = 0V, unless otherwise noted.

OPA452TA, FA
PARAMETER CONDITION MIN TYP MAX UNITS

OFFSET VOLTAGE
Input Offset Voltage VOS VS = ±40V, VCM = 0V, IO = 0V ±1 ±3 mV
over Temperature ±6 mV
Drift dVOS/dT ±5 µV/°C
vs Power Supply PSRR VS = ±10V to ±40V, VCM = 0V 5 30 µV/V
over Temperature 45 µV/V
INPUT BIAS CURRENT(1)
Input Bias Current IB VS = ±40V, VCM = 0V ±7 ±100 pA
Input Offset Current IOS VS = ±40V, VCM = 0V ±1 ±100 pA
NOISE
Input Voltage Noise Density en f = 1kHz 21 nV/ √Hz
Current Noise Density in f = 1kHz 9 fA/ √Hz
INPUT VOLTAGE RANGE
Common-Mode Voltage Range VCM (V–) + 5 (V+) – 0.5 V
Common-Mode Rejection Ratio CMRR VS = ±40V, –35V < VCM < 39.5V 86 94 dB
over Temperature VS = ±40V, –35V < VCM < 39.5V 76 dB
INPUT IMPEDANCE
Differential 1013 || 2 Ω || pF
Common-Mode VS = ±40V, –35V < VCM < 39.5V 1013 || 6 Ω || pF
OPEN-LOOP GAIN
Open-Loop Voltage Gain AOL IO = 10mA, –VS + 2V < VO < +VS – 2V 105 110 dB
over Temperature IO = 10mA, –VS + 2V < VO < +VS – 2V 107 dB
IO = 50mA, –VS + 4V < VO < +VS – 4V 96 110 dB
over Temperature IO = 50mA, –VS + 5V < VO < +VS – 5.5V 105 dB
FREQUENCY RESPONSE
Gain-Bandwidth Product GBW VS = ±40V 1.8 MHz
Slew Rate SR VS = ±40V +7.2 /–10 V/µs
Settling Time: 0.1% VS = ±40V, G = +1, 10V Step, CL = 100pF 2 µs
0.01% VS = ±40V, G = +1, 10V Step, CL = 100pF 5 µs
Overload Recovery Time VIN • Gain = VS 1 µs
Total Harmonic Distortion + Noise THD+N VS = ±40V, VO = 30Vp-p, G = 5 0.0008 %
f = 1kHz, RL = 2kΩ
OUTPUT
Voltage Output VOUT IO = 50mA (V–) + 4.0 (V+) – 4 V
over Temperature IO = 50mA (V–) + 5 (V+) – 5.5 V
Voltage Output IO = 10mA (V–) + 2 (V+) – 2 V
over Temperature IO = 10mA (V–) + 2 (V+) – 2 V
Output Current ±50 mA
Short-Circuit Current ISC ±125 mA
Capacitive Load Drive CLOAD See Typical Characteristic
SHUTDOWN FLAG
Thermal Shutdown Status Output
Normal Operation VS = ±40V 0.1 1.0 µA
Thermally Shutdown VS = ±40V 100 140 165 µA
Junction Temperature
Shutdown +160 °C
Reset from Shutdown +145 °C
POWER SUPPLY
Supply Voltage Range VS ±10 ±40 V
Quiescent Current (per amplifier) IQ IO = 0 ±5.5 ±6.5 mA
over Temperature ±7.5 mA
TEMPERATURE RANGE
Specified Range (junction) TJ –40 +125 °C
Operating Range (junction) TJ –55 +125 °C
Storage Range (ambient) TA –65 +150 °C
Thermal Resistance θJC
TO200-7 3 °C/W
DDPAK-7 3 °C/W

NOTE: (1) All tests are high-speed tested at +25°C ambient temperature. Effective junction temperature is +25°C, unless otherwise noted.

OPA452, 453 3
SBOS127C www.ti.com
ELECTRICAL CHARACTERISTICS: OPA453; VS = ±10V to ±40V
Boldface limits apply over the specified junction temperature range, TJ = –40°C to +125°C.
At TJ = +25°C, RL = 3.8kΩ connected to ground, and VOUT = 0V, unless otherwise noted.

OPA453TA, FA
PARAMETER CONDITION MIN TYP MAX UNITS

OFFSET VOLTAGE
Input Offset Voltage VOS VS = ±40V, VCM = 0V, IO = 0V ±1 ±3 mV
over Temperature ±6 mV
Drift dVOS/dT ±5 µV/°C
vs Power Supply PSRR VS = ±10V to ±40V, VCM = 0V 5 30 µV/V
over Temperature 45 µV/V
INPUT BIAS CURRENT(1)
Input Bias Current IB VS = ±40V, VCM = 0V ±7 ±100 pA
Input Offset Current IOS VS = ±40V, VCM = 0V ±1 ±100 pA
NOISE
Input Voltage Noise Density en f = 1kHz 21 nV/ √Hz
Current Noise Density in f = 1kHz 9 fA/ √Hz
INPUT VOLTAGE RANGE
Common-Mode Voltage Range VCM (V–) + 5 (V+) – 0.5 V
Common-Mode Rejection Ratio CMRR VS = ±40V, –35V < VCM < 39.5V 86 94 dB
over Temperature VS = ±40V, –35V < VCM < 39.5V 76 dB
INPUT IMPEDANCE
Differential 1013 || 2 Ω || pF
Common-Mode VS = ±40V, –35V < VCM < 39.5V 1013 || 6 Ω || pF
OPEN-LOOP GAIN
Open-Loop Voltage Gain AOL IO = 10mA, –VS + 2V < VO < +VS – 2V 105 110 dB
over Temperature IO = 10mA, –VS + 2V < VO < +VS – 2V 107 dB
IO = 50mA, –VS + 4V < VO < +VS – 4V 96 110 dB
over Temperature IO = 50mA, –VS + 5V < VO < +VS – 5.5V 105 dB
FREQUENCY RESPONSE
Gain-Bandwidth Product GBW VS = ±40V 7.5 MHz
Slew Rate SR VS = ±40V +23 / –38 V/µs
Settling Time: 0.1% VS = ±40V, G = +5, 10V Step, CL = 100pF 1 µs
0.01% VS = ±40V, G = +5, 10V Step, CL = 100pF 1.5 µs
Overload Recovery Time VIN • Gain = VS 1 µs
Total Harmonic Distortion + Noise THD+N VS = ±40V, VO = 30Vp-p, G = 5 0.0008 %
f = 1kHz, RL = 2kΩ
OUTPUT
Voltage Output VOUT IO = 50mA (V–) + 4.0 (V+) – 4 V
over Temperature IO = 50mA (V–) + 5 (V+) – 5.5 V
Voltage Output IO = 10mA (V–) + 2 (V+) – 2 V
over Temperature IO = 10mA (V–) + 2 (V+) – 2 V
Output Current ±50 mA
Short-Circuit Current ISC ±125 mA
Capacitive Load Drive CLOAD See Typical Characteristic
SHUTDOWN FLAG
Thermal Shutdown Status Output
Normal Operation VS = ±40V 0.1 1.0 µA
Thermally Shutdown VS = ±40V 100 140 165 µA
Junction Temperature
Shutdown +160 °C
Reset from Shutdown +145 °C
POWER SUPPLY
Supply Voltage Range VS ±10 ±40 V
Quiescent Current (per amplifier) IQ IO = 0 ±5.5 ±6.5 mA
over Temperature ±7.5 mA
TEMPERATURE RANGE TJ
Specified Range (junction) TJ –40 +125 °C
Operating Range (junction) TA –55 +125 °C
Storage Range (ambient) –65 +150 °C
Thermal Resistance θJC
TO200-7 3 °C/W
DDPAK-7 3 °C/W

NOTE: (1) All tests are high-speed tested at +25°C ambient temperature. Effective junction temperature is +25°C, unless otherwise noted.

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TYPICAL CHARACTERISTICS
At TJ = +25°C, VS = ±40V, and RL = 3.8kΩ, unless otherwise noted.
All temperatures are junction temperatures unless otherwise noted. Refer to the Applications Information section to calculate junction temperatures from ambient
temperatures for a specific configuration.

OPEN-LOOP GAIN AND PHASE vs FREQUENCY OPEN-LOOP GAIN AND PHASE vs FREQUENCY
140 0 140 0
OPA452 OPA453
120 –20 120 –20
Gain Gain
100 –40 100 –40

80 –60 80 –60
Phase Phase
Gain (dB)

Gain (dB)
Phase (°)

Phase (°)
60 –80 60 –80

40 –100 40 –100
20 –120 20 –120

0 –140 0 –140
–20 –160 –20 –160

–40 –180 –40 –180

1 10 100 1k 10k 100k 1M 10M 1 10 100 1k 10k 100k 1M 10M
Frequency (Hz) Frequency (Hz)

COMMON-MODE REJECTION RATIO vs FREQUENCY POWER-SUPPLY REJECTION RATIO vs FREQUENCY

120 140

100 120

80 100
CMRR (dB)

PSRR (dB)

+PSRR
60 80
–PSRR
40 60

20 40

0 20
1 10 100 1k 10k 100k 1M 10M 1 10 100 1k 10k 100k 1M 10M
Frequency (Hz) Frequency (Hz)

INPUT VOLTAGE AND CURRENT NOISE TOTAL HARMONIC DISTORTION + NOISE

SPECTRAL DENSITY vs FREQUENCY vs FREQUENCY
100 1
in AV = +5
en VO = 30Vp-p OPA452
RL = 600Ω, 2kΩ
Voltage Noise (nV/√Hz)
Current Noise (fA/√Hz)

0.1
600Ω
THD+N (%)

2kΩ
10 0.01
OPA453

600Ω
0.001
2kΩ

1 0.0001
10 100 1k 10k 100k 1M 10 100 1k 10k 100k
Frequency (Hz) Frequency (Hz)

OPA452, 453 5
SBOS127C www.ti.com
TYPICAL CHARACTERISTICS (Cont.)
At TJ = +25°C, VS = ±40V, and RL = 3.8kΩ, unless otherwise noted.
All temperatures are junction temperatures unless otherwise noted. Refer to the Applications Information section to calculate junction temperatures from ambient
temperatures for a specific configuration.

MAXIMUM OUTPUT VOLTAGE SWING

vs FREQUENCY OUTPUT VOLTAGE SWING vs OUTPUT CURRENT
45 (V+)

40 –55°C
Maximum Output Voltage (Vp-p)

(V+) – 2

Output Voltage Swing (V)

35
OPA452 (V+) – 4 +85°C
30
OPA453
25 (V+) – 6
+25°C
20 (V–) – 8
15 –55°C
(V–) + 4
10 +25°C
Without Slew-Induced (V–) + 2
5 Distortion
+85°C
0 (V–)
1k 10k 100k 1M 0 20 40 60 80 100 120
Frequency (Hz) Output Current (mA)

OPEN-LOOP GAIN, POWER-SUPPLY

REJECTION RATIO, AND COMMON-MODE INPUT BIAS CURRENT AND INPUT
REJECTION RATIO vs TEMPERATURE OFFSET CURRENT vs TEMPERATURE
120 10000

AOL
AOL, PSRR, and CMRR (dB)

110 1000

PSRR
Current (pA)

100 100
CMRR
+IB
–IB
90 10

80 1
IOS

70 0.1
–55 –35 –15 5 25 45 65 85 105 125 –55 –35 –15 5 25 45 65 85 105 125
Temperature (°C) Temperature (°C)

QUIESCENT CURRENT AND SHORT-CIRCUIT GAIN BANDWIDTH PRODUCT

CURRENT vs TEMPERATURE vs TEMPERATURE
160 10

OPA453
Short-Circuit Current (mA)

140 8
Quiescent Current (mA)

Gain Bandwidth (MHz)

+ISC
–ISC
120 5.7 6
IQ

100 5.5 4

OPA452
80 5.3 2

60 0
–55 –35 –15 5 25 45 65 85 105 125 –55 –35 –15 5 25 45 65 85 105 125
Temperature (°C) Temperature (°C)

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TYPICAL CHARACTERISTICS (Cont.)
At TJ = +25°C, VS = ±40V, and RL = 3.8kΩ, unless otherwise noted.
All temperatures are junction temperatures unless otherwise noted. Refer to the Applications Information section to calculate junction temperatures from ambient
temperatures for a specific configuration.

INPUT BIAS CURRENT AND INPUT OFFSET CURRENT

SLEW RATE vs TEMPERATURE vs COMMON-MODE VOLTAGE
45 20
–Slew (OPA453)
15
35 +IB
Slew Rate (V/µs)

–IB

Current (pA)
10
+Slew (OPA453)
25
5
IOS
15
+Slew (OPA452) 0
–Slew (OPA452)

5 –5
–55 –35 –15 5 25 45 65 85 105 125 –40 –30 –20 –10 0 10 20 30 40
Temperature (°C) Common-Mode Voltage (V)

QUIESCENT CURRENT AND SHORT-CIRCUIT OFFSET VOLTAGE

CURRENT vs TEMPERATURE PRODUCTION DISTRIBUTION
130 15
–ISC Percentage of Amplifiers (%)
Short-Circuit Current (mA)

Quiescent Current (mA)

120
+ISC
10

110

5
6

IQ

5 0
–55 10 20 30 40 –3 –2 –1 0 1 2 3
Temperature (°C) Offset Voltage (mV)

OFFSET VOLTAGE DRIFT DISTRIBUTION SETTLING TIME vs CLOSED-LOOP GAIN

20 100

15
Settling Time (µs)
Amplifiers (%)

10 10
0.01%
0.01%

5 OPA452
0.1%
0.1% OPA453

0 1
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 10 100
Offset Voltage Drift (µV/°C) Gain (V/V)

OPA452, 453 7
SBOS127C www.ti.com
TYPICAL CHARACTERISTICS (Cont.)
At TJ = +25°C, VS = ±40V, and RL = 3.8kΩ, unless otherwise noted.
All temperatures are junction temperatures unless otherwise noted. Refer to the Applications Information section to calculate junction temperatures from ambient
temperatures for a specific configuration.

SMALL-SIGNAL OVERSHOOT LARGE-SIGNAL STEP RESPONSE

vs LOAD CAPACITANCE (G = 1, CL = 100pF)
60
OPA452 OPA452
OPA453
50
G = –1
40
Overshoot (%)

10V/div
G = –4
30

G = –2
20

G = +1
10
G = –6
G = –8
0
0.01 0.1 1 10 32 2.5µs/div
Load Capacitance

LARGE-SIGNAL STEP RESPONSE SMALL-SIGNAL STEP RESPONSE

(G = 5, CL = 100pF) (G = 1, CL = 100pF)

OPA453 OPA452
10V/div

20V/div

2.5µs/div 1µs/div

SMALL-SIGNAL STEP RESPONSE SMALL-SIGNAL STEP RESPONSE

(G = 5, CL = 100pF) (G = –1, CL = 1000pF)

OPA453 OPA452
20V/div

20V/div

500ns/div 2.5µs/div

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APPLICATIONS INFORMATION CURRENT LIMIT
The OPA452 and OPA453 are designed with internal cur-
Figure 1 shows the OPA452 connected as a basic noninverting
rent-limiting circuitry that limits the output current to approxi-
amplifier. The OPA452 can be used in virtually any op amp
mately 125mA. The current limit varies slightly with increas-
configuration. The OPA453 is designed for use in configura-
ing junction temperature and supply voltage, as shown in the
tions with gains of 5 or greater. Power-supply terminals
Typical Characteristics. Current limit, in combination with the
should be bypassed with 0.1µF capacitors, or greater, near
thermal protection circuitry, provides protection from most
the power-supply pins. Be sure that the capacitors are
types of overload conditions including short-circuit to ground.
appropriately rated for the power-supply voltage used. The
OPA452 and OPA453 can supply output currents up to
50mA with excellent performance. THERMAL PROTECTION
The OPA452 and OPA453 have thermal shutdown circuitry
that protects the amplifier from damage caused by overload
V+
conditions. The thermal protection circuitry disables the out-
10µF put when the junction temperature reaches approximately
R2
G = 1+
+ R1 160°C, allowing the device to cool. When the junction tem-
0.1µF perature cools to approximately 140°C, the output circuitry is
R1 R2 automatically re-enabled.
The thermal shutdown function is not intended to replace
proper heat sinking. Activation of the thermal shutdown
circuitry is an indication of excessive power dissipation or an
OPA452 VO inadequate heat sink. Continuously running the amplifier into
ZL
thermal shutdown can degrade reliability.
VIN Flag
The Thermal Shutdown Indicator (Flag) pin can be monitored
(optional) to determine if shutdown is occurring. During normal opera-
tion, the current output from the flag pin is typically 50nA.
During shutdown, the current output from the flag pin in-
0.1µF
creases to 140µA (typical). This current output allows for
easy interfacing to external logic. Figure 2 shows two ex-
10µF
+ amples implementing this function.

V–

FIGURE 1. Basic Circuit Connections.

OPA452 VOUT OPA452 VOUT

Flag +5V
100µA to +5V
165µA
HCT logic has relatively well- Interface to virtually any CMOS
controlled logic level. A properly HCT logic gate by choosing a resistor
chosen resistor value can 19.1kΩ value that provides an assured CMOS
assure proper logic high level logic high voltage with the 39kΩ
throughout the full range of flag minimum (100µA) flag current.
output current. Logic
Logic
Ground
Ground

Interfacing with HCT Logic Interfacing with CMOS Logic

FIGURE 2. Thermal Shutdown Indicator.

OPA452, 453 9
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POWER SUPPLIES Where,
The OPA452 and OPA453 may be operated from power VO = output voltage
supplies of ±10V to ±40V, or a total of 80V with excellent VS = supply voltage
performance. Most behavior remains unchanged throughout
IO = output current
the full operating voltage range. Parameters that vary signifi-
cantly with operating voltage are shown in the Typical Char- RL = load resistance
acteristics. TJ = junction temperature (°C)
For applications that do not require symmetrical output volt- TA = ambient temperature (°C)
age swing, power-supply voltages do not need to be equal. θJA = junction-to-air thermal resistance (°C/W)
The OPA452 and OPA453 can operate with as little as 20V
To estimate the margin of safety in a complete design
between the supplies or with up to 80V between the supplies.
(including heat sink), increase the ambient temperature until
For example, the positive supply could be set to 70V with the
the thermal protection is activated. Use worst-case load and
negative supply at –10V or vice-versa.
signal conditions. For good reliability, the thermal protection
The tabs of the DDPAK-7 and TO220 packages are electri- should trigger more than +35°C above the maximum ex-
cally connected to the negative supply (V–), however, these pected ambient condition of your application. This ensures a
connections should not be used to carry current. For best maximum junction temperature of +125°C at the maximum
thermal performance, the tab should be soldered directly to expected ambient condition.
the circuit board copper area (see Heat Sinking section).
Operation from a single power supply (or unbalanced power
supplies) can produce even larger power dissipation be-
POWER DISSIPATION cause a larger voltage can be impressed across the conduct-
Internal power dissipation of these op amps can be quite ing output transistor. Consult Application Bulletin SBOA022
large. All of the specifications for the OPA452 and OPA453 at www.ti.com for further information on how to calculate or
may change with junction temperature. If the device is not measure power dissipation.
subjected to internal self-heating, the junction temperature Power dissipation can be minimized by using the lowest
will be the same as the ambient. However, in practical possible supply voltage. For example, with a 50mA load, the
applications, the device will self-heat and the junction tem- output will swing to within 5.0V of the power-supply rails.
perature will be significantly higher than ambient. The follow- Power supplies set to no more than 5.0V above the maxi-
ing calculation can be performed to establish junction tem- mum output voltage swing required by the application will
perature as a function of ambient temperature and the minimize the power dissipation.
conditions of the application.
Consider the OPA452 in a circuit configuration where the SAFE OPERATING AREA
load is 600Ω and the output voltage is 20V. The supplies are
The Safe Operating Area (SOA curves, Figure 3) shows the
at ±40V and the ambient temperature (TA) is 40°C. The θJA
permissible range of voltage and current. The safe output
for the package plus heat sink is 30°C/W.
current decreases as the voltage across the output transistor
First, the quiescent heating of the op amp is as follows: (VS – VO) increases. For further insight on SOA, consult
PD(internal) = IQ • VS = 6mA • 80V = 480mW Application Report SBOA022.
The output current (IO) can be calculated: Output short circuits are a very demanding case for SOA. A
IO = VO/RL = 20V/600Ω = 33.33mA short-circuit to ground forces the full power-supply voltage
(V+ or V–) across the conducting transistor and produces a
The power being dissipated (PD) in the output transistor of
the amplifier can be calculated:
PD(output stage) = IO • (VS – VO) = 33.3mA • (40 – 20) = 667mW SAFE OPERATING AREA
100
PD(total) = PD(internal) + PD(output stage) = 480mW + 667mW = 1147mW
50
The resulting junction temperature can be calculated:
TJ = TA + PD θJA +85°C, θ = 40
10
TJ = 40°C + 1147mW • 30°C/W = 74.4°C +85°C, θ =θ20
IO (mA)

θ is total thermal
resistance including +25°C, θ = 40
junction-to-case.
1
+25°C,θθ = 3
This graph is for
+125°C max operating
temperature.
0.1
10 80 100
| VS | – | VO | (V)

FIGURE 3. DDPAK-7 and TO220-7 Safe Operating Area.

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typical output current of 125mA. With ±40V power supplies, CAPACITIVE LOADS
this creates an internal dissipation of 10W. This far exceeds The dynamic characteristics of the OPA452 and OPA453
practical heat sinking and is not recommended. If operation have been optimized for commonly encountered gains, loads,
in this region is unavoidable, use the part with a heat sink. and operating conditions. The combination of low closed-
loop gain and capacitive load will decrease the phase margin
HEAT SINKING and may lead to gain peaking or oscillations. Figure 5 shows
Power dissipated in the OPA452 or OPA453 will cause the a circuit that preserves phase margin with capacitive load.
junction temperature to rise. For reliable operation, the junc- Figure 6 shows the small-signal step response for the circuit
tion temperature should be limited to +125°C. Many applica- in Figure 5. Consult Application Bulletin SBOA015, at
tions will require a heat sink to assure that the maximum www.ti.com, for more information.
operating junction temperature is not exceeded. The heat
sink required depends on the power dissipated and on
ambient conditions.
For heat sinking purposes, the tab of the DDPAK is typically +40V
soldered directly to a circuit board copper area. Increasing
the copper area improves heat dissipation. Figure 4 shows
typical thermal resistance from junction-to-ambient as a
function of copper area. OPA452
Depending on conditions, additional heat sinking may be
RG RF 10nF
required. Aavid Thermal Products Inc. manufactures sur-
5kΩ 5kΩ
face-mountable heat sinks designed specifically for use with
VI
these packages. Further information is available on Aavid’s
CS CF
web site, www.aavid.com. 1.8nF 270pF

–40V

THERMAL RESISTANCE vs
CIRCUIT BOARD COPPER AREA
50

FIGURE 5. Driving Large Capacitive Loads.

Thermal Resistance, θJA (°C/W)

OPA452FA, OPA453FA
40 Surface-Mount Package
1oz. copper

30
SMALL-SIGNAL STEP RESPONSE
20 (G = –1, CL = 10nF)

OPA452
10

0
20mV/div

0 1 2 3 4 5
Copper Area (inches2)

Circuit Board Copper Area

2.5µs/div

FIGURE 6. Small-Signal Step Response for Figure 5.

OPA452FA, OPA453FA
Surface-Mount Package

FIGURE 4. DDPAK Thermal Resistance versus Circuit Board

Copper Area.

OPA452, 453 11
SBOS127C www.ti.com
INCREASING OUTPUT CURRENT INPUT PROTECTION
In those applications where the 50mA of output current is not The OPA452 and OPA453 feature internal clamp diodes to
sufficient to drive the desired load, output current can be protect the inputs when voltages beyond the supply rails are
increased by connecting two or more OPA452s or OPA453s encountered. However, input current should be limited to
in parallel, as shown in Figure 7. Amplifier A1 is the master 5mA. In some cases, an external series resistor may be
amplifier and may be configured in virtually any op amp required. Many input signals are inherently current-limited,
circuit. Amplifier A2, the slave, is configured as a unity gain therefore, a limiting resistor may not be required. Please
buffer. Alternatively, external output transistors can be used consider that a large series resistor, in conjunction with the
to boost output current. The circuit in Figure 8 is capable of input capacitance, can affect stability.
supplying output currents up to 1A. Alternatively, the OPA547,
OPA548, and OPA549 series power op amps should be USING THE OPA453 IN LOW GAINS
considered for high output current drive, along with program-
The OPA453 is intended for applications with signal gains of
mable current limit and output disable capability.
5 or greater, but it is possible to take advantage of its high
slew rate in lower gains using an external compensation
R1 R2 technique in an inverting configuration. This technique main-
tains low noise characteristics of the OPA453 architecture at
RS(1)
low frequencies. Depending on the application, a small in-
“MASTER”
10Ω crease in high-frequency noise may result. This technique
OPA452 shapes the loop gain for good stability while giving an easily
VIN controlled 2nd-order low-pass frequency response.
Considering only the noise gain (noninverting signal gain) for
the circuit of Figure 9, the low-frequency noise gain (NG1) will
RS(1) be set by the resistor ratios, whereas the high-frequency
10Ω
noise gain (NG2) will be set by the capacitor ratios. The
OPA452
capacitor values set both the transition frequencies and the
“SLAVE” RL high-frequency noise gain. If this noise gain, determined by
NG2 = 1 + CS/CF, is set to a value greater than the recom-
mended minimum stable gain for the op amp and the noise
NOTE: (1) RS resistors minimize the circulating
gain pole, set by 1/RFCF, is placed correctly, a very well
current that can flow between the two devices controlled, 2nd-order low-pass frequency response will result.
due to VOS errors.
To choose the values for both CS and CF, two parameters
and only three equations need to be solved. First, the target
FIGURE 7. Parallel Amplifiers Increase Output Current Ca- for the high-frequency noise gain (NG2) should be greater
pability. than the minimum stable gain for the OPA453. In the circuit
in Figure 9, a target NG2 of 10 is used. Second, the signal
gain of –1 in Figure 10 sets the low-frequency noise gain to
R1 R2
NG1 = 1 + RF/RG (= 2 in this example). Using these two gains,
knowing the Gain Bandwidth Product (GBP) for the OPA453
+40V
(7.5MHz), and targeting a maximally flat 2nd-order, low-pass
Butterworth frequency response (Q = 0.707), the key fre-
quency in the compensation can be found.
TIP29C
CF For the values in Figure 9, the f–3dB will be approximately
R4
180kHz. This is less than that predicted by simply dividing the
0.2Ω
R3(1) GBP by NG1. The compensation network controls the band-
100Ω
OPA452 VO width to a lower value while providing good slew rate at the
VIN
R4
output and an exceptional distortion performance due to
0.2Ω increased loop gain at frequencies below NG1 • Z0. The
LOAD capacitor values in Figure 10 are calculated for NG1 = 2 and
TIP30C NG2 = 10 with no adjustment for parasitics.
Actual circuit values can be optimized by checking the small-
signal step response with actual load conditions. See Figure 9
–40V
for the small-signal step response of this OPA453, G = –1
NOTE: (1) R3 provides current limit and allows the amplifier to
drive the load when the output is between 0.7V and –0.7V.
circuit with a 1000pF load. It is well-behaved with no tendency
to oscillate. If CS and CF were removed, the circuit would be
unstable.

FIGURE 8. External Output Transistors Boost Output Cur-

rent Up to 1 Amp.

12
OPA452, 453
www.ti.com SBOS127C
 +40V SMALL-SIGNAL STEP RESPONSE
(G = –1, CL = 1000pF)

OPA453

OPA453 VOUT

20mV/div
RG RF
5kΩ 5kΩ
VIN
CS CF
1.8nF 200pF

–40V

NG1 = 1 + RF/RG = 2
NG2 = 1 + CS/CF = 10 2.5µs/div

FIGURE 9. Compensation of the OPA453 for G = –1. FIGURE 10. Small-Signal Step Response for Figure 9.

OPA452, 453 13
SBOS127C www.ti.com
 PACKAGE OPTION ADDENDUM

www.ti.com 13-Aug-2021

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

OPA452FA/500 ACTIVE DDPAK/ KTW 7 500 RoHS & Green Call TI | SN Level-3-245C-168 HR -40 to 125 OPA452F
TO-263
OPA452FAKTWT ACTIVE DDPAK/ KTW 7 250 RoHS & Green Call TI | SN Level-3-245C-168 HR -40 to 125 OPA452F
TO-263
OPA452FAKTWTG3 ACTIVE DDPAK/ KTW 7 250 RoHS & Green SN Level-3-245C-168 HR -40 to 125 OPA452F
TO-263
OPA453FAKTWT ACTIVE DDPAK/ KTW 7 250 RoHS & Green Call TI | SN Level-3-245C-168 HR -40 to 125 OPA453F
TO-263
OPA453TA ACTIVE TO-220 KC 7 50 RoHS & Green Call TI | SN N / A for Pkg Type -40 to 125 OPA453T

OPA453TA-1 ACTIVE TO-220 KVT 7 50 RoHS & Green Call TI | SN N / A for Pkg Type -40 to 125 OPA453T

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 13-Aug-2021

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

TUBE

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
OPA453TA KC TO-220 7 50 532.13 34.54 13340 NA
OPA453TA-1 KVT TO-220 7 50 532.13 34.54 13340 NA

Pack Materials-Page 1
 MECHANICAL DATA

MPSF015 – AUGUST 2001

KTW (R-PSFM-G7) PLASTIC FLANGE-MOUNT

0.410 (10,41) 0.304 (7,72)

–A–
0.385 (9,78) 0.006 0.296 (7,52)
–B–
0.303 (7,70) 0.300 (7,62)
0.0625 (1,587) H 0.297 (7,54) 0.055 (1,40) 0.252 (6,40)
0.064 (1,63)
0.0585 (1,485) 0.045 (1,14)
0.056 (1,42)

0.370 (9,40) 0.187 (4,75)

0.330 (8,38) 0.179 (4,55)
H A
0.605 (15,37)
0.595 (15,11)
0.012 (0,305)
C 0.000 (0,00)
0.104 (2,64)
0.019 (0,48) 0.096 (2,44) H
0.017 (0,43)

0.050 (1,27) 0.026 (0,66)

C
0.034 (0,86) 0.014 (0,36)
0°~3°
C F 0.022 (0,57)
0.010 (0,25) M B AM C M

0.183 (4,65)
0.170 (4,32)

4201284/A 08/01

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.
C. Lead width and height dimensions apply to the
plated lead.
D. Leads are not allowed above the Datum B.
E. Stand–off height is measured from lead tip
with reference to Datum B.
F. Lead width dimension does not include dambar
protrusion. Allowable dambar protrusion shall not
cause the lead width to exceed the maximum
dimension by more than 0.003”.
G. Cross–hatch indicates exposed metal surface.
H. Falls within JEDEC MO–169 with the exception
of the dimensions indicated.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 MECHANICAL DATA

MSOT010 – OCTOBER 1994

KC (R-PSFM-T7) PLASTIC FLANGE-MOUNT PACKAGE

0.156 (3,96)
0.420 (10,67) DIA 0.185 (4,70)
0.146 (3,71)
0.380 (9,65) 0.175 (4,46)
0.113 (2,87) 0.055 (1,40)
0.103 (2,62) 0.045 (1,14)

0.147 (3,73)
0.137 (3,48)

0.335 (8,51)
0.325 (8,25)
1.020 (25,91)
1.000 (25,40)

1 7

0.125 (3,18)
(see Note C)

0.030 (0,76) 0.122 (3,10)

0.050 (1,27)
0.026 (0,66) 0.102 (2,59)
0.010 (0,25) M 0.025 (0,64)
0.300 (7,62)
0.012 (0,30)

4040251 / B 01/95

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.
C. Lead dimensions are not controlled within this area.
D. All lead dimensions apply before solder dip.
E. The center lead is in electrical contact with the mounting tab.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

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