OPA445

SBOS156B − MARCH 1987 − REVISED APRIL 2008

High Voltage FET-Input

OPERATIONAL AMPLIFIER
FEATURES DESCRIPTION
D WIDE-POWER SUPPLY RANGE:
±10V to ±45V The OPA445 is a monolithic operational amplifier capable
D HIGH SLEW RATE: 15V/µs of operation from power supplies up to ±45V and output
currents of 15mA. It is useful in a wide variety of
D LOW INPUT BIAS CURRENT: 10pA applications requiring high output voltage or large
D STANDARD-PINOUT TO-99, DIP, SO-8 common-mode voltage swings.
PowerPAD, AND SO-8 SURFACE-MOUNT
PACKAGES The OPA445’s high slew rate provides wide power-
bandwidth response, which is often required for
high-voltage applications. FET input circuitry allows the
APPLICATIONS use of high-impedance feedback networks, thus minimiz-
D TEST EQUIPMENT ing their output loading effects. Laser trimming of the input
circuitry yields low input offset voltage and drift.
D HIGH-VOLTAGE REGULATORS
D POWER AMPLIFIERS The OPA445 is available in standard pinout TO-99, DIP-8,
D DATA ACQUISITION and SO-8 surface-mount packages as well as an SO-8
D SIGNAL CONDITIONING PowerPAD package for reducing junction temperature. It
is fully specified from −25°C to +85°C and operates from
D AUDIO −55°C to +125°C. A SPICE macromodel is available for
D PIEZO DRIVERS design analysis (from www.ti.com).

OPA445
NC OPA445

8 Offset Trim 1 8 NC
Offset
Trim 1 7 V+
−In 2 7 V+

+In 3 6 Output
−In 2 6 Output
V− 4 5 Offset Trim

+In 3 5 Offset
DIP−8, SO−8, SO−8 PowerPAD
4 Trim

V− NC = No internal connection;
Case is connected to V− leave NC floating or connect to GND, V+, or V−.
TO−99

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments, Inc. All other trademarks are the property of their respective owners.

             
 Copyright  1987−2008, Texas Instruments Incorporated
                  

   !       !   

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This integrated circuit can be damaged by ESD. Texas

ABSOLUTE MAXIMUM RATINGS(1) Instruments recommends that all integrated circuits be
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50V handled with appropriate precautions. Failure to observe
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±80V proper handling and installation procedures can cause damage.
Input Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |±VS| − 3V
ESD damage can range from subtle performance degradation to
Storage Temperature Range: M . . . . . . . . . . . . . . −65°C to +150°C complete device failure. Precision integrated circuits may be more
P, U, DDA . . . . . . . −55°C to +125°C susceptible to damage because very small parametric changes could
Operating Temperature Range . . . . . . . . . . . . . . . −55°C to +125°C cause the device not to meet its published specifications.
Output Short-Circuit to Ground (TJ < +125°C) . . . . . . Continuous
Junction Temperature: M . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175°C
Junction Temperature: P, U, DDA . . . . . . . . . . . . . . . . . . . . . +150°C
(1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods
may degrade device reliability. These are stress ratings only, and
functional operation of the device at these or any other conditions
beyond those specified is not supported.

ORDERING INFORMATION(1)
PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR PACKAGE MARKING
OPA445AP DIP-8 P OPA445AP
OPA445AU SO-8 Surface-Mount D OPA445AU
OPA445ADDA SO-8 PowerPAD DDA OPA445
OPA445BM TO-99 8-Pin LMC OPA445BM
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI web site
at www.ti.com.

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ELECTRICAL CHARACTERISTICS
Boldface limits apply over the specified temperature range, TA = −25°C to +85°C. VS = ±40V.
At TA = +25°C, VS = ±40V, and RL = 5kΩ, unless otherwise noted.
OPA445BM OPA445AP, AU, ADDA
PARAMETER TEST CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
OFFSET VOLTAGE
Input Offset Voltage VOS VCM = 0, IO = 0 ±1 ±3 ±1.5 ±5 mV
vs Temperature VOS/dT TA = −25°C to +85°C ±10 * µV/°C
vs Power Supply PSRR VS = ±10V to ±45V 4 100 ∗ ∗ µV/V
INPUT BIAS CURRENT(1)
Input Bias Current IB VCM = 0V ±10 ±50 ∗ ±100 pA
Over Specified Temperature Range ±10 ±20 nA
Input Offset Current IOS VCM = 0V ±4 ±20 ∗ ±40 pA
Over Specified Temperature Range ±5 ±10 nA
NOISE
Input Voltage Noise Density, f = 1kHz en 15 ∗ nV/√Hz
Current Noise Density, f = 1kHz in 6 ∗ fA/√Hz
INPUT VOLTAGE RANGE
Common-Mode Voltage Range VCM VS = ±40V (V−) + 5 (V+) − 5 ∗ ∗ V
Common-Mode Rejection CMRR VCM = −35V to +35V 80 95 ∗ ∗ dB
Over Specified Temperature Range 80 * dB
INPUT IMPEDANCE
Differential 1013 || 1 ∗ Ω || pF
Common-Mode 1014 || 3 ∗ Ω || pF
OPEN-LOOP GAIN, DC
Open-Loop Voltage Gain AOL VO = −35V to +35V 100 110 ∗ ∗ dB
Over Specified Temperature Range 97 ∗ dB
FREQUENCY RESPONSE
Gain Bandwidth Product GBW 2 ∗ MHz
Slew Rate SR VO = 70VPP 5 15 ∗ ∗ V/µs
Full Power Bandwidth VO = 70VPP 23 70 ∗ ∗ kHz
Rise Time VO = ±200mV 100 ∗ ns
Overshoot G = +1, ZL = 5kΩ || 50pF 35 ∗ %
Total Harmonic Distortion + Noise THD+N f = 1kHz, VO = 3.5Vrms, G = 1 0.0002 ∗ %
f = 1kHz, VO = 10Vrms, G = 1 0.00008 ∗ %
OUTPUT
Voltage Output VO (V−) + 5 (V+) − 5 ∗ ∗ V
Over Specified Temperature Range (V−) + 5 (V+) − 5 * * V
Current Output IO VO = ±28V ±15 ∗ mA
Output Resistance, Open Loop RO dc 220 ∗ Ω
Short Circuit Current ISC ±26 ∗ mA
Capacitive Load Drive CLOAD See Typical Characteristic(2) ∗
POWER SUPPLY
Specified Operating Range VS ±40 ∗ V
Operating Voltage Range ±10 ±45 ∗ ∗ V
Quiescent Current IQ IO = 0 ±4.2 ±4.7 ∗ ∗ mA
TEMPERATURE RANGE
Specification Range −25 +85 ∗ ∗ °C
Operating Range −55 +125 ∗ ∗ °C
Storage Range −65 +125 −55 +125 °C
Thermal Resistance,
qJA
Junction-to-Ambient
TO-99 200 °C/W
DIP-8 100 °C/W
SO-8 Surface-Mount 150 °C/W
SO-8 PowerPAD(3) 52 °C/W
Thermal Resistance, Junction-to-Case qJC
SO-8 PowerPAD(3) 10 °C/W

NOTE: ∗ Specifications same as OPA445BM.

(1) High-speed test at TJ = +25°C.
(2) See Small-Signal Overshoot vs Load Capacitance in the Typical Characteristics section.
(3) Test board 1in x 0.5in heat-spreader, 1oz copper.

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TYPICAL CHARACTERISTICS
At TA = +25°C and VS = ±40V, unless otherwise noted.

OPEN−LOOP GAIN AND PHASE OPEN−LOOP GAIN AND SUPPLY CURRENT

vs FREQUENCY vs SUPPLY VOLTAGE
140 125 4.5

120 −45 120

Supply Current (mA)

100
Voltage Gain (dB)

Voltage Gain (dB)

115 IQ 4.0
AVOL

Phase (_ )
80 −90
θ
110
60
105 3.5
40 −135
Gain 100
20

0 −185 95 3.0
10 100 1k 10k 100k 1M 10M 10 20 30 40 50
Frequency (Hz) Supply Voltage (±VS)

GAIN BANDWIDTH AND SLEW RATE GAIN BANDWIDTH AND SLEW RATE
vs TEMPERATURE vs SUPPLY VOLTAGE
2.6 16 2.2 19

2.4 15
SR
Gain Bandwidth (MHz)
Gain Bandwidth (MHz)

GBW

Slew Rate (V/µs)

Slew Rate (V/µs)

2.2 14 2.0 17

2.0 13
GBW
1.8 12 1.8 15
SR
1.6 11

1.4 10 1.6 13
−75 −50 −25 0 25 50 75 100 125 10 20 30 40 50
Ambient Temperature (_C) Supply Voltage (±VS)

INPUT BIAS CURRENT INPUT BIAS CURRENT

vs TEMPERATURE vs COMMON−MODE VOLTAGE
100nA 40

10nA 35

30
1nA
Input Bias Current

Bias Current (pA)

25
100pA
20
10pA
15
−I B +IB
1pA
10
0.1pA 5
0.01pA 0
−75 −50 −25 0 25 50 75 100 125 −50 −40 −30 −20 −10 0 10 20 30 40 50
Temperature (_ C) Common−Mode Voltage (V)

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TYPICAL CHARACTERISTICS (continued)

At TA = +25°C and VS = ±40V, unless otherwise noted.

POWER SUPPLY REJECTION COMMON−MODE REJECTION

vs FREQUENCY vs FREQUENCY
120 100

Common−Mode Rejection (dB)

100 90
Power Supply Rejection (dB)

+PSRR
80 80

60 70

−PSRR
40 60

20 50

0 40
10 100 1k 10k 100k 1M 10M 100M 10 100 1k 10k 100k 1M 10M
Frequency (Hz) Frequency (Hz)

OPEN−LOOP GAIN POWER SUPPLY REJECTION AND

vs TEMPERATURE COMMON−MODE REJECTION vs TEMPERATURE
120 130

120
PSRR, CMRR (dB)

PSRR
Voltage Gain (dB)

110 110

100

CMRR
100 90

80

90 70
−75 −50 −25 0 25 50 75 100 125 −75 −50 −25 0 25 50 75 100 125
Ambient Temperature (_ C) Ambient Temperature (_ C)

INPUT VOLTAGE TOTAL HARMONIC DISTORTION + NOISE

NOISE SPECTRAL DENSITY vs FREQUENCY
100 0.1
Voltage Noise (nV/√Hz)

0.01
THD+Noise (%)

VO = 3.5Vrms

10 0.001 G = 10
VO = 10Vrms
VO = 3.5Vrms

0.0001 G=1
VO = 10Vrms

1 0.00001
10 100 1k 10k 100k 20 100 1k 10k 20k
Frequency (Hz) Frequency (Hz)

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TYPICAL CHARACTERISTICS (continued)

At TA = +25°C and VS = ±40V, unless otherwise noted.

OUTPUT VOLTAGE SWING vs OUTPUT CURRENT OUTPUT VOLTAGE SWING vs TEMPERATURE

(V+) (V+)
(V+) − 2 (V+) − 1
(V+) − 4 Positive Swing
(V+) − 2
Output Voltage Swing (V)

Output Voltage Swing (V)

(V+) − 6
Sourcing (V+) − 3
(V+) − 8
Current
(V+) − 10 (V+) − 4
(V−) + 10 (V−) + 4
(V−) + 8
(V−) + 3
(V−) + 6 Sinking Negative Swing
(V−) + 2
(V−) + 4 Current
(V−) + 2 (V−) + 1

(V−) (V−)
0 ±5 ±10 ±15 ±20 ±25 ±30 −75 −50 −25 0 25 50 75 100 125
Output Current (mA) Temperature (_C)

SUPPLY CURRENT vs TEMPERATURE OUTPUT CURRENT vs TEMPERATURE

5 35

30
Short−Circuit Current
Supply Current (mA)

Output Current (mA)

25
4
20

15
Output Current
3
10
VO = ±35V
5

2 0
−75 −50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125
Ambient Temperature (_C) Temperature (_ C)

OFFSET VOLTAGE
PRODUCTION DISTRIBUTION OFFSET VOLTAGE DRIFT
20 PRODUCTION DISTRIBUTION
Typical production 25
18 distribution of Typical production
packaged units. distribution of
16
Percent of Amplifiers (%)

20 packaged units.
Percent of Amplifiers (%)

14
12
15
10
8
10
6
4
5
2
0
0
− 5 .0
− 4 .5
− 4 .0
− 3 .5
− 3 .0
− 2 .5
− 2 .0
− 1 .5
− 1 .0
− 0 .5
0
0 .5
1 .0
1 .5
2 .0
2 .5
3 .0
3 .5
4 .0
4 .5
5 .0

0
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

Offset Voltage (mV) Offset Voltage Drift (µV/_ C)

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TYPICAL CHARACTERISTICS (continued)

At TA = +25°C and VS = ±40V, unless otherwise noted.

MAXIMUM POWER DISSIPATION MAXIMUM POWER DISSIPATION

vs TEMPERATURE vs TEMPERATURE
0.8 2.0
No Heat Sink SO−8 PowerPAD:
0.7 TJ(max) = +125_C
Plastic DIP
0.6 1.5
TO−99
Dissipation (W)

Dissipation (W)
0.5

0.4 1.0
SO−8
0.3 Surface−Mount
(non PowerPAD)
0.2 0.5 T J (125 _ C max) = TA + [(|V S | − |V O |) IO × θ JA ]
TJ (max) θ JA = 52 _ C/W, SO−8 PowerPAD
0.1 TO−99: 150_ C (1in × 0.5in heat−spreader, 1oz Copper)
DIP, SO: 125_C T J = 25 _ C + (1.93W × 52 _ C/W) = +125 _ C
0 0
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125
Temperature (_C) Temperature (_C)

MAXIMUM OUTPUT VOLTAGE SWING SMALL−SIGNAL OVERSHOOT

vs FREQUENCY vs LOAD CAPACITANCE
90 60
Maximum output
80 without slew−rate
induced distortion. 50
70
Output Voltage (VPP)

G = −1
60 40
Overshoot (%)

50
30 G = +1
40

30 20 G = −2

20
10
10 G = 10
0 0
1k 10k 100k 1M 10pF 100pF 1nF 10nF
Frequency (Hz) Load Capacitance

SMALL−SIGNAL STEP RESPONSE LARGE−SIGNAL STEP RESPONSE

G = 1, CL = 100pF G = 1, CL = 100pF
50mV/div

10V/div

500ns/div 2.5µs/div

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APPLICATIONS INPUT PROTECTION

The inputs of conventional FET-input op amps should be
Figure 1 shows the OPA445 connected as a basic
protected against destructive currents that can flow when
noninverting amplifier. The OPA445 can be used in
input FET gate-to-substrate isolation diodes are
virtually any op amp configuration.
forward-biased. This can occur if the input voltage
Power-supply terminals should be bypassed with 0.1µF exceeds the power supplies or there is an input voltage
capacitors, or greater, near the power supply pins. Be sure with VS = 0V. Protection is easily accomplished with a
that the capacitors are appropriately rated for the resistor in series with the input. Care should be taken
power-supply voltage used. because the resistance in series with the input
capacitance may affect stability. Many input signals are
inherently current-limited; therefore, a limiting resistor may
V+
not be required.
0.1µF
R2
G = 1+ OFFSET VOLTAGE TRIM
R1
R1 R2
The OPA445 provides offset voltage trim connections on
pins 1 and 5. Offset voltage can be adjusted by connecting
a potentiometer as shown in Figure 2. This adjustment
OPA445 VO should be used only to null the offset of the op amp, not to
VIN ZL
adjust system offset or offset produced by the signal
source. Nulling system offset could degrade the offset
0.1µF voltage drift behavior of the op amp. While it is not possible
to predict the exact change in drift, the effect is usually
small.
V−

Figure 1. The OPA445 Configured as a

Noninverting Amplifier
Use offset adjust pins
V+ only to null offset voltage
of op amp−see text.
POWER SUPPLIES 2
7

The OPA445 may be operated from power supplies up to 6

OPA445
±45V or a total of 90V with excellent performance. Most 3 1 10mV Typical
behavior remains unchanged throughout the full operating 5 Trim Range
voltage range. Parameters which vary significantly with 4
(1)
operating voltage are shown in the Typical Characteristics.
NOTE: (1) 10kΩ to 1MΩ
Some applications do not require equal positive and Trim Potentiometer
V− (100kΩ recommended).
negative output voltage swing. Power-supply voltages do
not need to be equal. The OPA445 can operate with as little
as 20V between the supplies and with up to 90V between
the supplies. For example, the positive supply could be set
to 80V with the negative supply at −10V, or vice-versa. Figure 2. Offset Voltage Trim

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CAPACITIVE LOADS INCREASING OUTPUT CURRENT

The dynamic characteristics of the OPA445 have been In those applications where the 15mA of output current is
optimized for commonly encountered gains, loads, and not sufficient to drive the required load, output current can
operating conditions. The combination of low closed-loop be increased by connecting two or more OPA445s in
gain and capacitive load will decrease the phase margin parallel as shown in Figure 4. Amplifier A1 is the master
and may lead to gain peaking or oscillations. Figure 3 amplifier and may be configured in virtually any op amp
shows a circuit which preserves phase margin with circuit. Amplifier A2, the slave, is configured as a unity gain
capacitive load. The circuit does not suffer a voltage drop buffer. Alternatively, external output transistors can be
due to load current; however, input impedance is reduced used to boost output current. The circuit in Figure 5 is
at high frequencies. Consult Application Bulletin capable of supplying output currents up to 1A.
SBOA015, available for download at www.ti.com, for
details of analysis techniques and application circuits.
R1 R2

R1 R2
Master RS(1)
10Ω
2kΩ 2kΩ
OPA445
RC R2 VIN
G=1+
20Ω R1

CC
0.22µF RS(1)
OPA445 VO
10Ω
VIN
OPA445
CL
R2 5000pF
RC = Slave RL
2CL × 1010 − (1 + R2 /R1)

CL × 103
CC =
RC NOTE: (1) RS resistors minimize the circulating
current that will always flow between the two devices
NOTE: Design equations and component values are approximate. due to VOS errors.
User adjustment is required for optimum performance.

Figure 4. Parallel Amplifiers Increase Output

Figure 3. Driving Large Capacitive Loads Current Capability

R1 R2

+45V

TIP29C
CF
R4
(1)
0.2Ω
R3
100Ω
OPA445 VO
VIN
R4
0.2Ω LOAD

TIP30C

−45V
NOTE: (1) Provides current limit for OPA445 and allows the amplifier to
drive the load when the output is between +0.7V and −0.7V.

Figure 5. External Output Transistors Boost Output Current Up to 1 Amp

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SAFE OPERATING AREA 100

Stress on the output transistors is determined both by the TA = 25_C

output current and by the output voltage across the

Output Current (mA)

conducting output transistors, VS − VO. The power 10
dissipated by the output transistor is equal to the product TA = 125_ C
of the output current and the voltage across the conducting TA = 85_ C
transistor, VS − VO. The Safe Operating Area (SOA curve,
Figure 6 through Figure 10) illustrates the permissible 1 TA + [(|VS| − |VO|) I O × θ JA] ≤ TJ (max)
range of voltage and current. The curves shown represent θ JA = 200_C/W (No Heat−Sink)
TJ (max) = 150_C
devices soldered to a printed circuit board (PCB) with no
NOTE: Simple clip−on heat−sinks can
heat sink. Increasing printed circuit trace area or the use reduce θ by as much as 50_ C/W.
of a heat sink (TO-99 package) can significantly reduce 0.1
1 2 5 10 20 50 100
thermal resistance (q ), resulting in increased output
|VS| − |VO| (V)
current for a given output voltage (see Figure 11,
Figure 12, and the Heat Sink section).
Figure 7. TO-99 Safe Operating Area
The safe output current decreases as VS − VO increases.
Output short-circuits are a very demanding case for SOA. 100
A short-circuit to ground forces the full power supply
TA = 25_C
voltage (V+ or V−) across the conducting transistor and
produces a typical output current of 25mA. With ±40V
power supplies, this creates an internal dissipation of 1W. Output Current (mA) 10
TA = 85_ C
This exceeds the maximum rating and is not TA = 120_C
recommended. If operation in this region is unavoidable,
a heat sink is required. For further insight on SOA, consult
1
Application Bulletin SBOA022 (available for download at
www.ti.com). TA + [(|VS | − |VO|) IO × θ JA ] ≤ TJ (max)
θ JA = 150_C/W
TJ (max) = 125_C
0.1
100 1 2 5 10 20 50 100
TA = 25_ C |VS| − |VO| (V)

Figure 8. SO-8 (non PowerPAD) Safe Operating

Output Current (mA)

10 Area
TA = 85_C
TA = 120_ C
100

1 TA = 25_ C

TA + [(|VS | − |VO|) IO × θ JA ] ≤ TJ (max)

Output Current (mA)

θ JA = 100_C/W 10
TJ (max) = 125_C TA = 85_C
TA = 120_C
0.1
1 2 5 10 20 50 100
|VS| − |VO| (V)
1

TA + [(|VS| − |VO|) IO × θ JA] ≤ TJ (max)

Figure 6. DIP-8 Safe Operating Area
θ JA = 96_ C/W
TJ (max) = 125_C
0.1
1 10 100
|VS| − |VO| (V)

Figure 9. SO-8 PowerPAD Safe Operating Area

(no heat-spreader, no airflow)

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100 POWER DISSIPATION

1in x 0.5in, 1oz Cu TA = 25_ C Power dissipation depends on power supply, signal, and
load conditions. For dc signals, power dissipation is equal
to the product of the output current times the voltage
Output Current (mA)

TA = 85_ C
10 across the conducting output transistor, PD = IL (VS − VO).
Power dissipation can be minimized by using the lowest
TA = 120_C
possible power-supply voltage necessary to assure the
1
required output voltage swing.
For resistive loads, the maximum power dissipation occurs
TA + [(|VS| − |VO|) IO × θ JA] ≤ TJ (max)
θ JA = 52_C/W at a dc output voltage of one-half the power supply voltage.
TJ (max) = 125_ C Dissipation with ac signals is lower. Application Bulletin
0.1 SBOA022 explains how to calculate or measure
1 10 100
dissipation with unusual loads or signals.
|VS| − |VO| (V)
The OPA445 can supply output currents of 15mA and
larger. This would present no problem for a standard op
Figure 10. SO-8 PowerPAD Safe Operating Area amp operating from ±15V supplies. With high supply
(with heat-spreader, no airflow) voltages, however, internal power dissipation of the op
amp can be quite large. Operation from a single power
supply (or unbalanced power supplies) can produce even
120 larger power dissipation since a large voltage is impressed
across the conducting output transistor. Applications with
Thermal Resistance, θ JA (_ C/W)

100
No Heat−Spreader large power dissipation may require a heat-sink.
80
HEAT SINKING
60
Power dissipated in the OPA445 will cause the junction
With Heat−Spreader, 1in x 0.5in, 1oz Cu
temperature to rise. For reliable operation junction
40
temperature should be limited to 125°C, maximum (150°C
20
for TO-99 package). Some applications will require a
heat-sink to assure that the maximum operating junction
0 temperature is not exceeded. In addition, the junction
0 0.5 1.0 1.5 2.0 2.5 3.0 temperature should be kept as low as possible for
Air−Flow (meters/sec) increased reliability. Junction temperature can be
determined according to the following equation:

Figure 11. SO-8 PowerPAD Thermal Resistance T J + T A ) PD q JA (1)

(with and without heat-spreader) Package thermal resistance, qJA, is affected by mounting
techniques and environments. Poor air circulation and use
of sockets can significantly increase thermal resistance.
100 Best thermal performance is achieved by soldering the op
No Airflow amp into a circuit board with wide printed circuit traces to
Thermal Resistance, θ JA (_ C/W)

90 allow greater conduction through the op amp leads.

Simple clip-on heat sinks (such as a Thermalloy 2257) can
80
reduce the thermal resistance of the TO-99 metal package
70 by as much as 50°C/W. The SO-8 PowerPAD package will
provide lower thermal resistance, especially with a simple
60
heat-spreader—even lower with a heat-sink. For
50 additional information on determining heat-sink require-
ments, consult Application Bulletin SBOA021.
40

30
0 0.5 1.0 1.5 2.0 2.5 3.0
Copper Area (inches2)

Figure 12. Thermal Resistance vs Circuit Board

Copper Area
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PowerPAD THERMALLY-ENHANCED The PowerPAD package allows for both assembly and
PACKAGE thermal management in one manufacturing operation.
During the surface-mount solder operation (when the
In addition to the SO-8, DIP-8, and TO-99 packages, the
leads are being soldered), the thermal pad must be
OPA445 also comes in an SO-8 PowerPAD. The SO-8
soldered to a copper area underneath the package.
PowerPAD is a standard-size SO-8 package where the
Through the use of thermal paths within this copper area,
exposed leadframe on the bottom of the package can be
heat can be conducted away from the package into either
soldered directly to the PCB to create an extremely low
a ground plane or other heat-dissipating device. Soldering
thermal resistance. This architecture enhances the
the PowerPAD to the PCB is always required, even with
OPA445’s power dissipation capability significantly and
applications that have low power dissipation. Follow these
eliminates the use of bulky heatsinks and slugs
steps:
traditionally used in thermal packages. This package can
be easily mounted using standard PCB assembly 1. The PowerPAD must be connected to the most
techniques. NOTE: Since the SO-8 PowerPAD is negative supply voltage on the device, V−.
pin-compatible with standard SO-8 packages, the
2. Prepare the PCB with a top-side etch pattern. There
OPA445 can directly replace operational amplifiers in
should be etching for the leads as well as etch for the
existing sockets. Soldering the PowerPAD to the PCB is
thermal pad.
always required, even with applications that have low
power dissipation. Soldering the device to the PCB 3. Place recommended holes in the area of the thermal
provides the necessary thermal and mechanical pad. Recommended thermal land size and thermal via
connection between the leadframe die pad and the PCB. patterns for the SO-8 DDA package is shown in
Figure 14. These holes should be 13 mils in diameter.
The PowerPAD package is designed so that the leadframe
Keep them small, so that solder wicking through the
die pad (or thermal pad) is exposed on the bottom of the
holes is not a problem during reflow. The minimum
IC; see Figure 13. This design provides an extremely low
recommended number of holes for the SO-8
thermal resistance (qJC) path between the die and the
PowerPAD package is five.
exterior of the package. The thermal pad on the bottom of
the IC can then be soldered directly to the PCB, using the 4. Additional vias may be placed anywhere along the
PCB as a heatsink. In addition, plated-through holes (vias) thermal plane outside of the thermal pad area. These
provide a low thermal resistance heat flow path to the back vias help dissipate the heat generated by the OPA445
side of the PCB. IC. These additional vias may be larger than the 13-mil
diameter vias directly under the thermal pad. They can
be larger because they are not in the thermal pad area
to be soldered; thus, wicking is not a problem.
Leadframe (Copper Alloy)
IC (Silicon) Die Attach (Epoxy)
5. Connect all holes to the internal power plane of the
correct voltage potential (V−).
6. When connecting these holes to the plane, do not use
the typical web or spoke via connection methodology.
Web connections have a high thermal resistance
connection that is useful for slowing the heat transfer
during soldering operations, makeing the soldering of
Leadframe Die Pad vias that have plane connections easier. In this
Mold Compound (Plastic) Exposed at Base of the Package application, however, low thermal resistance is
(Copper Alloy)
desired for the most efficient heat transfer. Therefore,
the holes under the OPA445 PowerPAD package
should make the connections to the internal plane with
Figure 13. Section View of a PowerPAD Package
a complete connection around the entire
circumference of the plated-through hole.
GENERAL PowerPAD LAYOUT GUIDELINES
7. The top-side solder mask should leave the terminals
The OPA445 is available in a thermally-enhanced
of the package and the thermal pad area exposed.
PowerPAD package. This package is constructed using a
The bottom-side solder mask should cover the holes
downset leadframe upon which the die is mounted. This
of the thermal pad area. This masking prevents solder
arrangement results in the lead frame being exposed as a
from being pulled away from the thermal pad area
thermal pad on the underside of the package. This thermal
during the reflow process.
pad has direct thermal contact with the die; thus, excellent
thermal performance is achieved by providing a good 8. Apply solder paste to the exposed thermal pad area
thermal path away from the thermal pad. and all of the IC terminals.

12
 
""#
www.ti.com
SBOS156B − MARCH 1987 − REVISED APRIL 2008

9. With these preparatory steps in place, the PowerPAD

IC is simply placed in position and run through the Thermal Land
(Copper)
solder reflow operation as any standard surfacemount Minimum Size
O PTIONAL:
component. This preparation results in a properly 4.8mm x 3.8mm Additional four vias outside
(189 mils x 150 mils) of thermal pad area but
installed part. under the package.
For detailed information on the PowerPAD package,
including thermal modeling considerations and repair REQUIRED:
procedures, see technical brief SLMA002 PowerPAD Thermal pad area 2.286mm x 2.286mm
(90 mils x 90 mils) with five vias
Thermally-Enhanced Package available for download at
(via diameter = 13 mils)
www.ti.com.

Figure 14. 8-Pin PowerPAD PCB Etch and Via

Pattern

TYPICAL APPLICATIONS
R1 R2
100kΩ 10kΩ
V1
+60V
+40V 0.1µF

25kΩ
OPA445
0−2mA
DAC8811
R5 or
−40V 100Ω DAC7811
OPA445
V2 VO = 0V to +50V
Protects DAC
R3 R4 at 10mA
During Slewing
100kΩ 9.9kΩ 0.1µF
Load
IL
IL = [(V2 − V1)/R5] (R2 /R1)
= (V2 − V1)/1kΩ −12V
Compliance Voltage Range = ±35V

NOTE: R 1 = R3 and R2 = R4 + R5

Figure 15. Voltage-to-Current Converter Figure 16. Programmable Voltage Source

R1 R2 R3
1kΩ 9kΩ 10kΩ

R4
10kΩ

+45V +45V

160V
OPA445 OPA445 Slave
VIN Piezo(1)
±4V Master Crystal
−45V −45V

NOTE: (1) For transducers with large capacitance the stabilization

technique described in Figure 6 may be necessary. Be certain that the
Master amplifier is stable before stabilizing the Slave amplifier.

Figure 17. Bridge Circuit Doubles Voltage for Piezo Crystals

13
 PACKAGE OPTION ADDENDUM

www.ti.com 14-Sep-2023

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

OPA445ADDA ACTIVE SO PowerPAD DDA 8 75 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -55 to 125 OPA445 Samples

OPA445ADDAR ACTIVE SO PowerPAD DDA 8 2500 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -55 to 125 OPA445 Samples

OPA445AP ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 OPA445AP Samples

OPA445APG4 LIFEBUY PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 OPA445AP
OPA445AU ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-3-260C-168 HR -50 to 125 OPA Samples
445AU
OPA445AU/2K5 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-3-260C-168 HR -55 to 125 OPA Samples
445AU
OPA445AUG4 LIFEBUY SOIC D 8 75 RoHS & Green NIPDAU Level-3-260C-168 HR -55 to 125 OPA
445AU
OPA445BM LIFEBUY TO-99 LMC 8 20 RoHS & Green AU N / A for Pkg Type OPA445BM

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 14-Sep-2023

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 2-Dec-2022

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA445ADDAR SO DDA 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
PowerPAD
OPA445AU/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 2-Dec-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
OPA445ADDAR SO PowerPAD DDA 8 2500 356.0 356.0 35.0
OPA445AU/2K5 SOIC D 8 2500 356.0 356.0 35.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 2-Dec-2022

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
OPA445ADDA DDA HSOIC 8 75 506.6 8 3940 4.32
OPA445AP P PDIP 8 50 506 13.97 11230 4.32
OPA445APG4 P PDIP 8 50 506 13.97 11230 4.32
OPA445AU D SOIC 8 75 506.6 8 3940 4.32
OPA445AUG4 D SOIC 8 75 506.6 8 3940 4.32
OPA445BM LMC TO-CAN 8 20 532.13 21.59 889 NA

Pack Materials-Page 3
 GENERIC PACKAGE VIEW
DDA 8 PowerPAD TM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE

Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4202561/G
 PACKAGE OUTLINE
DDA0008J SCALE 2.400
PowerPAD TM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE

C
6.2
TYP SEATING PLANE
5.8

A PIN 1 ID
AREA 0.1 C
6X 1.27
8
1

5.0 2X
4.8 3.81
NOTE 3

4
5
0.51
8X
4.0 0.31
B 1.7 MAX
3.8 0.1 C A B
NOTE 4

0.25
TYP
0.10

SEE DETAIL A

4 5
EXPOSED
THERMAL PAD

3.1 0.25
2.5 GAGE PLANE

0.15
0 -8 1.27 0.00
1 8
0.40
DETAIL A
2.6 TYPICAL
2.0

4221637/B 03/2016
PowerPAD is a trademark of Texas Instruments.
NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MS-012, variation BA.

www.ti.com
 EXAMPLE BOARD LAYOUT
DDA0008J PowerPAD TM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE

(2.95)
NOTE 9
SOLDER MASK
(2.6) DEFINED PAD
SOLDER MASK
OPENING
8X (1.55) SEE DETAILS

1
8

8X (0.6)
(3.1)
SYMM SOLDER MASK
(1.3) OPENING
TYP (4.9)
NOTE 9

6X (1.27)

5
4

( 0.2) TYP
VIA SYMM METAL COVERED
BY SOLDER MASK

(1.3) TYP

(5.4)

LAND PATTERN EXAMPLE

SCALE:10X

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

SOLDER MASK METAL SOLDER MASK METAL UNDER

OPENING OPENING SOLDER MASK

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4221637/B 03/2016

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.

www.ti.com
 EXAMPLE STENCIL DESIGN
DDA0008J PowerPAD TM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE

(2.6)
BASED ON
0.125 THICK
STENCIL
8X (1.55)
1
8

8X (0.6)

(3.1)
SYMM
BASED ON
0.127 THICK
STENCIL

6X (1.27)

5
4

METAL COVERED SEE TABLE FOR

SYMM DIFFERENT OPENINGS
BY SOLDER MASK
FOR OTHER STENCIL
THICKNESSES
(5.4)

SOLDER PASTE EXAMPLE

EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:10X

STENCIL SOLDER STENCIL

THICKNESS OPENING
0.1 2.91 X 3.47
0.125 2.6 X 3.1 (SHOWN)
0.150 2.37 X 2.83
0.175 2.20 X 2.62

4221637/B 03/2016

NOTES: (continued)

10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.

www.ti.com
 PACKAGE OUTLINE
D0008A SCALE 2.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A PIN 1 ID AREA
6X .050
[1.27]
8
1

.189-.197 2X
[4.81-5.00] .150
NOTE 3 [3.81]

4X (0 -15 )

4
5
8X .012-.020
B .150-.157 [0.31-0.51]
.069 MAX
[3.81-3.98] .010 [0.25] C A B [1.75]
NOTE 4

.005-.010 TYP
[0.13-0.25]

4X (0 -15 )

SEE DETAIL A
.010
[0.25]

.004-.010
0 -8 [0.11-0.25]
.016-.050
[0.41-1.27] DETAIL A
(.041) TYPICAL
[1.04]

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.

www.ti.com
 EXAMPLE BOARD LAYOUT
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55]
SYMM SEE
DETAILS
1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:8X

SOLDER MASK SOLDER MASK

METAL METAL UNDER
OPENING OPENING SOLDER MASK

EXPOSED
METAL EXPOSED
METAL
.0028 MAX .0028 MIN
[0.07] [0.07]
ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55] SYMM

1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
5 [0.05]
4
6X (.050 )
[1.27]
(.213)
[5.4]

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
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