IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 20, NO.

2, MARCH 2005 405

A Multilevel Converter Topology

With Fault-Tolerant Ability
Alian Chen, Lei Hu, Lifeng Chen, Yan Deng, and Xiangning He, Senior Member, IEEE

Abstract—A new topology with fault-tolerant ability that im-

proves the reliability of multilevel converters is proposed. This
new topology is developed through analysis of different power
device’s failure modes. With the proposed scheme, the function
of the power stage can be maintained even part of it fails. Its
fault-tolerant ability results from the redundant nature of the
multiswitching-state topology and from control signal modifica-
tion. Furthermore, it balances the voltage levels automatically
without any assistance from other circuits. The validity of the
proposed scheme is confirmed by experiments in a five-level
single-phase inverter prototype.
Index Terms—Failure, fault-tolerant, multilevel converter,
reliability.

I. INTRODUCTION

M ULTILEVEL converters have become a research hotspot

in high-voltage and high-power applications because of
their many advantages, such as their low voltage stress on power
switches, low harmonic and EMI output. Many multilevel con-
verter topologies [1]–[7] have been proposed in recent years.
However, with the increase of voltage levels, failure probability
of the circuit will be increased, i.e., reliability will be decreased. Fig. 1. General multilevel converter topology proposed in [1] and [2].
To improve the reliability of multilevel converters, [8]–[11] dis-
cussed the fault-tolerant design strategies for flying capacitor flying-capacitor multilevel converters, a series of new multi-
multilevel converters and diode clamped multilevel converters. level converter topologies can be derived from it. Moreover,
The fault-tolerance in [9]–[11] is realized by scarifying some it can balance each dc voltage level automatically without
of the voltage levels, so the output voltage THD is increased. any assistance from other circuits. In this topology, there are
Reference [8] can keep the same voltage levels by reconfig- redundant switching states for output at middle levels; however
uring the flying capacitor multilevel inverter into a full binary there is only one switching state for output at highest level and
combination scheme [12] and keep capacitor voltage balance one switching state for output at lowest level. So it is possible
by using three-phase joint switching states, but the self-voltage to realize redundancy for the middle voltage levels by using
balancing can not be realized in the single-phase circuit. This redundant switching states and impossible for the highest and
paper will present a fault-tolerant multilevel inverter topology. lowest voltage levels. The modified topology proposed in this
In this topology, when a part of the circuit fails, the main func- paper provides redundancy to all voltage levels, which is real-
tion of the circuit is realized by using the inherent redundant re- ized by using a proper combination and function substitution
sources. The function of the power stage can be maintained and of switching states. This paper is organized as follows.
the self-voltage balancing can be easily realized. The proposed The first part analyzes how switching device failure impacts
topology is based on the general multilevel converter topology. on the circuit, including the device short circuit and open cir-
The general multilevel converter topology is shown in Fig. 1, cuit. The second part explains the operating principle of the
which is presented in [1] and [2] from different points of view. proposed topology with fault tolerant ability. Specifically, the
The advantages of the topology include that in addition to equivalent circuits, gate signals and neutral-point voltage self-
the existing multilevel converters such as diode-clamped and balancing are discussed in detail. In the third part, the validity
of this method is proven by experimental results in a five-level
Manuscript received November 17, 2003; revised August 4, 2004. This paper single-phase half-bridge inverter.
was presented at the IEEE APEC’04 Conference, 2004. This work was sup-
ported by the National Nature Science Foundation of China (50277035). Rec-
ommended by Associate Editor J. H. R. Enslin. II. IMPACTS OF SWITCHING DEVICE FAILURE ON CIRCUIT
The authors are with the College of Electrical Engineering, Zhejiang Univer-
sity, Hangzhou 310027, China (e-mail: hxn@zju.edu.cn). Switching device failure is often a cause of circuit dysfunc-
Digital Object Identifier 10.1109/TPEL.2004.842983 tion. Multilevel converters use a large number of switching de-
0885-8993/$20.00 © 2005 IEEE

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406 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 20, NO. 2, MARCH 2005

TABLE I
RELATIONSHIP BETWEEN OUTPUT Vo AND SWITCHING STATES UNDER
NORMAL OPERATING CONDITIONS (“1” INDICATES ON, “0” INDICATES OFF)

Fig. 2. One-leg of the general five-level converter.

vices, which affect circuit operation significantly. Many factors

can lead to power switch failure, and the disabled device can be
either short circuit or open circuit depending on different causes
and device types. A five-level half-bridge circuit (see Fig. 2)
is used to analyze the effect of switching device failure on the
circuit. In this figure, the circled switches are the main devices
used to produce a desired output voltage; the other switches are
clamping devices. Any two adjacent switching devices on each
pole are complementary, i.e., if one is ON the other is OFF and
vice versa. More detailed operating principles of the topology Fig. 3. Multilevel converter topology with fault-tolerant ability.
are shown in [2].

A. Short-Circuit Analysis
It is obvious that the source or flying capacitors will discharge
through a conducted pole switch pair as a consequence of a
power switch short failure, if no corresponding protective mea-
sures are taken in time. The counterpart of the failed switch must
be turned off quickly and properly to avoid series damages and
system collapse due to a sharp current surge.

B. Open-Circuit Analysis
When the main switching devices fail open, some switching
states and the corresponding desired voltage levels are lost.
When clamping devices fail open, the clamping ability and
some switching states are lost. From this analysis, one knows
that a device’s failure fatally impacts on the circuit operation.
In order to keep the converter functioning when the switching
device fails, it is most effective to have a redundant circuit.
The relationship between output voltage Vo and switching Fig. 4. One-leg of five-level converter with fault-tolerant ability.
states is shown in Table I. From the table it can be seen that only
one switching state is able to produce 0 Vdc, and only one is able III. MULTILEVEL CONVERTER TOPOLOGY WITH
to produce 4 Vdc. However, there are four switching states for FAULT-TOLERANT ABILITY
1 Vdc and 3 Vdc, and six switching states for 2 Vdc. When
certain switching states are invalidated due to switch failure, A. Normal Operation of the Modified Topology
the same output voltage can be obtained by using substitutive The modified multilevel converter topology with fault-tol-
switching states in the case that Vo needs 1 Vdc, 2 Vdc, and erant ability is shown in Fig. 3. To explain how it operates,
3 Vdc, however no acceptable switching state is available for a five-level converter using this topology is illustrated in
the output voltage Vo at 0 Vdc and 4 Vdc in this case. Fig. 4. Compared with the original topology, the modified

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CHEN et al.: MULTILEVEL CONVERTER TOPOLOGY 407

(a) (b)

(c)
Fig. 5. (a) Current path to produce 4 Vdc and balance capacitor voltages. (b) One of the switching states to produce 3 Vdc and balance capacitor voltages.
(c) Another of the switching states to produce 3 Vdc and balance capacitor voltages.

topology only reserves the flying capacitors that are nearest and balancing the capacitor voltages in some switching states
to the dc side and deletes other flying capacitors. Also two and used to produce desired voltage in other switching states.
additional switching pairs (Sa1/Da1 and Sa2/Da2) are added This change is caused by the deletion of some flying capacitors.
in the topology. Under normal operating conditions, the two Speaking in more detail, in the original topology, the output
switches are ON all along and have no impacts on the circuit. voltage is realized by combining all the capacitor voltages
In some failure modes, they are required to switch off to and in the modified topology the output voltage is realized by
disconnect the related branches. Their detailed function and combining the reserved capacitor voltages. So the current paths
operating principle will be given in the following part. To keep corresponding to a switching state will be changed. Although
consistency with the original topology, the devices Sp1–Sp4 fewer capacitors are needed in the modified topology, the
and Sn1–Sn4 are still called main switches and the devices self-voltage balancing ability still can be realized, which is also
Sc1–Sc12 called clamping switches. In fact, the functions of through the parallel connecting of capacitors. For example,
these switches are not completely same as their functions in the in Fig. 5(a), Sp1–Sp4 are gated on to produce 4 Vdc and the
original topology. In the original topology, the main switches circled devices are gated on to clamp and balance voltages.
are used to produce desired voltage and the clamping switches Clamping switch Sc8 is gated on so that the capacitors C1 and
are used for clamping and balancing the capacitor voltages. In C4 are connected in parallel to balance their charges. Clamping
the modified topology, the main switches are used to produce switches Sc10 and Sc12 are gated on so that the capacitors
desired voltage in some switching states and are for clamping in C2 and C5, C3 and C6 are connected in parallel, respectively.
other switching states. The clamping switches are for clamping Fig. 5(b) shows one of the switching states to produce 3 Vdc

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408 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 20, NO. 2, MARCH 2005

TABLE II
RELATIONSHIP BETWEEN OUTPUT Vo AND SWITCHING STATES WHEN MAIN
SWITCHING DEVICES FAIL OPEN (“X” INDICATES AN OPEN-CIRCUIT STATE,
“1” INDICATES ON, “0” INDICATES OFF)

B. Realization of Redundant Ability When Switching Devices

Fig. 6. Self-voltage balancing of the DC-link capacitors. Fail Open
1) Main Switching Devices Fail Open: When Vo is equal
and balance capacitor voltages. In this case, main switches to 1 Vdc, 2 Vdc, 3 Vdc, and a certain main switching device
Sp1–Sp3 and Sn4 are gated on to produce 3 Vdc. Clamping fails open, the desired output voltage can be produced by using
switches Sc7, Sc9 and Sc11 are gated on to parallel connect substitutive switching states, in which the failed device remains
capacitors C1 and C5, C2 and C6, C3 and C7 so that they are in off state. For this case, the relationship between output Vo and
charge-balanced respectively (i.e., 5, 6, the switching states is shown in Table II.
3 7). Fig. 5(c) shows another switching state to pro- When Vo is equal to 4 Vdc, in normal operating conditions,
duce 3 Vdc and balance capacitor voltages. In this case, main Sp1–Sp4 are ON and Sn1–Sn4 are OFF. If Sp1 fails open, Vo
switch Sn1and clamping switches Sc2, Sc4 and Sc8 are gated can be realized through the bold line path shown in Fig. 7(a), in
on to produce 3 Vdc. Main switch Sp4 and clamping switches which Dn1, Sc1 and Sc2 are used to replace Sp1; If Sp2 fails
Sc10 and Sc12 are gated on to parallel connect capacitors C1 open, Vo can be realized through the bold line path shown in
and C4, C2 and C5, C3 and C6 so that they are charge-balanced Fig. 7(b), in which Dc1, Sc3 and Sc4 are used to replace Sp2.
respectively (i.e., 4, 2 5, 3 6). When Vo is equal to 0 Vdc, in normal operating conditions,
In this case, the clamping devices Sc2, Sc4 and Sc8 are used Sp1–Sp4 are OFF and Sn1–Sn4 are ON. If Sn1 fails open, Vo
to produce desired voltage and the main switch Sp4 is used can be realized through the bold line path shown in Fig. 7(c), in
for capacitor voltage balancing. Other switching states can be which Dp1, Sc1 and Sc2 are used to replace Sn1; If Sn2 fails
analyzed by using the similar method. open, Vo can be realized through the bold line path shown in
From the above analysis, it can be seen that only the switches Fig. 7(d), in which Dc2, Sc5 and Sc6 are used to replace Sn2.
Sp4, SC7–SC12, and Sn4 contribute to the capacitor voltage 2) Clamping Devices Fail Open: The redundancy can also
balancing. So even if in failure modes, so long as these devices be realized by using redundant switching states when clamping
operate well, the self-voltage balancing will not be impacted. devices fail open. That is to say, when one clamping device fails
When Sp4, Sc8, Sc10 and Sc12 are ON, capacitors C1 and C4, open, the desired output voltage can be produced by changing
C2 and C5, C3 and C6 are parallel connected respectively, so switching states to keep the failed device in off state. The de-
1 4, 2 5, 3 6; When Sp4, Sc8, tailed combination is shown in Table III.
Sc10 and Sc12 are OFF, capacitors C1 and C5, C2 and C6, C3 3) Additional Devices Fail Open: When Sa1and Sa2 fail
and C7 are parallel connected respectively, so 1 5, open, 0 Vdc and 4 Vdc can still be realized. For the middle
2 6, 3 7; When these switches are from voltage levels, if the current path must include Sc3 or Sc4,
ON to OFF, the following equations can be seen: 4 5, then the corresponding switching state is invalidated when
5 6, 6 7. That is to say, each capacitor Sa1 fails open; if the current path must include Sc5 or Sc6,
can keep its voltage balance through the auxiliary capacitors then the corresponding switching state is invalidated when Sa2
C1, C2, and C3. So long as these switches can switch once in fails open. It is indicated in Table IV if the switching state is
one period, the neutral-point voltages can be balanced. Fig. 6 validated or not. The symbol Y indicates that the switching
shows the simulated waveforms of each dc-link capacitor, the state is validated and the symbol N indicates that the switching
self-voltage balancing ability is obvious. state is invalidated. It can be seen from the table that both of the
The switching rules of this modified topology are summa- cases can realize fault-tolerance if the topology is controlled
rized as follows: 1) each switch pole is an independent switching according to the validated switching states for each voltage
unit, 2) the adjacent two switches in the pole that is nearest to the level.
dc side are complementary, and 3) any two adjacent switches of
other poles should not be ON simultaneously. For convenience, C. Realization of Redundancy When Switching Devices Fail
this topology can be controlled under the same rule with the Short
original topology. That is, any two adjacent switches of each Because of the duality property between short circuits and
switch pole are complementary. So the Relationships between open circuits, it is easy to obtain redundancy when switching
output Vo and switching states in normal operating conditions devices fail short.
of the two topologies are the same, as shown in Table I. But the 1) Main Switching Devices Fail Short: When Vo is equal
number of current paths for each switching state of the modified to 1 Vdc, 2 Vdc, 3 Vdc and a certain main switching device
topology is fewer than that of the original topology. fails short, the desired output voltage can be produced by using

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CHEN et al.: MULTILEVEL CONVERTER TOPOLOGY 409

(a) (b)

(c) (d)
Fig. 7. (a) Current path to produce 4 Vdc when Sp1 fails open (the current path to produce 4 Vdc when Sn1 fails short). (b) Current path to produce 4 Vdc when
Sp2 fails open (the current path to produce 4 Vdc when Sn2 fails short). (c) Current path to produce 0 Vdc when Sn1 fails open (the current path to produce 0 Vdc
when Sp1 fails short). (d) Current path to produce 0 Vdc when Sn2 fails open (the current path to produce 0 Vdc when Sp2 fails short).

TABLE III TABLE IV

RELATIONSHIP BETWEEN OUTPUT Vo AND SWITCHING STATES WHEN RELATIONSHIP BETWEEN OUTPUT Vo AND SWITCHING STATES WHEN
CLAMPING DEVICES FAIL OPEN (“X” INDICATES AN OPEN-CIRCUIT STATE, ADDITIONAL DEVICES FAIL OPEN (“1” INDICATES ON, “0” INDICATES OFF)
“1” INDICATES ON, “0” INDICATES OFF)

substitutive switching states, in which the failed device remains forced to turn off. In this case, Vo can be realized through the
in on state. For this case, the relationship between output Vo and bold line path shown in Fig. 7(c), in which Dp1, Sc1 and Sc2 are
switching states is shown in Table V. used to replace Sn1; If Sp2 fails short, then Sn2 is forced to turn
When Vo is 0 Vdc, in normal operating conditions, Sp1–Sp4 off. Here, Vo can be realized through the bold line path shown
are OFF and Sn1–Sn4 are ON. If Sp1 fails short, then Sn1is in Fig. 7(d), in which Dc2, Sc5 and Sc6 are used to replace Sn2.

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410 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 20, NO. 2, MARCH 2005

TABLE V D. Fault-Tolerance in Multiple-Switch-Failure

RELATIONSHIP BETWEEN OUTPUT Vo AND SWITCHING STATES WHEN MAIN
SWITCHING DEVICES FAIL SHORT (“O” INDICATES A SHORT-CIRCUIT STATE, It is not very common that more than one switch fails simulta-
“1” INDICATES ON, “0” INDICATES OFF) neously. But in such case, the operation of the circuit is decided
through the different failure modes. The switching frequencies
of the additional switches Sa1 and Sa2are much lower than that
of the other switches, so the two switches can be treated as
fault-free devices in this case. Also Sp4, Sc7–Sc12, and Sn4 are
needed for the voltage balancing, so their fault will lead to the
capacitor voltage unbalancing and the circuit invalidated. When
Sp3 and Sn3 fail, it is difficult to realize 4 Vdc and 0 Vdc, and
TABLE VI
RELATIONSHIP BETWEEN OUTPUT Vo AND SWITCHING STATES WHEN
then the topology has no fault-tolerance in these cases.
CLAMPING DEVICES FAIL SHORT (“O” INDICATES A SHORT-CIRCUIT STATE, For the multiple failed devices, which are in the same pole
“1” INDICATES ON, “0” INDICATES OFF) and switch ON and OFF simultaneously, if they fail open (or
short), the switching state that keeps them OFF (or ON) can be
selected to realize the desired output voltage. And the current
paths shown in Fig. 7(a)–(d) can be used to realize 4 Vdc and
0 Vdc. So in this case, the fault-tolerance can be realized, and
devices (Sp2, Sc2), (Sc1, Sn2), (Sc3, Sc5) are included.
When the two adjacent switches in the same pole fail short, it
is impossible to realize fault-tolerance, such as (Sp1, Sn1), (Sp2,
Sc1), (Sc1, Sc2) and so on. If the clamping switches Sc1–Sc6
fail open, the fault-tolerance can be realized, and there is only
one switching state for each voltage level in this case. In other
cases, it is difficult for the topology to realize fault-tolerance.
The two pairs of additional switching devices (Sa1, Da1; Sa2,
Da2) are used for preventing the conducting devices from di-
rectly parallel connecting to capacitors (Such as Sp4, Sp3, Sp2,
(a) Sc1, Dc4, Dc8 parallel connecting to capacitors C1 and C4; Sn4,
Sn3, Sn2, Sc2, Dc5, Dc11 parallel connecting to capacitors C3
and C7). When the circuit works according to Fig. 7(a) and (b),
Sa1 is turned off and in other cases turned on. When the circuit
works according to Fig. 7(c) and (d), Sa2 is turned off and in
other cases turned on. The two switching devices do not impact
(b) the neutral point voltage balancing. For any voltage level, only
Fig. 8. (a) Carriers and modulation signal under normal operating conditions.
two pairs of additional switching devices are needed. There-
(b) Gate signals under normal operating conditions. fore, the topology is more suitable for multilevel converters with
more voltage levels.
Based on the above analysis, one can draw the conclusions
When Vo is equal to 4 Vdc, in normal operating conditions, that the devices, which are nearest to the dc side, are most im-
Sp1–Sp4 are ON and Sn1–Sn4 are OFF. If Sn1 fails short, then portant for the circuit and their failure will lead to the circuit
Sp1is forced to turn off. In this case, Vo can be realized through dysfunction. The main devices adjacent to them are also impor-
the bold line path shown in Fig. 7(a), in which Dn1, Sc1 and Sc2 tant enough; the topology’s fault-tolerance cannot be realized
are used to replace Sp1; If Sn2 fails short, then Sp2 is forced to under their failure. When other switches fail, the topology may
turn off. Here, Vo can be realized through the bold line path still work normally by rearranging the control signals. The gen-
shown in Fig. 7(b), in which Dc1, Sc3 and Sc4 are used to re- eral rules for the selection of the switching devices that should
place Sp2. be turned on or off are summarized as follows: 1) when the
2) Clamping Devices Fail Short: The redundancy can also switches fail open, another switching state in which the failed
be realized by using redundant switching states when clamping switches keep OFF will be selected, 2) when the switches fail
devices fail short. That is to say, when a certain clamping de- short, another switching state in which the failed switches keep
vice fails short, the desired output voltage can be produced by ON will be selected, and 3) the additional switches are turned
changing switching states to have the failed device ON. The de- off only when the main switches fail and the highest and lowest
tailed combination is shown in Table VI. voltage levels are produced.
Specifically, when Vo is equal to 4 Vdc and Sc1 (or Sc3) fails
short, Sa1 needs to be turned off. When Vo is equal to 0 Vdc and
E. Fault Detection
Sc2 (or Sc6) fails short, Sa2 needs to be turned off.
3) Additional Devices Fail Short: Because the additional Because there are a large number of devices in a multilevel
switches are ON all along in normal operating conditions, they converter topology, it is complex to design a fault detection cir-
will not impact the circuit operation when they fail short. cuit for each device. Many integrated commercial drive chips

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CHEN et al.: MULTILEVEL CONVERTER TOPOLOGY 411

(a) (b)

(c) (d)

(e) (f)
Fig. 9. (a) Gate signal of Sp1 and output voltage when Sp1 works from normal conditions to an open circuit. (b) Output voltage spectrum when Sp1 works under
normal conditions. (c) Output voltage spectrum when Sp1 works under open circuit. (d) Gate signals of Sp1 and Sn1 when Sp1 works from normal conditions to
an open circuit. (e) Gate signals of Sp1 and Sc1 when Sp1 works from normal conditions to an open circuit. (f) Gate signals of Sp1 and Sa1 when Sp1 works from
normal conditions to an open circuit.

have detection and protection functions, which can be used in faults of the switching devices are produced by a fault-simulated
fault detection. The method only monitoring of input and output board. The gate signals are produced by an FPGA embedded
quantities is also feasible [9], [13], [14]. board. The corresponding experimental results for short circuits
and open circuits are given below, including one main switching
device failure and one clamping device failure.
IV. EXPERIMENTAL RESULTS
Fig. 9(a)–(f) show the output voltage waveforms and related
To verify the validity of the proposed topology, a five level gate signals when Sp1 changes from normal conditions to an
single-phase half-bridge 5 KW inverter has been built in the lab- open circuit. It can be seen from Fig. 9(a) that the output voltage
oratory based on the proposed topology. The dc input voltage is continues as normal when Sp1 fails open. 4 Vdc is produced
supplied by a booster/rectifier and set to 800 V. The ac output through the path shown in Fig. 7(a). In this case, Sn1 should
frequency is set to 50 Hz. All the capacitors have the same keep ON all along and the gate signal of Sc1 should be the
capacitance of 1100 u. Sub harmonic PWM method is used. Boolean addition of gate signals of Sc1 and Sp1. Because Sp2
Switching frequency is set to 3 KHz and modulation index is set and Sc1 should conduct synchronously to produce 4 Vdc, to pre-
to 0.8. In normal operating conditions, the carriers of Sp1–Sp4, vent the conducting switching devices from parallel connecting
modulation signal and gate signals are shown in Fig. 8. The to capacitors C1 and C4 directly, Sa1 should be in off state and

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412 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 20, NO. 2, MARCH 2005

(a) (b)

(c) (d)

(e)
Fig. 10. (a) Gate signal of Sc3 and output voltage when Sc3 works from normal conditions to an open circuit. (b) Output voltage spectrum when Sc3 works under
normal conditions. (c) Output voltage spectrum when Sc3 works under open circuit. (d) Gate signals of Sc3 and Sp4 when Sc3 works from normal conditions to
an open circuit. (e) Gate signals of Sc3 and Sp3 when Sc3 works from normal conditions to an open circuit.

in other cases be in on state. So the gate signal of Sa1 is the to be changed are shown in Fig. 11(d)–(g), other gate signals are
opposite of Sp1. The gate signals that need to be changed are unchanged.
shown in Fig. 9(d)–(f), other gate signals are unchanged. Fig. 12(a)–(h) are the output voltage waveforms and related
Fig. 10(a)––(e) are the output voltage waveforms and related gate signals when Sc1 works from normal conditions to a short
gate signals when Sc3 works from normal conditions to an open circuit. After Sc1 fails short, change the switching state combi-
circuit. After Sc3 fails open, the gate signals of Sp3 and Sp4 nation to keep Sc1 in on state. The gate signals of Sp1 and Sp2
are interchanged to keep Sp3 in on state except when producing are interchanged to keep Sp2 in off state except when producing
0 Vdc. The gate signals of Sp3 and Sp4 are shown in Fig. 10(d) 4 Vdc. In this case, the gate signals that need to be changed are
and (e), other gate signals are unchanged. shown in Fig. 12(d)–(h), other gate signals are unchanged.
Fig. 11(a)–(g) are the output voltage waveforms and related It can be seen from the above experimental results and
gate signals when Sp2 works from normal conditions to a short analysis that when one switching device fails open or short, the
circuit. After Sp2 fails short, changing the switching state com- desired output voltage still can be achieved by using substitu-
bination to keep Sp2 in on state. In this case, Sn2 is kept in off tive switching states to replace the disabled ones. Therefore,
state, which is equal to the open state of Sn2. 0 Vdc is produced the topology has fault-tolerant ability and the reliability is
by the circuit path shown in Fig. 7(d). The gate signals that need improved.

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CHEN et al.: MULTILEVEL CONVERTER TOPOLOGY 413

(a) (b)

(c) (d)

(e) (f)

(g)

Fig. 11. (a) Gate signal of Sp2 and output voltage when Sp2 works from normal conditions to a short circuit. (b) Output voltage spectrum when Sp2 works under
normal conditions. (c) Output voltage spectrum when Sp2 works under short circuit. (d) Gate signals of Sp2 and Sp4 when Sp2 works from normal conditions to
a short circuit. (e) Gate signals of Sp2 and Sn2 when Sp2 works from normal conditions to a short circuit. (f) Gate signals of Sp2 and Sc6 when Sp2 works from
normal conditions to a short circuit. (g) Gate signals of Sp2 and Sa2 when Sp2 works from normal conditions to a short circuit.

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414 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 20, NO. 2, MARCH 2005

(a) (b)

(c) (d)

(e) (f)

(g) (h)

Fig. 12. (a) Gate signal of Sc1 and output voltage when Sc1 works from normal conditions to a short circuit. (b) Output voltage spectrum when Sc1 works under
normal conditions. (c) Output voltage spectrum when Sc1 works under short circuit. (d) Gate signals of Sc1 and Sn1 when Sc1 works from normal conditions to
a short circuit. (e) Gate signals of Sc1 and Sa1 when Sc1 works from normal conditions to a short circuit. (f) Gate signals of Sc1 and Sn2 when Sc1 works from
normal conditions to a short circuit. (g) Gate signals of Sc1 and Sp1 when Sc1 works from normal conditions to a short circuit. (h) Gate signals of Sc1 and Sp2
when Sc1 works from normal conditions to a short circuit.

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CHEN et al.: MULTILEVEL CONVERTER TOPOLOGY 415

V. CONCLUSION Lei Hu was born in Hunan, China, in 1977. He re-

ceived the B.Sc. and M.Sc. degrees from Zhejiang
A multilevel converter topology with fault-tolerant ability is University, Hangzhou, China, in 1999 and 2002, re-
proposed in this paper. The output voltage can be maintained at spectively, where he is currently pursuing the Ph.D.
degree in power electronics.
power device’s failure by using a redundant equivalent circuit His research interests are power electronics and
and control mode modification. This modified topology uses their industrial applications.
fewer capacitors than the original topology, and balances the
voltage levels automatically. It is more suitable for converters
with more voltage levels and a high reliability requirement. The
validity has been proven through experimental results in a five
level single-phase inverter.
Lifeng Chen was born in Zhejiang, China, in 1979.
REFERENCES He received the B.Sc. degree from Zhejiang Univer-
[1] H. Y. Wu, “Multilevel Conversion Techniques and Control Methods,” sity, Hangzhou, China, in 2002 where he is currently
Ph.D. dissertation, Zhejiang Univ., Hangzhou, China, 2001. pursuing the M.S. degree in power electronics.
[2] F. Z. Peng, “A generalized multilevel inverter topology with self voltage His research interests are power electronics and
balancing,” IEEE Trans. Ind. Applicat., vol. 37, no. 2, pp. 611–618, their industrial applications.
Mar./Apr. 2001.
[3] Y. S. Kim et al., “A novel structure of multilevel high voltage source
inverter,” in Proc. IEEE TENCON’93 Conf., Beijing, China, Oct. 19–21,
1993, pp. 503–508.
[4] X. M. Yuan et al., “A new diode clamping multilevel inverter,” in Proc.
IEEE PESC’99 Conf., Charleston, SC, Jun. 27–Jul. 1 1999, pp. 495–501.
[5] N. S. Choi et al., “A general circuit topology of multilevel inverter,”
in Proc. IEEE PESC’91 Conf., Cambridge, MA, Jun. 24–27, 1991, pp.
96–103. Yan Deng was born in Sichuan, China, in 1973.
[6] F. Z. Peng, J. S. Lai, and J. McKeever et al., “A multilevel voltage source He received the B.E.E. degree and the Ph.D. de-
converter system with balanced dc voltages,” in Proc. IEEE PESC’95 gree in power electronics and electric drives from
Conf., Atlanta, GA, Jun. 18–22, 1995, pp. 1144–1150. Zhejiang University, Hangzhou, China, in 1994 and
[7] J. S. Lai and F. Z. Peng, “Multilevel converters—a new breed of power 2000, respectively.
converters,” IEEE Trans. Ind. Applicat., vol. 32, no. 3, pp. 509–517, He has been a Faculty Member, Teacher, and has
May/Jun. 1996. conducted research on power electronics in the same
[8] X. Kou, K. A. Corzine, and Y. Familiant, “A unique fault-tolerant de- college since 2000. He is now an Associate Professor
sign for flying capacitor multilevel inverters,” in Proc. IEEE IEMDC’03 with more than 20 papers published in international
Conf., Jun. 1–4, 2003, pp. 531–538. and domestic conferences/transactions. His research
[9] C. Turpin, P. Baudesson, F. Richardeau, F. Forest, and T. A. Meynard, interests are topologies and control for switch mode
“Fault management of multicell converters,” IEEE Trans. Ind. Electron., power conversion.
vol. 49, no. 5, pp. 988–997, Oct. 2002.
[10] F. Richardeau, P. Baudesson, and T. Meynard, “Failures-tolerance
and remedial strategies of a PWM multicell inverter,” in Proc. IEEE
PESC’00 Conf., Galway, Ireland, Jun. 18–23, 2000, pp. 649–654.
[11] B. Francois and J. P. Hautier, “Design of a fault tolerant control system Xiangning He (M’95–SM’96) received the B.Sc.
for a N.P.C. multilevel inverter,” in Proc. IEEE ISIE’02 Conf., Jul. 8–11, and M.Sc. degrees from Nanjing University of Aero-
2002, pp. 1075–1080. nautical and Astronautical, Nanjing, China, in 1982
[12] X. Kou, K. A. Corzine, and Y. Familiant, “Full binary combination and 1985, respectively, and the Ph.D. degree from
schema for floating voltage source multi-level inverters,” IEEE Trans. Zhejiang University, Hangzhou, China, in 1989.
Power Electron., vol. 17, no. 6, pp. 891–897, Nov. 2002. From 1985 to 1986, he was an Assistant Engineer
[13] A. C. Renfrew and J. X. Tian, “The use of a knowledge-based system at the 608 Institute of Aeronautical Industrial General
in power electronic circuit diagnosis,” in Proc. EPE’93 Conf., Brighton, Company, China. From 1989 to 1991, he was a Lec-
UK, Sep. 13–16, pp. 57–62. turer at Zhejiang University. In 1991, he obtained a
[14] W. G. Fenton, T. M. McGinnity, and L. P. Maguire, “Fault diagnosis of Fellowship from the Royal Society of U.K., and con-
electronic systems using intelligent techniques: a review,” IEEE Trans. ducted research in the Department of Computing and
Syst., Man, Cybern., vol. 31, no. 3, pp. 269–281, May 2001. Electrical Engineering, Heriot-Watt University, Edinburgh, U.K., as a Post-Doc-
toral Research Fellow for two years. In 1994, he joined Zhejiang University as
an Associate Professor. Since 1996, he has been a Full Professor in the Col-
lege of Electrical Engineering, Zhejiang University. He presently also the Head
Alian Chen was born in Shandong, China, in 1976. of the Department of Applied Electronics and the Director of the Power Elec-
She received the B.Sc. and M. Sc. degrees from Shan- tronics Research Institute, Zhejiang University. His research interests are power
dong University, China, in 1998, and 2000, respec- electronics and their industrial applications. He holds eight Chinese patents.
tively, and is currently pursuing the Ph.D. degree in Dr. He received the 1989 Excellent Ph.D. Graduate Award, the 1995 Elite
power electronics at Zhejiang University, Hangzhou, Prize Excellence Award, the 1996 Outstanding Young Staff Member Award
China. from Zhejiang University for his teaching and research contributions, three Sci-
Her research interests are power electronics and entific and Technological Progress Awards (two in 1998 and one in 2002) from
their industrial applications. Zhejiang Provincial Government and the State Educational Ministry of China,
respectively, and four Excellent Paper Awards. He is a Fellow of the Institution
of Electrical Engineers (IEE), U.K.

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