7480 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 31, NO.

11, NOVEMBER 2016

A Fault-Tolerant Strategy Based on Fundamental

Phase-Shift Compensation for Three-Phase
Multilevel Converters With Quasi-Z-Source
Networks With Discontinuous Input Current
Mohsen Aleenejad, Hamid Mahmoudi, and Reza Ahmadi, Member, IEEE

Abstract—This paper proposes a new fault-tolerant strategy for flexible means of power conversion between the source and load
a multilevel converter with an integrated impedance-source net- in a very wide range of power conversion applications [9], [10].
work. The proposed fault-tolerant strategy leverages the flexibility
Numerous power conversion topologies incorporating differ-
provided by the impedance-source network to implement the fun-
damental phase-shift compensation (FPSC) method in order to ent types of impedance-source networks have been proposed
restore operation of a multilevel converter with one or more faulty in the literature recently [11]–[14]. Among them, the multi-
switches to the prefault conditions. In case of a fault occurrence, the level converters incorporating Z-source networks (ZSI) [9], [15],
proposed fault-tolerant strategy makes the most use of the remain- quasi-Z-Source networks (qZSI) [16], [17], or qZSI with discon-
ing converter capacity and generates balanced line-to-line voltages, tinuous input current networks (qZSId) [18], [19] are of utmost
while evenly distributing an inevitable voltage stress increase, over
all converter switches. In this paper, first, a brief background about importance for scholars in the area of high-power conversion.
an impedance-source based cascaded H-bridge converter and a These topologies provide an excellent opportunity to marry the
suitable modulation method for it is provided. Then, the FPSC benefits of the multilevel converters with the flexibility pro-
method is explained and the proposed fault-tolerant strategy based vided by the impedance-source networks to achieve the best of
on this method is introduced. Finally, several experimental results both worlds: lower THD, higher efficiency, and lower switching
from a prototype converter are provided to validate the operation
of the proposed strategy. stress [20] combined with a wide range of ac output that can
be lower or higher than the input voltage [21]. In particular, the
Index Terms—Fault-tolerant strategy, fundamental phase-shift Z-source networks can be easily fused with cascaded H-bridge
compensation, impedance-source multilevel converter, multilevel
converter, Z-source CHB.
(CHB) converters to relieve the voltage gain requirements for
H-bridge modules in a CHB [4], [19], [22], [23]. This combina-
I. INTRODUCTION
tion provides single-stage energy conversion with higher equiva-
HE medium-to-high-voltage industrial settings involving lent output pulse width modulation (PWM) frequency [15], [24],
T electric energy conversion demand for safe, reliable, and
efficient power electronic stages [1]. This has fostered a myriad
[25] while featuring an excellent boost function [26]. Therefore,
higher inversion efficiency can be achieved while reducing the
of research and development activities in the areas of high- size of the output filter and the number of H-bridge modules re-
power/high-voltage energy conversion and high-power elec- quired to match the output voltage generated by a conventional
tronics through the past decade [2], [3]. Two of the prominent CHB [22]. The reduced number of H-bridge cells makes the
technologies developed recently to facilitate high-power conver- system less expensive, less complex, and more reliable [27].
sion are multilevel converters and impedance-source networks Despite the improvements provided by multilevel converters,
for power electronic converters [4], [5]. Multilevel converters since the number of power electronic switches in a multilevel
are becoming increasingly popular in industrial apparatus aimed converter topology is higher than that of a conventional inverter,
at medium-to-high-power conversion applications. Compared to the chances of fault occurrence on the switches is higher, and
conventional inverters, they feature superior characteristics such thus, the converter’s reliability is relatively lower compared to
as lower total harmonic distortion (THD), higher efficiency, and conventional inverters [28], [29]. High reliability for power con-
lower switching voltage stress [6]–[8]. The impedance-source verters in commercial and industrial applications is critical due
networks overcome several limitations of the conventional to extreme monetary ramifications of interruption of operation.
voltage/current source inverters and provide an efficient and As a result, developing fault-tolerant operation schemes for mul-
tilevel converters has always been a topic of great interest for
Manuscript received October 04, 2015; revised December 08, 2015; ac- researchers in the related areas [30]–[33]. Several fault-tolerant
cepted January 07, 2016. Date of publication January 21, 2016; date of cur- operation schemes for multilevel converters have been recently
rent version June 24, 2016. Recommended for publication by Associate Editor proposed in the literature; however, almost all of these tech-
G. Baoming.
The authors are with the Department of Electrical and Computer Engineering, niques can be classified into two main categories: techniques
Southern Illinois University Carbondale, Carbondale, IL 62901 USA (e-mail: that modify the converter hardware topology after fault diagno-
ahmadi@siu.edu; mohsen@siu.edu; hamid@siu.edu). sis [34], [35] and techniques that modify the converter control
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org. algorithm, particularly the modulation method, after fault diag-
Digital Object Identifier 10.1109/TPEL.2016.2520884 nosis [36].

0885-8993 © 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications standards/publications/rights/index.html for more information.
ALEENEJAD et al.: FAULT-TOLERANT STRATEGY BASED ON FPSC FOR THREE-PHASE MULTILEVEL CONVERTERS WITH QUASI-Z-SOURCE 7481

Although several valuable fault-tolerant strategies for

multilevel converters have been developed by researchers, the
development of fault-tolerant strategies that are applicable to
multilevel inverters with impedance-source networks is not a
very well explored area [37], [38]. Few works concerned with
fault-tolerant operation of impedance-source-based inverters
are only concerned with conventional two-level ZSIs [39], [40].
The authors of this paper believe that the inherent boosting
characteristic of a Z-source network, if leveraged properly,
provides a viable countermeasure to compensate for the adverse
effects of a faulty switch in a multilevel converter.
The purpose of this paper is to propose a new fault-tolerant
strategy for postfault operation of an impedance-source multi-
level converter with one or more faulty switches. The proposed
fault-tolerant strategy generates balanced line-to-line voltages
without bypassing any healthy converter elements, makes better
use of the converter capacity, and generates ac output voltages
with no amplitude reduction in the event of a fault. The proposed
Fig. 1. Three-phase n-level qZSId-CHB converter with m series connected
strategy exploits the advantages of the boosting capability of the H-bridge cells in each phase.
Z-source network in conjunction with a slightly modified fun-
damental phase-shift compensation (FPSC) technique [41] to
generate balanced voltages with the same amplitude as the volt- Nonshoot-through operating modes and shoot-through operat-
ages during the normal operation. In case of a fault occurrence ing modes. When a qZSd cell is in a nonshoot-through mode,
on a switch, the proposed strategy increases the voltage gain it operates similar to a conventional H-bridge cell while also
of the remaining healthy H-bridge cells to compensate for the boosting the input voltage to its H-bridge stage to [18]
negative effects of bypassing a faulty cell while revising the
phase shifts between the phase voltages to achieve balanced 1
Vdc = B × Vin = × Vin (1)
line-to-line voltages, all while keeping the voltage stress of the 1 − 2D
healthy switches at the minimum possible value. The proposed where D is the shoot-through duty ratio, B is the boost factor of
strategy is applicable to any impedance-source CHB converter the qZSId network, Vin is the input voltage to the qZSId cell,
with three or more voltage levels. and Vdc is the input voltage to the H-bridge stage of the qZSId
cell (see Fig. 1). When a qZSId cell is in a shoot-through mode,
II. GROUNDWORK the input terminal to the H-bridge stage is short circuited,
A. Converter Topology rendering the value of Vdc to zero.
In a shoot-through mode, the output terminal voltage of the
CHB multilevel converters feature modular structure, sim- qZSId cell is always equal to zero. However, in a nonshoot-
ple physical layout, and numerous redundant switching states through mode, the output terminal voltage can be equal to Vdc ,
[20]. Therefore, CHB converters are excellent topologies for de- 0, or −Vdc based on the status of conduction of the switches in
signing fault-tolerant inversion stages. Various voltage-fed ZSI the H-bridge stage. Therefore, due to the series connection of
configurations such as the traditional ZSI, qZSI, and qZSId [42] m qZSId cells in each phase of the qZSId-CHB converter, the
can be readily combined with the CHB topology to enhance following n voltage levels can be generated by each phase of the
its fault-tolerant properties. In this work, a qZSId network is converter: −mVdc , . . . , −Vdc , 0, Vdc , . . . , mVdc [20].
integrated into the traditional CHB converter topology to as-
semble a fault-tolerant CHB converter with a very high degree
of flexibility. The qZSId network is especially selected due to B. Modulation Method
the lower voltage rating requirement for its capacitors compared A large variety of modulation methods for multilevel con-
to the traditional ZSI network [19]. Nevertheless, the proposed verters have been discussed in the literature throughout the
fault-tolerant strategy can be applied to a CHB converter with last decade [43], [44]. Several of these methods can be em-
any of the mentioned Z-source networks. ployed to control the proposed qZSId-CHB converter [21], [45].
Fig. 1 illustrates the circuit diagram of the n-level qZSId- However, a certain carrier-based PWM method, called phase-
based CHB converter, referred to as the qZSId-CHB converter shifted PWM [43], is very well suited to implement the pro-
hereinafter. As pictured, the proposed qZSId-CHB converter posed fault-tolerant strategy in this paper [34]. For the purpose
places a qZSId network on the input side of each standard of this work, the PS-PWM method is modified slightly to gen-
H-bridge cell. These modified H-bridge cells are referred to erate shoot-through switching states in addition to traditional
as qZSId cells hereinafter. Each phase of the qZSId-CHB nonshoot-through states. Fig. 2 illustrates the switching logic of
converter is made up of m qZSId cells (n = 2m + 1). The the modified PS-PWM technique for one of the qZSId cells in
qZSId cells exhibit two distinct categories of operating modes: the qZSId-CHB converter.
7482 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 31, NO. 11, NOVEMBER 2016

shoot-through states. However, increasing the shoot-through

leads to an increase in the output voltage of the ZSI circuitry (the
Vdc in Fig. 1) [10]. This dc-link voltage is the voltage stress that
the inverter switches need to tolerate. Therefore, when increas-
ing the amplitude of the generated voltages using shoot-through
states, it is essential to ensure that the amplitude of the dc-
link voltage does not exceed the stress rating of the switches
[38]. Additionally, increasing the dc-link voltage results in a
significant increase in the current of the inductors in a ZSI net-
work [18]. As such, for any operating point, it is desirable to
minimize the dc-link voltage and achieve the required output
voltage level by increasing the modulation index rather than the
shoot-through.
In the qZSId cell of Fig. 1, the dc-link voltage is equal to
BVin , and the upper limit of the dc-link voltage is the voltage
stress rating of the H-bridge switches (VBN )
BVin ≤ VBN . (3)
Therefore, the maximum boost factor allowed is equal to
VBN /Vin . As a result, the maximum allowed shoot-through is
equal to
   
VBN 2VBN
Dm ax = −1 . (4)
Vin Vin
Fig. 2. Phasor diagram of phase voltages in a qZSId-CHB converter. This gives a hard upper limit on the amount of shoot-through
(a) Healthy operation. (b) Faulty condition in which the faulty cell is bypassed
and the line-to-line voltages are unbalanced. (c) Phase angles are modified ac- that the proposed method can generate.
cording to the FPSC strategy to generate balanced line-to-line voltages with less To minimize the dc-link voltage for any inverter voltage gain
voltage reduction. (d) Voltage gain is modified by changing the shoot-through (G), the amount of shoot-through needs to be minimized, while
ratio to compensate for the line-to-line voltage reduction in the postfault condi-
tion. the modulation index is maximized. The modulation index (M)
is always greater than zero and less than (1 – D). To maximize
the modulation index and to minimize the shoot-through ratio,
The traditional PS-PWM uses two carrier signals with 180° the shoot-through ratio must be equal to 1 – M. According
phase shift for each H-bridge cell in a CHB converter (ci and ci to the formulations for a qZSId circuit [18]
in [14, Fig. 6]) [19]. The relative phase angle of carrier signals 1
for each phase of the converter depends on the number of H- G = Bm in × Mm ax = × (1 − Dm in ). (5)
1 − 2Dm in
bridge cells in each phase [14]
⎧ By careful inspection of (5), one can realize the minimized
⎨ θci = (i − 1) × 360 shoot-through is
2m , i = 1, 2, 3, . . . , m. (2)
⎩ G−1
θc  i = θci + 180 Dm in = (6)
2G − 1
A sinusoidal reference signal (mj ) is compared with the two while the maximized modulation index will be equal to
carrier signals associated with each H-bridge cell in a converter
phase and the switching signals for the H-bridge switches are Mm ax = 1 − Dm in . (7)
generated accordingly. To generate the shoot-through states us- The results in (6) and (7) will be used as the basis for balancing
ing the modified PS-PWM technique, a new shoot-trough signal the shoot-thorough versus modulation index by the proposed
with amplitude of 1 – D is introduced to the switching logic. This method whenever necessary.
new signal is represented as a cyan line in [14, Fig. 6]. Also, the
switching logic is modified so that whenever the carrier signal III. FAULT-TOLERANT STRATEGY
is smaller than the shoot-through signal, the H-bridge stage in
The problem of detecting a fault, finding the location, and then
the corresponding qZSId cell is short circuited by its switches.
taking appropriate action is the basis of fault-tolerant control.
The generated shoot-through states are depicted as shaded areas
Fortunately, many fault detection methods have been proposed
in [14, Fig. 6].
over the last few years [46]. However, the main challenge in this
paper is limited to take appropriate action after fault diagnosis.
C. Minimizing Voltage Stress on Switches
In this paper, it is assumed that the type and location of the fault
In a typical ZSC inverter, the amplitude of the generated has been detected by the proposed method in [46]. In this sec-
voltages can be increased by increasing the duration of the tion, a fault-tolerant strategy for a qZSId-CHB converter based
ALEENEJAD et al.: FAULT-TOLERANT STRATEGY BASED ON FPSC FOR THREE-PHASE MULTILEVEL CONVERTERS WITH QUASI-Z-SOURCE 7483

on FPSC technique is proposed. The proposed fault-tolerant strategy employs the FPSC technique to evenly distribute the
strategy combines the voltage gain flexibility provided by the rise of voltage stress between all of the inverter switches.
qZSId-cells with the phase-shifting property of the FPSC tech- The conventional FPSC technique is discussed in [41]. The
nique to fully recover the converter operation upon occurrence FPSC technique modifies the phase angles of the inverter
of single or multiple faults on inverter switches. The proposed phase voltages (θab , θb c , θca in Fig. 2) to generate balanced
fault-tolerant strategy works in two stages to compensate for the line-to-line voltages. Fig. 2(c) demonstrates how modifying
faulty switches in the inverter. The first stage involves bypass- the phase angles of inverter voltages can lead to balanced
ing the faulty cells, while the second stage involves applying the line-to-line voltages for a seven-level qZSId-CHB converter
FPSC technique to recover the amplitude and balance the phase with one bypassed faulty cell. According to this figure, although
angles of the inverter voltages. the amplitudes of the phase voltages (Vb , Vc ) are not equal,
In case there are one or more faulty switches in a qZSId-CHB by properly adjusting the phase angles (θab , θb c , θca ), the
converter, based on the fault type and the location of the faulty amplitudes of the line-to-line voltages (Vab , Vb c , Vca ) are made
switches, the faulty qZSId-cells fail to generate all of the pre- all equal (4.6 p.u.). The phase angles that result in balanced
viously mentioned feasible output terminal voltage levels in a line-to-line voltages can be found by solving the following set
nonshoot-through mode (Vdc , 0, −Vdc ). As a result, the inverter of equations for θab , θb c , and θca [41]
phases with faulty cells can no longer generate phase voltages ⎧ 2
⎪ V + Vb2 − 2Va Vb cos(θab )
that are symmetric around the zero-volt level. Therefore, the ⎪ a
⎪
⎪
⎪ = Vb2 + Vc2 − 2Vb Vc cos(θb c )
faulty phases of the inverter start generating unbalanced phase ⎪
⎨
voltages that contain dc offset components. In its first stage Vb2 + Vc2 − 2Vb Vc cos(θb c ) (8)
of operation, the proposed method bypasses all of the faulty ⎪
⎪
⎪
⎪ = Vc + Va − 2Vc Va cos(θca )
2 2
qZSId-cells to prevent generation of the dc offset by making ⎪
⎪
⎩
the phase voltages symmetric around zero-volt level. However, θab + θb c + θca = 360◦
in this condition, the amplitude of the voltages generated by
where θab , θb c , and θca are the modified phase shifts between
all three phases of the converter is no longer equal. The phases
phase voltages and Va , Vb , and Vc are the amplitude of the phase
with bypassed cells can no longer generate all of the voltage lev-
voltages after bypassing the faulty cells. For instance, in case
els, and thus, the amplitude of the voltages generated by these
of the previously mentioned seven-level qZSId-CHB converter
phases will be less than that of the healthy phases. For instance,
with one bypassed cell (assuming the bypassed phases is phase
in a seven-level qZSId-CHB converter with one faulty cell, the
“a”), substituting Va = 2 p.u. and Vb = Vc = 3 p.u. in (8) yields
healthy phases can generate voltages with a maximum ampli-
θab , = θca = 130.5◦ and θba = 99◦ . Therefore, for generating
tude of 3Vdc (3 p.u.), while the faulty phase can only generate a
balanced line-to-line voltages, the phase shifts between phase
voltage with a maximum amplitude of 2Vdc (2 p.u.). This leads
voltages should be adjusted according to the obtained values.
to generation of unbalanced inverter line-to-line voltages. The
The phase angles of the inverter phase voltages can be easily
phasor diagram of Fig. 2(a) and (b) elaborates on the opera-
adjusted in PS-PWM through adjusting the phase angles of the
tion of a seven-level converter before and after occurrence of a
sinusoidal reference signals (mj in [14, Fig. 6]).
fault. According to Fig. 2(b), after bypassing the faulty phase,
Although by applying the FPSC technique to a qZSId-CHB
the amplitude of Vb c is equal to 5.19 p.u., while the ampli-
converter with faulty cells, balanced line-to-line voltages can
tude of Vab and Vca is equal to 4.35 p.u. To fully recover the
be generated, however, the converter operation is not fully re-
converter operation, the line-to-line voltages need to be both bal-
covered because the amplitudes of the generated line-to-line
anced and have the same amplitude as the voltages in a healthy
voltages are less than those of a healthy converter. In the seven-
inverter.
level qZSId-CHB converter of above, for instance, according to
To balance and increase the voltage amplitudes to the prefault
Fig. 2(a), the amplitude of the line-to-line voltages before fault
condition, it is easy to come up with the simple idea of increasing
occurrence is equal to 5.19 p.u.; however, after application of
the voltage gain of the faulty phases by increasing their asso-
the FPSC, the amplitude of the line-to-line voltages is reduced
ciated shoot-through levels. However, this simple idea comes
to 4.6 p.u. The proposed method in this work leverages the flex-
with two major drawbacks: by increasing the shoot-through in
ibility provided by the shoot-through states in a qZSId circuit
the faulty phases, the voltage stress on all of remaining healthy
to fully recover the amplitude of the line-to-line voltages to
switches in the faulty phases increases significantly, leading to
their prefault condition. To recover the line-to-line voltages, the
a higher possibility of a subsequent fault in the already faulty
proposed method increases the postfault inverter voltage gain
phases; additionally, the current of the inductors on all remaining
(Gfault ) to
healthy cells in the faulty phase increases considerably as well.
In the previously mentioned seven-level qZSId-CHB converter Gpre -fault
Gfault = (9)
with one faulty cell, to fully recover the converter operation KG
by increasing the shoot-through of the faulty phase, the voltage where Gpre -fault is the inverter voltage gain before fault occur-
gain of the faulty phase will be increased for a 1.5 factor result- rence and KG is a performance reduction factor found from
ing to a considerable increase in voltage stress over the healthy
switches in this phase. As a result, rather than only increasing |VLL |fault
KG = . (10)
the shoot-through of the faulty cells, the proposed fault-tolerant |VLL |pre -fault
7484 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 31, NO. 11, NOVEMBER 2016

In (10), |VLL |fault and |VLL |pre -fault are the amplitudes of
the line-to-line voltages of the inverter post- and prefault con-
ditions, respectively. For the seven-level qZSId-CHB converter
of above, |VLL |pre -fault = 5.19 p.u. and |VLL |fault = 4.6 p.u.
which results in a performance reduction factor of KG = 0.885.
According to (9), this means that the inverter voltage gain should
be increased by a factor of KG−1 = 1.129 after applying the
FPSC in order to fully recover the inverter operation. The re-
sulting phasor diagram for this postfault condition is shown in
Fig. 2(d). Comparing Fig. 2(a) with Fig. 2(d) clearly demon-
strates that in the postfault condition, by applying the proposed
method, despite having unbalanced phase voltages, the inverter
line-to-line voltages are fully recovered to their prefault condi- Fig. 3. Prototype three-phase seven-level qZSId-CHB converter and 12-V
batteries.
tion. It is worth mentioning that typically the correct line-to-line
voltages fully satisfy the requirements of the load and result in
uninterrupted operation of the inverter system. on the inverter switches increases for only 20% in this condition.
As mentioned in Section II, for any operating point of the This greatly reduces the possibility of a subsequent fault in the
inverter, the shoot-through (and thus the voltage stress of the already faulty inverter.
switches) should be minimized while modulation index is max-
imized. The minimum shoot-through that will result in the re-
IV. EXPERIMENTAL RESULTS
quired postfault gain (Gfault ) can be found from (6)
Gfault − 1 This section provides experimental results generated through
Dfault,m in = (11) utilizing the proposed fault-tolerant strategy to restore the op-
2Gfault − 1
eration of a prototype seven-level qZSId-CHB converter to the
while the modulation index in this condition can be calculated prefault conditions, in case of three different fault scenarios.
from (7) The experimental setup is shown in Fig. 3.
In this setup, the input side of each Z-Source network is
Mfault,m ax = 1 − Dfault,m in . (12)
connected to a 12-V battery and the output side is connected
Finally, the value of Dfault,m in from (11) is compared to the to the dc-link terminal of each H-bridge cell. The power semi-
upper limit Dm ax in (4) to make sure the switches will not get conductor devices used in this prototype are power MOSFETs
damaged in the postfault condition. As long as the Dfault,m in with drain-to-source voltage rating of 100 V (VBN = 100). The
is found to be less than Dm ax , the proposed method can fully Z-source components are C1 = C2 = 2200 μF, and L1 = L2
recover the converter operation regardless of the type and place = 500 μH. The output terminals of the qZSId-CHB converter
of the faults. are connected to a three-phase inductive load with a 0.9 power
As mentioned earlier, one advantage of the proposed method factor assembled using a 7-Ω resistor in series with a 1.2-mH
is that rather than only increasing the shoot-through of the faulty inductor in each phase. The proposed method was implemented
cells and thus increasing the voltage stress of the switches con- using the TMS320F28335 digital signal processor. In the
siderably in the faulty phases, it evenly increases the voltage operating point used for generating the results (Vload = 44 V,
stress on all inverter switches for a small amount. In the pre- Iload = 6 A), in order to minimize the voltage stress on the
viously mentioned seven-level qZSId-CHB converter with one switches, the modulation index and the shoot-through ratio are
faulty cell, to fully recover the converter operation by only in- set to 0.85 and 0.15, respectively. By substituting these values
creasing the shoot-through of the faulty phase, the voltage gain in (5), the voltage gain in normal operation (GPre -fault ) is found
of two remaining cells must be increased by a 1.5 factor. As- as 1.21. The fundamental and switching frequencies of the
suming the converter is operating with M = 0.85 and D = 0.15, PS-PWM method are 50 Hz, and 2 kHz, respectively. The phase
using (1) and (5), the boost factor and the voltage gain in normal voltages, line-to-line voltages, load voltages, and the dc-link
operation are found as B = 1.42 and G = 1.21. As mentioned, voltage of one H-bridge cell of the inverter for the prefault
after fault occurrence, the voltage gain on remaining cells needs condition are shown in Fig. 4. According to Fig. 4, in this
to be increased to Gfault = 1.5 × 1.21 = 1.82, which results in operating point, the amplitudes of phase voltages, line-to-line
Dfault = 0.31 and Bfault = 2.64. Therefore, the voltage stress voltages, load voltages, and the dc-link voltage of each H-bridge
on the switches in the faulty phase is increased for a factor of cell are equal to 44, 76, 44, and 17 V, respectively. The THD of
Bfault /B = 1.85. In the other words, the voltage stress on the the load voltages in this condition is calculated as 9.5%.
switches in the faulty phase increases for 85%, but it remains The first experiment analyzes the occurrence of a single fault
the same for the switches in the healthy phases. In contrast, in phase “b.” In this case, the faulty cell is bypassed at the first
using the proposed fault-tolerant strategy, the voltage gain of step. Therefore, the number of operative cells in phase “b” is
all of the healthy cells of the inverter increases by a factor reduced to two cells (Vb = 2 p.u., Va = Vc = 3 p.u.). In this
KG−1 = 1.129. Following the same calculations as before using condition, to generate balanced line-to-line voltages, based on
1.129 for voltage gain, it can be concluded that the voltage stress (8), the phase shifts between the inverter phase voltages need to
ALEENEJAD et al.: FAULT-TOLERANT STRATEGY BASED ON FPSC FOR THREE-PHASE MULTILEVEL CONVERTERS WITH QUASI-Z-SOURCE 7485

Fig. 4. qZSId-CHB’s voltages in normal operating condition. (a) Inverter’s

phase voltages. (b) Line-to-line voltages. (c) Load voltages. (d) DC-link voltage
of one H-Bridge cell (the voltage across H-Bridge’s switches).

be adjusted to θb c = θab = 130.5◦ . The performance reduction

factor (KG ) and the voltage gain in the faulty condition (Gfault )
in this experiment are calculated from (9) and (10) as 0.885 and
1.37, respectively. Subsequently, the new modulation index and
shoot-through ratio that compensate the loss of one operative cell
in phase “b,” while keeping the voltage stress across the switches
at minimum can be calculated from (6). These parameters
(M and D) are found to be equal to 0.78 and 0.22, respec-
tively. The calculated shoot-through ratio is checked against
the maximum applicable shoot-through ratio found from (4) as
Dm ax = 0.44 to make sure the voltage stress will not exceed
the limitations of the switches as a result of implementing the
proposed fault-tolerant strategy. The new values of M and D
along with the adjusted phase shifts are used by the PS-PWM
algorithm to generate modified switching commands to restore
the operation of the converter to the prefault conditions.
The generated phase voltages of the converter during the nor-
mal operation (t ≤ t0 ), the fault recovery period (t0 ≤ t ≤ t1 ),
and the postfault operation (t ≥ t1 ) are shown in Fig. 5(a). Due
to the inferior quality of the waveforms in this scope shot,
the actual raw data from the oscilloscope were exported to
MATLAB to generate Fig. 5(a). As pictured in Fig. 5(a), during
the normal operation (t ≤ t0 ), the phase voltages reach all seven
levels; however, during the fault recovery period (t0 ≤ t ≤ t1 )
and upon bypassing the faulty cell in phase “b,” this phase only
generates five voltage levels. In this condition, the amplitude of
the phase “b” voltage is equal to 35.1 V, while the amplitude of
the voltages in the healthy phases “a” and “c” are equal to 52.55
and 52.6 V, respectively.
According to the readings provided in Fig. 5(a) for the
waveforms in the postfault condition, the phase shifts between
the waveforms are accurately adjusted to the intended values
of θb c = θab = α = 130.5◦ by the proposed strategy. To verify
Fig. 5. qZSId-CHB voltages in the event of a faulty switch in phase “b” (first
generation of balanced line-to-line voltages, the raw data experiment). (a) Inverter’s phase voltages. (b) Line-to-line voltages. (c) Load
from Fig. 5(b) were imported to MATLAB to plot Fig. 5(b). voltages. (d) DC-link voltage of one H-bridge cell. (e) Harmonic spectrum of
According to this figure, the amplitudes of the line-to-line the load voltages. (f) Load currents.
7486 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 31, NO. 11, NOVEMBER 2016

voltages are all equal to 76.5 V, and the phase shifts between
these voltages are also all equal to 120°. This confirms the
validity of the proposed fault-tolerant strategy for generating
balanced line-to-line voltages in the event of a bypassed
faulty H-bridge. The waveforms plotted in Fig. 5(c) confirm
generation of balanced load voltages in the postfault condition
as well. Fig. 5(d) shows the dc-link voltage of one of the
H-bridge power cells during this experiment. According to this
figure, the value of the dc-link voltages is increased for only
3.5 V in the postfault condition. The harmonic spectrums of the
load voltage for the postfault condition is shown in Fig. 5(e).
The THDs of the load voltages are calculated using the data
imported from the oscilloscope as 10%, 11%, and 10% for the
Van , Vbn , and Vcn , respectively. This shows a negligible increase
of THD in the postfault condition. Finally, the load currents
in the event of a single faulty phase are given in Fig. 5(f). As it
can be seen, the amplitude of the current in the postfault oper-
ation of the inverter is equal to the amplitude of this current in
normal operation of the inverter. However, the THD of the cur-
rent is slightly increased in the postfault operation. The current
THD is increased from 2.9% to 3.3% due to fault occurrence.
The second experiment analyzes the case of two faulty
switches: one in phase “b” and another one in phase “c.” In this
condition, the phase shifts of the inverter phase voltages need
to be adjusted to θab = θca = α = 101.5◦ . To emulate the fault
condition, one switch in phase “b” and another one in phase “c”
were manually short circuited at t = t0 . The faulty H-bridge cells
were bypassed, and the fault-tolerant strategy was triggered at t
= t1 . The generated voltage waveforms for this experiment are
shown in Fig. 6. According to Fig. 6(a), in the fault recovery pe-
riod, the amplitude of the phase “a” voltage is equal to 60.58 V,
while the amplitudes of the voltages in the other two phases are
reduced to 41.1 and 41.2 V. Similar to before, upon triggering
the proposed fault-tolerant strategy, the phase shifts between the
waveforms are accurately adjusted to θab = θca = α = 101.5◦ .
Consequently, balanced line-to-line voltages with equal ampli-
tudes of 76 V and phase shift of 120° were generated. The THDs
of load voltage are calculated in this experiment as 11%, 12%,
and 12% for the Van , Vbn , and Vcn , respectively. The third ex-
periment analyzes the occurrence of multiple faults in one phase
of the converter. In this experiment, two switches in phase “b”
are manually short circuited to emulate the fault condition. In
this case, the phase shifts of the inverter phase voltages need
to be adjusted to θab = θb c = α = 140◦ . Similar to the previ-
ous experiments, the fault-tolerant strategy bypasses the faulty
cells and modifies the phase angles and shoot-through ratio to
generate balanced line-to-line voltages. The generated voltage
waveforms for this experiment are shown in Fig. 7.

V. CONCLUSION
In this paper, a new fault-tolerant strategy for improving the
performance of a qZSId-CHB converter under faulty condi-
tion was proposed. Using the proposed method, only the faulty
Fig. 6. qZSId-CHB voltages in the event of a faulty switch in phase “b” and
qZSId cell was bypassed and the remaining healthy cells were another faulty switch in phase “c” (second experiment). (a) Inverter’s phase
remained operative to use the maximum capacity of the con- voltages. (b) Line-to-line voltages. (c) Load voltages. (d) Harmonic spectrum
verter. By adopting the FPSC method, instead of just increasing of the load voltages. (f) Load currents.
7486 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 31, NO. 11, NOVEMBER 2016

voltages are all equal to 76.5 V, and the phase shifts between
these voltages are also all equal to 120°. This confirms the
validity of the proposed fault-tolerant strategy for generating
balanced line-to-line voltages in the event of a bypassed
faulty H-bridge. The waveforms plotted in Fig. 5(c) confirm
generation of balanced load voltages in the postfault condition
as well. Fig. 5(d) shows the dc-link voltage of one of the
H-bridge power cells during this experiment. According to this
figure, the value of the dc-link voltages is increased for only
3.5 V in the postfault condition. The harmonic spectrums of the
load voltage for the postfault condition is shown in Fig. 5(e).
The THDs of the load voltages are calculated using the data
imported from the oscilloscope as 10%, 11%, and 10% for the
Van , Vbn , and Vcn , respectively. This shows a negligible increase
of THD in the postfault condition. Finally, the load currents
in the event of a single faulty phase are given in Fig. 5(f). As it
can be seen, the amplitude of the current in the postfault oper-
ation of the inverter is equal to the amplitude of this current in
normal operation of the inverter. However, the THD of the cur-
rent is slightly increased in the postfault operation. The current
THD is increased from 2.9% to 3.3% due to fault occurrence.
The second experiment analyzes the case of two faulty
switches: one in phase “b” and another one in phase “c.” In this
condition, the phase shifts of the inverter phase voltages need
to be adjusted to θab = θca = α = 101.5◦ . To emulate the fault
condition, one switch in phase “b” and another one in phase “c”
were manually short circuited at t = t0 . The faulty H-bridge cells
were bypassed, and the fault-tolerant strategy was triggered at t
= t1 . The generated voltage waveforms for this experiment are
shown in Fig. 6. According to Fig. 6(a), in the fault recovery pe-
riod, the amplitude of the phase “a” voltage is equal to 60.58 V,
while the amplitudes of the voltages in the other two phases are
reduced to 41.1 and 41.2 V. Similar to before, upon triggering
the proposed fault-tolerant strategy, the phase shifts between the
waveforms are accurately adjusted to θab = θca = α = 101.5◦ .
Consequently, balanced line-to-line voltages with equal ampli-
tudes of 76 V and phase shift of 120° were generated. The THDs
of load voltage are calculated in this experiment as 11%, 12%,
and 12% for the Van , Vbn , and Vcn , respectively. The third ex-
periment analyzes the occurrence of multiple faults in one phase
of the converter. In this experiment, two switches in phase “b”
are manually short circuited to emulate the fault condition. In
this case, the phase shifts of the inverter phase voltages need
to be adjusted to θab = θb c = α = 140◦ . Similar to the previ-
ous experiments, the fault-tolerant strategy bypasses the faulty
cells and modifies the phase angles and shoot-through ratio to
generate balanced line-to-line voltages. The generated voltage
waveforms for this experiment are shown in Fig. 7.

V. CONCLUSION
In this paper, a new fault-tolerant strategy for improving the
performance of a qZSId-CHB converter under faulty condi-
tion was proposed. Using the proposed method, only the faulty
Fig. 6. qZSId-CHB voltages in the event of a faulty switch in phase “b” and
qZSId cell was bypassed and the remaining healthy cells were another faulty switch in phase “c” (second experiment). (a) Inverter’s phase
remained operative to use the maximum capacity of the con- voltages. (b) Line-to-line voltages. (c) Load voltages. (d) Harmonic spectrum
verter. By adopting the FPSC method, instead of just increasing of the load voltages. (f) Load currents.
7488 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 31, NO. 11, NOVEMBER 2016

[20] M. Aleenejad, H. Mahmoudi, P. Moamaei, and R. Ahmadi, “A new fault- [41] P. Lezana and G. Ortiz, “Extended operation of cascade multicell con-
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with DC-link ripple feedforward compensation for multilevel inverters,” verters,” IEEE Trans. Power Electron., vol. 29, no. 4, pp. 2098–2108,
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[25] N. Davoudzadeh, M. Tafazoli, and M. Sayeh, “On linearity of all optical [46] W. Tianzhen, X. Hao, H. Jingang, E. Elbouchikhi, and M. E. H. Benbouzid,
asynchronous binary delta–sigma modulator,” Opt. Commun., vol. 308, “Cascaded H-bridge multilevel inverter system fault diagnosis using a
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[26] L. Yushan, G. Baoming, and H. Abu-Rub, “Modelling and controller Power Electron., vol. 30, no. 12, pp. 7006–7018, Dec. 2015.
design of quasi-Z-source cascaded multilevel inverter-based three-phase
grid-tie photovoltaic power system,” IET Renewable Power Generation,
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[27] M. Aleenejad, H. Iman-Eini, and S. Farhangi, “Modified space vector
modulation for fault-tolerant operation of multilevel cascaded H-bridge
inverters,” IET Power Electron., vol. 6, pp. 742–751, 2013. Mohsen Aleenejad received the B.S. degree from the
[28] K. Nguyen-Duy, L. Tian-Hua, C. Der-Fa, and J. Y. Hung, “Improvement AmirKabir University of Technology, Tehran, Iran,
of matrix converter drive reliability by online fault detection and a fault- in 2010, and the M.S. degree from the University of
tolerant switching strategy,” IEEE Trans. Ind. Electron., vol. 59, no. 1, Tehran, Tehran, Iran, in 2013, both in electrical engi-
pp. 244–256, Jan. 2012. neering. He is currently working toward the Ph.D. de-
[29] S. Yantao and W. Bingsen, “Survey on reliability of power electronic gree in electrical and computer engineering at South-
systems,” IEEE Trans. Power Electron., vol. 28, no. 1, pp. 591–604, ern Illinois University, Carbondale, IL, USA.
Jan. 2013. His research interests include power electronics
[30] M. Mingyao, H. Lei, C. Alian, and H. Xiangning, “Reconfiguration of circuits, multilevel converters, and their applications
carrier-based modulation strategy for fault tolerant multilevel inverters,” in power grid and system, electric-drive vehicles, and
IEEE Trans. Power Electron., vol. 22, no. 5, pp. 2050–2060, Sep. 2007. solar energy systems.
[31] M. A. Parker, R. Li, and S. J. Finney, “Distributed control of a fault-tolerant
modular multilevel inverter for direct-drive wind turbine grid interfacing,”
IEEE Trans. Ind. Electron., vol. 60, no. 2, pp. 509–522, Feb. 2013.
[32] L. Jun, A. Q. Huang, L. Zhigang, and S. Bhattacharya, “Analysis and
design of active NPC (ANPC) inverters for fault-tolerant operation of
high-power electrical drives,” IEEE Trans. Power Electron., vol. 27,
no. 2, pp. 519–533, Feb. 2012. Hamid Mahmoudi was born in 1989. He received
[33] M. Aleenejad, P. Moamaei, H. Mahmoudi, and R. Ahmadi, “Unbalanced the B.Sc. degree in electrical engineering from the
selective harmonic elimination for fault-tolerant operation of three phase Noshirvani University of Technology, Mazandaran,
multilevel cascaded H-bridge inverters,” in Proc. IEEE Appl. Power Elec- Iran, in 2011, and the M.Sc. degree in electrical en-
tron. Conf. Expo., 2015, pp. 1589–1594. gineering from the Iran University of Science and
[34] B. Mirafzal, “Survey of fault-tolerance techniques for three-phase voltage Technology, Tehran, Iran, in 2014. He is currently
source inverters,” IEEE Trans. Ind. Electron., vol. 61, no. 10, pp. 5192– working toward the Ph.D. degree in electrical engi-
5202, Oct. 2014. neering at Southern Illinois University, Carbondale,
[35] E. C. dos Santos and S. Sajadian, “Fault-tolerant DC-AC converter with IL, USA.
split-wound coupled inductors,” in Proc. Brazilian Power Electron. Conf., His research interests include power electronics,
2013, pp. 30–35. digital control, and motor drives.
[36] M. Aleenejad, H. Mahmoudi, and R. Ahmadi, “A modified space vector
modulation method for fault-tolerant operation of multilevel converters,”
IEEE Trans. Power Electron., 2015. to be published.
[37] E. Gao, P. C. Loh, D. M. Vilathgamuwa, and F. Blaabjerg, “Performance
evaluation of three-level z-source inverters under semiconductor failure
conditions,” in Proc. 22nd Annu. IEEE Appl. Power Electron. Conf., 2007,
pp. 626–632. Reza Ahmadi (M’09) received the B.S. degree in
[38] G. Feng, L. P. Chiang, F. Blaabjerg, and D. M. Vilathgamuwa, “Perfor- electrical engineering from the Iran University of
mance evaluation of three-level z-source inverters under semiconductor- Science and Technology, Tehran, Iran, in 2009, and
failure conditions,” IEEE Trans. Ind. Appl., vol. 45, no. 3, pp. 971–981, the Ph.D. degree in electrical engineering from the
May/Jun. 2009. Missouri University of Science and Technology,
[39] A. Cordeiro, J. Palma, J. Maia, and M. Resende, “Fault-tolerant design of a Rolla, MO, USA, in 2013.
classical voltage-source inverter using z-source and standby redundancy,” He is currently an Assistant Professor of electrical
in Proc. 11th Int. Conf.Elect. Power Quality Utilisation, 2011, pp. 1–6. and computer engineering at Southern Illinois Uni-
[40] E. S. Najmi, M. Heydari, M. Mohamadian, and S. M. Dehghan, “Z-source versity, Carbondale, IL, USA. His research interests
three-phase four-switch inverter with DC link split capacitor and com- include modeling, design, and control of power elec-
prehensive investigation of z-source three-phase four-switch inverters,” in tronic converters, electric-drive vehicles, and solar
Proc. 3rd Power Electron. Drive Syst. Technol., 2012, pp. 25–31. energy systems.