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Optimized floating point arithmetic unit

Conference Paper · February 2015

DOI: 10.1109/INDICON.2014.7030552

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 2014 Annual IEEE India Conference (INDICON)

Optimized Floating Point Arithmetic Unit

Prateek Singh Kalyani Bhole

Instrumentation and Control Department Instrumentation and Control Department
College of Engineering College of Engineering
Pune, India 411005 Pune, India 411005
Email: singhp13.instru@coep.ac.in Email: kab.instru@coep.ac.in

Abstract—Arithmetic circuits plays an important role in (LNS) is simpler because it requires simple addition for
digital systems. Realization of complex digital circuits is possible multiplication and subtraction for division. [4]
with development in very large scale integration (VLSI) circuit
technology. In this paper an arithmetic unit based on IEEE-754 We have implemented arithmetic unit that are specially
standard for floating point numbers has been implemented on designed to carry out operations on floating point numbers. De-
Spartan3E XC3S500e FPGA Board. Here Floating Point Unit mand of more accuracy and resolution lead digital arithmatic
(FPU) follows IEEE single precision format. Various arithmetic development towards floating point operations.Complexity in-
operations such as, addition, subtraction multiplication and crease has given birth to software library routines (ip cores).
division on floating point numbers have been performed on
arithmetic unit. Novel approach of converting fixed to floating The IEEE 754 Floating point standard provides for many
point saves around 30% of slices and can perform 50 Mega closely related formats, differing in only a few details, like
floating point operations per second on Spartan 3E FPGA at
50 MHz clock. Arithmetic operations using proposed conversion
single precision, single precision, single extended. The single
optimize space and speed requirements. precision format includes 32 bits, contains 1 sign bit, 8 bits
for exponential and 23 bits wide mantissa. [5] Generally
Keywords: FPGA; floating point numbers; verilog; IEEE represented as follows:
754
1 8 23
sign exponent mantissa
I. I NTRODUCTION
Digital processors and application specific systems are
made up of group of digital arithmetic operations. Realization The value of representation is obtained from the equation.
of complex digital circuits is possible with development in very
large scale integration (VLSI) circuit technology.Conventional In this paper the operands are 32 bit wide, to choose
computer arithmetic methods as well as non conventional ones which operation to be performed op register gives information,
need floating point arithmetics.In the past,floating point were similarly for rounding modes rmode is used to provide infor-
usually implemented via coprocessor rather than an integrated mation that which mode among the four to be used. Standard
unit and in microcomputer era a single microchip are used. rounding mode is round to nearest. Here we use status signals
to represent the operation they are overflow, underflow, inexact,
exception and invalid.

II. FIXED TO FLOATING POINT CONVERSION

Fig. 1. Fixed to floating point conversion
Fixed to floating point conversion is an essential step in
In [1], a space efficient division on FPGAs is imple- floating point arithmetics.To optimize resources and execution
mented and implementation issues are discussed. Division time,fixed to floating point conversion is implemented using
algorithms are discussed in the context of implementing im- logic gates.Digital relation between fixed point exponent and
age processing algorithms on FPGAs.Compared Handel C, number of shift required,saves execution time and its imple-
Restoring and Non-restoring algorithms.Found non-restoring mentation in terms of logic gates saves resources.
division algorithm as faster than other two.Used Spartan-II
and Virtex-II board. Implementation of high speed fixed point
TABLE I. SHOWS RELATION BETWEEN FIXED POINT EXPONENT AND
dividers on FPGA [2] Implementation of fixed point division NUMBER OF SHIFTS
modules based on following algorithms using xilinxs FPGA.
a b c d e f g h x y z
Restoring digit algorithm Non-restoring digit algorithm SRT 0 0 0 0 0 0 0 1 0 0 0
algorithmNon-restoring algorithm is faster and smaller than 0 0 0 0 0 0 1 x 0 0 1
32 bit IP core from Xilinx. A Comparison of Floating Point 0 0 0 0 0 1 x x 0 1 0
and Logarithmic Number Systems on FPGAs [3]. The use 0 0 0 0 1 x x x 0 1 1
0 0 0 1 x x x x 1 0 0
of the logarithmic number system (LNS) as an alternative to 0 0 1 x x x x x 1 0 1
floating point (FP) because of simpler multiplication, division 0 1 x x x x x x 1 1 0
and exponentiation computations.Logarithmic number system 1 x x x x x x x 1 1 1

978-1-4799-5364-6/14/$31.00 ©2014 IEEE

Fig. 2. Gate level implementation part-I

Fig. 4. Gate level implementation part-III

Figure. 2,3,4 shows gate level implementation of fixed

to floating point conversion.
• An example is given further to demonstrate the basic
Fig. 3. Gate level implementation part-II steps for adding/subtracting two FP numbers.
• Take two 5-digits binary FP numbers:
III. IMPLEMENTATION OF FLOATING POINT UNIT
24 × 1.1001 + 22 × 1.0010
Three stages of all arithmetic operations are- pre-normalize
stage,arithmetic core and post-normalize stage. In pre- normal- (a) Get the number with the larger exponent and
ize stage the operands are converted into formats so that they subtract it from the smaller exponent.
can be handled easily and efficiently.In arithmetic core basic
arithmetic operations are done.Lastly in post normalize stage eL = 24 , eS = 22
the result is normalized and converted into format specified by
so
IEEE standard. [6]
diff = 4 − 2 = 2
A. Addition and Subtraction
(b) Shift the fraction with the smaller exponent
Floating point addition and subtraction algorithms consist difference positions to the right. We can now
of five stages- leave out the exponent since they are both
equal.
• Firstly difference between exponent is to be calcu-
lated, difference d = e1 − e2 . If e1 < e2 then 1.1001000 + 0.0100100
d = e2 − e 1 .
(c) Add both fractions
• In second stage pre-alignment of mantissas is achieved
by shifting smaller mantissa right by d bits.
1.1001000 + 0.0100100 = 1.1101100
• In third stage addition or subtraction of mantissa is
done to get tentative result for mantissa. (d) Round-to-nearest-even

• Then normalization is done.If there are leading-zeros 1.1110

in tentative result,result is shifted to left and exponent
is decreased by number of leading zeros.If overflows (e) Result
then result is shifted right and exponent increased by
1 bit. 24 × 1.1110

• Last stage is rounding. • Algorithm is shown in figure 5

 OperandA = signA & eA & fracA
OperandB = signB & eB & fracB

eA > eB
eL = e A eL = e B
es = e B es = e A
fracL = fracA fracL = fracB
fracs = fracB fracs = fracA

Diff= eL - e0
didiff

Shift Right fracs diff bits

frac0 = frac s +\- fracL

e0= eL

Round frac0

Exception Fig. 6. gate level implementation of multiplication algorithm.

occurred ?

Yes
Normalize Signal exception C. Division
No
The division is multiple subtraction of numbers and thus
Output=sign0 & e0 & frac0
division algorithm is implemented. Algorithm is implemented
such that it optimize between area and speed.The five stages
of division algorithm are counting leading zeros,shifting
Fig. 5. algorithm of addition and subtraction
left,division,rounding and normalization.In division algorithm
one stage is division so it is prime important to select such
B. Multiplication algorithm which optimize between area and speed.

In IEEE 754 floating point multiplication, the two mantis- • Count leading zeros in both floating point numbers.
sas are multiplied and two exponents are added .To implement
• Shift left fractional bits of both floating point numbers
sign logic simply XOR gate is realized.Floating point multi-
according to number of zeros.
plication algorithm is realized as follows: [7]
• Divide the fractional bits. Sign of result is calculated
• Addition of exponents and then subtract bias. from xoring sign of two operand.
• Multiply the mantissas and determine the sign of • Exponent of result is calculated by equation:
result.
e0 = eA eB + bias(127) − ZA + ZB
• Normalize the resulting value.
• Rounding occurs in floating point multiplication when • Round the fraction and normalize it if required.
the mantissa of the product is reduced by half. • To demonstrate the basic steps of division, lets say we
• The multiplication algorithm takes 3 steps. To demon- want to divide two 5-digits FP numbers:
strate the basic steps, take two 5- digits FP numbers
to multiply: 2110 ∗ 1.000/2100 ∗ 0.0011
(2100 × 1.1001) × (2110 × 1.0010)
(a) Count leading zeros in both fractions.
(a) Multiply fractions and calculate the result ex-
ponent. ZA = 0, ZB = 3
1.1001 × 1.0010 = 1.11000010
(b) Shift-left the fractions according to ZA , ZB .
so f rac0 = 1.11000010 Calculate the result exponent
and
e0 = 2100+110−bias = 283 f racA = 1000000000
(b) Round the fraction to nearest-even
f racB = 0000011000
f rac0 = 1.1100
(c) Result = 283 × 1.1100 e0 = 2110−100+bias−0+3 = 2140
• Algorithm implementation is shown in figure 6 (c) Divide both fractions
 Mega floating point operations per second on Spartan 3E
FPGA at 50 MHz clock whereas division algorithm executes
100000.0000/000001.1000 = 1.0101 at the speed of 2.03 Mega floating point operations per second
(e) Result = 1.0101 × 2140 on Spartan 3E FPGA at 50 MHz clock.

• Algorithm implementation is shown in figure 7 R EFERENCES

[1] D. G. Bailey, “Space efficient division on fpgas,” in Electronics New
Zealand Conference (EnzCon’06), 2006, pp. 206–211.
[2] N. Sorokin, “Implementation of high-speed fixed-point dividers on fpga,”
Journal of Computer Science & Technology, vol. 6, 2006.
[3] M. Haselman, M. Beauchamp, A. Wood, S. Hauck, K. Underwood,
and K. S. Hemmert, “A comparison of floating point and logarithmic
number systems for fpgas,” in Field-Programmable Custom Computing
Machines, 2005. FCCM 2005. 13th Annual IEEE Symposium on. IEEE,
2005, pp. 181–190.
[4] R. Goldberg, G. Even, and P.-M. Seidel, “An fpga implementation
of pipelined multiplicative division with ieee rounding,” in Field-
Programmable Custom Computing Machines, 2007. FCCM 2007. 15th
Annual IEEE Symposium on. IEEE, 2007, pp. 185–196.
[5] M. D. Ercegovac and R. McIlhenny, “Design and fpga implementation
of radix-10 algorithm for division with limited precision primitives,” in
Signals, Systems and Computers, 2008 42nd Asilomar Conference on.
IEEE, 2008, pp. 762–766.
[6] G. Lienhart, A. Kugel, and R. Manner, “Using floating-point arith-
metic on fpgas to accelerate scientific n-body simulations,” in Field-
Programmable Custom Computing Machines, 2002. Proceedings. 10th
Annual IEEE Symposium on. IEEE, 2002, pp. 182–191.
[7] X. Fang and M. Leeser, “Vendor agnostic, high performance, double
Fig. 7. gate level implementation of division algorithm.. precision floating point division for fpgas,” in High Performance Extreme
Computing Conference (HPEC), 2013 IEEE. IEEE, 2013, pp. 1–5.

IV. IMPLEMENTATION RESULTS AND

DISCUSSION
TABLE II. C OMPARISION
SLICES LUTS

Conventional 362 119

IP Core (XILINX) 151 222

IP Core (ZIP Core) 79 301

Proposed 45 78

Table II shows comparison of implementation of fixed to

floating point conversion with conventional method,Xilinx ip
core,Xilinx zip core.This novel approach saves around 30slices
and can perform 50 Mega floating point operations per second
on Spartan 3E FPGA at 50 MHz clock.
TABLE III. R ESOURCE UTILIZATION
SLICES LUTS

Addition 118 210

Substraction 118 210

Multiplication 60 107

Division 167 301

Table III shows resource utilization of floating point op-

erations,addition,subtraction,multiplication,division.Addition
n,subtraction,multiplication can perform at the speed of 25

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