FAST HUB FLOATING-POINT ADDER FOR FPGA

ABSTRACT:

IEEE Standard 754 floating point is the most common representation today for real
numbers on computers. Because of the complexity of the algorithms, floating point operations are very
hard to implement on FPGA. In this paper, we present a HUB floating-point adder for FPGA which
greatly improves the speed of previous proposed HUB designs for these devices. Our
architecture is based on the double path technique which reduces the execution time since each
path works in parallel. We also deal with the implementation of unbiased rounding in the
proposed adder. Experimental results are presented showing the goodness of the new HUB adder
for FPGA Spartan 3 XC3S 200 TQ-144. This Proposed System Implemented using Verilog HDL
and Simulated by Modelsim Tool and Synthesized by Xilinx tool.

OBJECTIVE:

This architecture is based on the double path technique which reduces the execution time since
each path works in parallel. We also deal with the implementation of unbiased rounding in the
proposed adder.

MOTIVATION:

A HUB floating-point adder for FPGA which greatly improves the speed of previous proposed
HUB designs for these devices.

INTRODUCTION:
The computations for floating point operations involve large dynamic range, but the
resources required for this operations is high compared with the integer operations. We have
unsigned/signed multiplier for multiplication of binary numbers, for multiplication of floating
point numbers floating point multiplier is used. There is a separate algorithm for this
multiplication. Floating point numbers are one possible way of representing real numbers in
binary format; the IEEE 754 standard presents two different floating point formats, Binary
interchange format and Decimal interchange format. Multiplying floating point numbers is a
critical requirement for DSP applications involving large dynamic range.

When specific Floating-Point (FP) is needed for some applications, Field-Programmable

Gate Array (FPGA) design allows meeting the required features. Thus, nowadays many systems
are not implemented in ASIC but using FPGAs. Traditionally FPGA implementations use fixed-
point arithmetic mainly because many of the Digital Signal Processing (DSP) applications
tolerate error precision providing low-cost implementation at the same time. However, in the last
years a fast growth of floating-point implementations and studies. There are more DSP
applications implementing complex algorithms which require extended dynamic range and
higher precision. The drawback is that the implied implementations on FPGA are costlier than
their fixed-point counterparts. However, there are some promising researches proposing designs
of adders and multipliers (key units on most DSP applications) which use other format than the
IEEE-754 standard for binary floating point with lower cost. Specifically the implementations
on FPGA of an adder and multiplier are having simultaneously less area and delay (compared to
Conventional implementations). HUB is the acronym of Half-Unit-Biased format and it is based
on shifting the standard numbers by half unit in the last place (ULP). Some of its important
features are that the two’s complement is carried out by bit-wise inversion, the round to- nearest
is performed by simple truncation, and requires the same number of bits for storage as its
conventional counterpart for the same precision.

Unsigned Multiplier:

A parallel-input parallel-output circuit (also known as array multiplier) that performs the
operations depicted is shown in below figure. The circuit is combinational because its output
depends only on its current inputs. As expected, it employs an array of AND gates plus full-
adder units. Indeed, this unsigned multiplier is useful in the multiplication of mantissa part of
floating point numbers.

FLOATING POINT MULTIPLIER:

This multiplier is mainly used to multiply two floating point numbers. Separate algorithm is
essential for multiplication of these numbers. Here multiplication operation is simple than
addition this is especially true if we are using a 32- bit format and 64-bit format.

FLOATING POINT FORMAT:

One of the ways to represent real numbers in binary is the floating point formats. There
are two different formats for the IEEE 754 standard. Binary interchange format and Decimal
interchange format. In the multiplication of floating point numbers involves a large dynamic
range which is useful in DSP applications. This paper concentrates only on single precision
normalized binary interchange format. The below figure shows the IEEE 754 single precision
binary format representation; consisting of a one bit sign (S), an eight bit exponent (E), and a
twenty three bit fraction (M or Mantissa).

The term floating point refers to the fact that the radix point (decimal point, or, more commonly
in computers, binary point) can "float"; that is, it can be placed anywhere relative to the
significant digits of the number. This position is indicated separately in the internal
representation, and floating-point representation can thus be thought of as a computer realization
of scientific notation. Over the years, a variety of floating-point representations have been used
in computers. However, since the 1990s, the most commonly encountered representation is that
defined by the IEEE 754 Standard.
The advantage of floating-point representation over fixed-point and integer representation is that
it can support a much wider range of values. For example, a fixed-point representation that has
seven decimal digits with two decimal places can represent the numbers 12345.67, 123.45, 1.23
and so on, whereas a floating-point representation (such as the IEEE 754 decimal32 format) with
seven decimal digits could in addition represent 1.234567, 123456.7, 0.00001234567,
1234567000000000, and so on. The floating-point format needs slightly more storage (to encode
the position of the radix point), so when stored in the same space, floating-point numbers achieve
their greater range at the expense of precision.

LITERATURE SURVEY:

Title: HUB floating point for improving FPGA implementations of DSP applications

Authors: J. Hormigo and J. Villalba

Publication: IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 64, no. 3, pp.
319–323

Year: Mar 2017

In this brief, we investigate the advantages of using half-unit biased (HUB) formats to
implement these FP applications on field-programmable gate arrays (FPGAs). These new FP
formats allow for the effective elimination of the rounding logic on FP arithmetic units. First, we
experimentally show that HUB and standard formats provide equivalent signal-to-noise ratio on
DSP application implementations. We then present a detailed study of the improvement achieved
when implementing FP adders and multipliers on FPGAs by using HUB numbers. In most of the
cases studied, the HUB approach reduces resource use and increases the speed of these FP units
while always providing statistically equivalent accuracy as that of conventional formats.

Drawbacks:

 More Area
 Less Accuracy
Title: Higher radix floating-point representations for FPGA-based arithmetic

Authors: B. Catanzaro and B. Nelson

Publication: 13th IEEE Symposium on Field- Programmable Custom Computing Machines

(FCCM’05)

Year: 2005

Field Programmable Gate Arrays (FPGAs) are increasingly being used for high-
throughput floating-point computation. It is forecasted that by 2009, FPGAs will provide an
order of magnitude greater sustained floating-point throughput than conventional processors.
FPGA implementations of floating-point operators have historically been designed to use binary
floating-point representations, as do general purpose processors. Binary representations were
chosen as the standard over three decades ago because they provide maximal numerical accuracy
per bit of floating point data. However, the unique nature of FPGA-based computation makes
numerical accuracy per unit of FPGA resources a more important measure of the usefulness of a
given floating-point representation.

Drawbacks:

 High-cost
 Complex Multiplier Design

Title: Floating point FPGA: Architecture and modeling

Authors: C. H. Ho, C. W. Yu, P. Leong, W. Luk, and S. J. E. Wilton

Publication: IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 17, no. 12, pp.
1709–1718

Year: Jan 2009

 This paper presents architecture for a reconfigurable device that is specifically optimized
for floating-point applications. Fine-grained units are used for implementing control logic and
bit-oriented operations, while parameterized and reconfigurable word-based coarse-grained units
incorporating word-oriented lookup tables and floating-point operations are used to implement
data paths. In order to facilitate comparison with existing FPGA devices, the virtual embedded
block scheme is proposed to model embedded blocks using existing field-programmable gate
array (FPGA) tools. This methodology involves adopting existing FPGA resources to model the
size, position, and delay of the embedded elements. The standard design flow offered by FPGA
and computer-aided design vendors is then applied and static timing analysis can be used to
estimate the performance of the FPGA with the embedded blocks.

Drawbacks:

 More Delay
 Hardware consumption More

EXISTING SYSTEM:
This paper analyzes the benefits of using half-unit-biased (HUB) formats to implement
floating-point (FP) arithmetic under a round-to-nearest mode from a quantitative point of view.
Using the HUB formats to represent numbers allows the removal of the rounding logic of
arithmetic units, including sticky-bit computation. This is shown for FP adders, multipliers, and
converters. Experimental analysis demonstrates that the HUB formats and the corresponding
arithmetic units maintain the same accuracy as the conventional ones. On the other hand, the
implementation of these units, based on basic architectures, shows that the HUB formats
simultaneously improve area, speed, and power consumption.

EXISTING SYSTEM DRABACKS:

 Area and Delay more

 More Complexity
PROPOSED SYSTEM:

In this paper we present new architectures based on the double-path technique that speed
up the previous results of HUB addition in FPGA devices presented. Moreover, the problem of
bias when rounding in the previous architectures is overcome by adapting the proposal. The
proposed double-path HUB adder is presented in Bellow Fig. It has a global structure similar to
that of the classic double-path implementation, except that the circuits required for rounding
have been eliminated to handle floating point HUB numbers. The left adder forms the Close
path, and the right adder forms the Far path, both including only one variable shifter. Note that in
both paths the Implicit Least Significant Bit (ILSB) of the operands is incorporated as the Least
Significant Bit (LSB) of the operation in the suitable modules in the architecture (R1-SHIFTER,
R-SHIFTER and both adders). As well, that sign extension (bit 0) is incorporated in the top
conditional inverter and at the second input of the two adders.
 Block diagram of proposed design

PROPOSED SYSTEM ADVANTAGES:

 Bias Rounding Problem is overcome in Proposed Method

 It is possible to eliminate the rounding logic which
 It reduces both area and delay
SYNTHESIS TOOL:

XILINX 9.1/13.2:

Xilinx Tools is a synthesize tools used for the design of digital circuits implemented
using Xilinx Field Programmable Gate Array (FPGA). Digital designs can be entered in various
ways using the above CAD tools: using a schematic entry tool, using a hardware description
language (HDL) – Verilog or VHDL or a combination of both.

HARDWARE REQUIREMENT:

FPGA:

Field Programmable Gate Arrays (FPGAs) are programmable semiconductor devices

that are based around a matrix of Configurable Logic Blocks (CLBs) connected through
programmable interconnects. As opposed to Application Specific Integrated Circuits (ASICs),
where the device is custom built for the particular design, FPGAs can be programmed to the
desired application or functionality requirements and One-Time Programmable (OTP) FPGAs
are available. In our project we are using Spartan 3 FPGA kit.

SPARTAN 3:

The Spartan 3 trainer xc3s200 tq144 is useful to realize and verify digital designs. User
can construct Verilog/VHDL code and verify the results by implementing physically into the
target device (FPGA). With the help of this kit user can simulate/observe various input and
output conditions to verify the implemented design.

PROGRAMING LANGUAGE:

VERILOG HDL

Verilog, standardized as IEEE 1364, is a hardware description language (HDL) used to

model electronic systems. It is most commonly used in the design and verification of digital
circuits at the register-transfer level of abstraction. It is also used in the verification of analog
circuits and mixed-signal circuits, as well as in the design of genetic circuits. In 2009, the
Verilog standard (IEEE 1364-2005) was merged into the System Verilog standard, creating IEEE
Standard 1800-2009. Since then, Verilog is officially part of the System Verilog language. The
current version is IEEE standard 1800-2017.

REAL TIME APLLICATIONS:

 Arithmetic Processing unit

 FFT / IFFT Applications
 Filtering Applications

MODIFICATION:

 We will design a FIR Filter Implementation based on Proposed HUB Adder Design.

MODIFIED TITLE:

Title 1: Implementation of FIR Filter based on Fast Hub Floating-Point Adder

Title 2: A Design of High Speed Hub Floating-Point Adder using Verilog HDL

Title 3: FPGA Implementation of Fast Hub Floating-Point Adder