Assignment-2

Computer Organization and Assembly Language

Name: Hafiz Abdullah Bin Shoaib

Roll No: 21F-BSCS-62
Contents

Q-1 Define pipelining in the context of computer architecture. Explain the concept with the help of a
diagram and describe the advantages it offers over traditional single-cycle processing..............................1
Every phase of the pipeline corresponds to a distinct operation:............................................................1
Pipelining has advantages over conventional single-cycle processing:....................................................1
Q-2. Discuss the major stages involved in the instruction pipeline. What are the potential hazards that
can occur in pipelining, and how can they be mitigated?............................................................................2
Potential Hazards in Pipelining and Mitigation Techniques:....................................................................2
Mitigation strategies:...............................................................................................................................2
Mitigation strategies:...............................................................................................................................2
Mitigation strategies:...............................................................................................................................3
Mitigation strategies................................................................................................................................3
Q-4. Suppose you have a 5-stage pipeline: Instruction Fetch (IF), Instruction Decode (ID), Execute (EX),
Memory Access (MEM), and Write Back (WB). Calculate the speedup achieved by pipelining for a
sequence of 100 instructions, assuming that the pipeline is perfect and there are no stalls or hazards.....3
There are 5 pipeline stages in our scenario (IF, ID, EX, MEM, and WB). The speedup would therefore
be:...........................................................................................................................................................3
Let's examine the execution of the same 100 instructions on a pipelined CPU to a non-pipelined
processor to better understand the speedup:.........................................................................................4
Processor without a pipeline:..................................................................................................................4
Processor in a pipeline:............................................................................................................................4
Q-5. Compare and contrast different cache mapping techniques: direct-mapped, set-associative, and fully
associative. Discuss their performance, implementation complexity, and trade-offs..................................5
Cache Direct-Mapped:.............................................................................................................................5
Associative Cache Set:.............................................................................................................................5
Comprehensive Cache:............................................................................................................................6
In conclusion, every cache mapping method has advantages and disadvantages of its own:.................6
Q-8. Explain the key factors that influence CPU performance. How does the instruction set architecture
(ISA) affect the overall performance of a CPU?............................................................................................6
The main elements affecting CPU performance are:...............................................................................6
Q-1 Define pipelining in the context of computer architecture. Explain the
concept with the help of a diagram and describe the advantages it offers over
traditional single-cycle processing.

In the context of computer architecture, the term "pipelining" refers to a method for increasing a
processor's overall efficiency by segmenting the execution of instructions into a number of overlapping
stages. The pipeline's stages each carry out a distinct function, and several instructions are
simultaneously being executed at different levels. By processing many instructions simultaneously, the
processor is able to increase throughput and speed up program execution.

Instruction 1: IF | ID | EX | MEM | WB

Instruction 2: IF | ID | EX | MEM | WB

Instruction 3: IF | ID | EX | MEM | WB

Instruction 4: IF | ID | EX | MEM | WB

Every phase of the pipeline corresponds to a distinct operation:

1. Fetch the following instruction from memory using IF (Instruction Fetch).

2. ID (Instruction Decode): Read the required registers and decode the instruction that was
fetched.
3. Execute the action or computation directed by the instruction by typing EX (Execution).
4. If memory access is necessary, such as for load/store instructions, use MEM (Memory Access).
5. Write the results of the instruction back into the proper registers using the WB (Write Back)
command.

Pipelining has advantages over conventional single-cycle processing:

1. Increased Throughput: Pipelining enables the processing of several instructions at once,

maximizing the number of instructions finished in a given amount of time. Performance
improves and throughput is increased as a result.
2. Reduced Latency: By segmenting the process into phases and overlapping them, pipelines
shorten the amount of time it takes to carry out each command. Individual instruction latency is
reduced as a result, increasing processor efficiency.
3. Improved Resource Utilization: During single-cycle processing, some resources may go unused
while others are in use. Pipelining allows the processor to maximize resource usage and boost
efficiency by keeping various stages occupied with various instructions.

Despite the benefits, pipelining also brings with it some disadvantages, including as risks (data risks,
control risks, and structural risks) that, if not adequately managed, might impair performance.
Nevertheless, with proper planning and optimization, pipelining can be a very successful method for
enhancing processor performance in contemporary computer systems.
Q-2. Discuss the major stages involved in the instruction pipeline. What are
the potential hazards that can occur in pipelining, and how can they be
mitigated?

The execution of instructions is divided into numerous stages, each of which is in charge of a certain task.
The following are the key phases of the instruction pipeline:

1. Instruction Fetch (IF): Using the program counter (PC) as the address, the processor retrieves
the instruction from memory at this stage. After that, an instruction register is used to hold the
retrieved instruction.
2. Instruction Decode (ID): In this step, the fetched instruction is decoded to reveal the operation
and operands to be executed. In this phase, register values may also be read.
3. Execution (EX): During this phase, the instruction's specified actual operation is carried out. The
calculations involved can be arithmetic or logical, and the outcomes might be saved in
temporary registers.
4. Memory Access (MEM): This stage is responsible for accessing memory if required by the
instruction. For load instructions, data is fetched from memory and stored in temporary
registers. For store instructions, data from registers is stored in memory.
5. Write Back (WB): In the final stage, the results of the executed instruction are written back to
the appropriate registers in the register file.

Potential Hazards in Pipelining and Mitigation Techniques:

1. Data Hazards: Data risks happen when an instruction rely on the outcome of an earlier command
that hasn't been finished. Read After Write (RAW), Write After Read (WAR), and Write After Write
(WAW) are the three different categories of data dangers.

Mitigation strategies:

 The results of an instruction in the EX or MEM stage can be transmitted directly to the
dependant instruction in the ID or EX stage via forwarding (also known as data forwarding or
data hazard interlocking). This avoids the WB stage.
 The pipeline can be paused (i.e., insert a bubble or NOP - No-Operation) when a data hazard is
discovered to provide time for the data dependency to be resolved.
2. Control risks: Control risks happen when conditional branches or jumps alter the program's logic. In
a pipelined processor, when the branch choice is decided later, retrieving and decoding future
instructions may become challenging.

Mitigation strategies:

 Branch Prediction: Make a prediction about the branch's conclusion (whether it will be taken or
not), then hypothetically fetch the instructions along the projected path. If the prediction is
accurate, the pipeline runs uninterrupted. If not, the faulty instructions are flushed (discarded)
and the proper instructions are retrieved.
 3. Structural risks: Structural risks occur when several instructions use the same hardware resource at
once. Two instructions might simultaneously attempt to write to the same register or access
memory, for instance.

Mitigation strategies:

 Duplicate essential hardware resources so they can process several commands at once.
4. Resource Partitioning: To prevent conflicts, divide the processor into several units to handle
different kinds of instructions. Data When numerous instructions attempt to access the same
memory region at once, cache dangers develop.

Mitigation strategies

 Implement cache coherence methods to guarantee that all caches contain the most recent
values.

It's important to remember that while these strategies can reduce a variety of risks, they can also add
complexity and even have an impact on performance. To achieve a balance between performance
enhancements and the complexity of the pipeline, skilled design and optimization are required.

Q-4. Suppose you have a 5-stage pipeline: Instruction Fetch (IF), Instruction
Decode (ID), Execute (EX), Memory Access (MEM), and Write Back (WB).
Calculate the speedup achieved by pipelining for a sequence of 100
instructions, assuming that the pipeline is perfect and there are no stalls or
hazards.

Through the simultaneous execution of several instructions, pipelining is a potent approach employed in
contemporary computer processors to enhance performance and boost throughput and overall
efficiency. Pipelining enables the processor to overlap the execution of various stages for various
instructions, resulting in better resource utilization and faster execution, as opposed to processing one
instruction at a time through all stages (IF, ID, EX, MEM, and WB) before going on to the next instruction.

A pipeline without risks or stalls is the ideal one. When dependencies between instructions prevent the
next instruction from beginning its execution until the dependency has been resolved, hazards may
result. On the other hand, stalls can be brought on by a number of things, including data hazards,
branching, or cache misses. We presume that in a perfect pipeline there are no such stalls or dangers,
enabling the processor to operate at optimum efficiency.

The formula below can be used to determine the speedup brought on by pipelining when there are no
stalls or dangers.

Speedup is equal to the product of the number of pipeline stages and one.
There are 5 pipeline stages in our scenario (IF, ID, EX, MEM, and WB). The speedup would therefore
be:

Speedup is equal to 5 / (5 - 1) = 5 / 4 = 1.25.

This indicates that a processor with pipelines can execute a sequence of 100 instructions around 1.25
times faster than a processor without pipelines can handle the same sequence of instructions.

Let's examine the execution of the same 100 instructions on a pipelined CPU to a non-pipelined
processor to better understand the speedup:

Processor without a pipeline:

 the first instruction is retrieved (IF).

 gets the operands for the first instruction (ID) and decodes it.

 carries out the initial command (EX).

 if necessary, does a memory access (MEM).

 Writes the outcome back (WB) to the memory or register file.

 sequentially repeats the same actions for every instruction.

Processor in a pipeline:

 The pipelined processor divides the 100 instructions into phases and begins carrying out several
instructions at once. At any given time, each stage is processing a distinct instruction.
  The first instruction may be in the Execute stage (EX), followed by the Instruction Decode stage
(ID), the Instruction Fetch stage (IF), the Second Instruction, and so on.\

The pipelined processor completes the series of 100 instructions significantly faster than the non-
pipelined processor, achieving a speedup of almost 1.25 times as a result of this overlapping of
instruction execution in the pipeline.

While pipelining is a potent strategy for enhancing performance, it may not always achieve the greatest
speedup feasible due to a variety of reasons like data risks, branch mispredictions, and other pipeline
bottlenecks. The actual speedup can be a little bit less than the predicted optimal value in real-world
settings. However, pipelining is still a vital component of contemporary processor architecture and has
greatly advanced computer technology.

Q-5. Compare and contrast different cache mapping techniques: direct-

mapped, set-associative, and fully associative. Discuss their performance,
implementation complexity, and trade-offs.

The methods for placing data in the cache memory, known as cache mapping techniques, are critical for
influencing cache performance, implementation complexity, and trade-offs. The three most popular
cache mapping methods—direct-mapped, set-associative, and completely associative—will be
contrasted and compared.

Cache Direct-Mapped:

Performance: Each block in main memory is mapped to only one particular place (cache line) in a direct-
mapped cache. As a result, if numerous memory blocks are mapped to the same cache line, cache
conflicts may occur. In situations where there is a lot of competition for a given cache line, this can
increase the risk of cache misses.

Implementation Difficulty: Since each memory block has a set placement in the cache, direct-mapped
caches are quite easy to create. In comparison to alternative mapping strategies, this simplicity enables
quicker cache access times.

Trade-offs: The biggest drawback of direct-mapped caches is that, due to their low associativity, they
may have significant conflict misses. Uneven cache utilization, where certain cache lines may be
frequently utilized while others remain underutilized, is another potential side effect of the fixed
mapping approach.

Associative Cache Set:

Performance: Set-associative caches offer a middle ground between completely associative and direct-
mapped caches. There are several cache lines in each of the sets that make up the cache. A hashing
function is used to map memory blocks to particular sets. As opposed to direct-mapped caches, each set
can contain numerous cache lines, giving some latitude in cache placement and lowering the risk of
conflict misses.

Implementation Difficulty: Because a hashing algorithm and cache set management are required, set-
associative caches are more difficult to implement than direct-mapped caches. The complexity is still less
than completely associative caches, though.

Trade-offs: Set-associative cache trade-offs entail striking a compromise between complexity and
performance. Conflict misses can be decreased by increasing associativity, but access latency and
complexity also rise.

Comprehensive Cache:

Performance: A fully associative cache offers the utmost flexibility and completely eliminates the chance
of conflict misses because each memory block can be inserted into any cache line. When compared to
direct-mapped and set-associative caches, this results in improved cache utilization and perhaps lower
miss rates.

Fully associative caches are the most difficult to design since they need a more complex search algorithm
to locate the desired memory block among all cache lines. When compared to direct-mapped and set-
associative caches, this complexity results in slower access times and more expensive hardware.

Trade-offs: Fully associative caches have a higher level of hardware complexity and access latency, which
is their principal trade-off.

In conclusion, every cache mapping method has advantages and disadvantages of its own:

Although direct-mapped caches are easy to set up, they may have lower cache usage and higher conflict
misses.

Compared to direct-mapped caches, set-associative caches reduce conflict misses by balancing

complexity and efficiency.

The best cache usage and potential miss rates are provided by fully associative caches, which also have
higher hardware complexity and access latency.

The target application, cache size, access patterns, and financial limitations are only a few factors that
affect which cache mapping technique is best for a given system. To choose the best option for a given
situation, designers must carefully consider these factors.

Q-8. Explain the key factors that influence CPU performance. How does the
instruction set architecture (ISA) affect the overall performance of a CPU?
The main elements affecting CPU performance are:

 Clock Speed: The amount of instructions the CPU can process in a second depends on its clock
speed. Although quicker processing is often the result of higher clock speeds, these speeds can
also result in higher power usage and heat production.

 Instruction-Level Parallelism (ILP): By simultaneously executing several instructions, modern

CPUs maximize resource efficiency and boost speed. Examples of these techniques are
instruction pipelining and superscalar execution.

 Memory access latency is decreased by caching frequently accessed data close to the CPU.
Performance can be increased by minimizing the amount of time spent waiting for data from
main memory with larger and more effective caches.

 Memory Access and Hierarchy: The performance of the CPU depends on effective memory
access. How rapidly data may be processed depends on the memory hierarchy, which includes
registers, caches, and main memory.
 Branch Prediction: To minimize pipeline pauses and boost speed, CPUs use branch prediction
algorithms to foresee the results of conditional branches.

 Simultaneous Operation on several Data Element (SIMD) and Vectorization: SIMD (Single
Instruction, Multiple Data) instructions allow CPUs to process the same operation on several
data elements at once, improving performance for particular tasks like multimedia processing.

 Pipelining and Superscalar Execution: Pipelining separates the execution of instructions into
various stages, enabling the processing of numerous instructions at once. This idea is expanded
upon by superscalar execution, which boosts throughput even further.

The instructions that a CPU may execute and how they are encoded are specified by the Instruction Set
Architecture (ISA), which has an impact on CPU performance. Faster instruction decoding and execution
can result from a well-designed ISA, which also makes hardware simpler. Significant ISA performance
effects include:

 Instruction Complexity: A straightforward and orthogonal ISA makes it easier to decode and
execute instructions, enhancing CPU speed and efficiency.
  Support for Parallelism: Parallelism-supporting ISA characteristics, like as SIMD instructions,
allow CPUs to handle several data components at once, speeding up some processes.

 Effective ISA addressing options minimize memory access overhead and increase cache usage.

 Compact instruction encoding saves cache space and lowers memory bandwidth needs, enabling
quicker fetches of instructions.
 Coprocessor Support: In some areas, the speed of the CPU can be greatly improved by using ISA
instructions for specialist coprocessors, such as floating-point units or cryptographic
accelerators.

In short, by specifying the available instructions and their properties, the ISA has a major impact on CPU
performance. Improved performance, effective hardware use, and higher parallelism and vectorization
capability exploitation can all be attributed to a well-designed ISA.