HUF76129D3, HUF76129D3S

Data Sheet January 2003

20A, 30V, 0.016 Ohm, N-Channel, Logic Features

Level UltraFET Power MOSFETs • Logic Level Gate Drive
These N-Channel power MOSFETs
• 20A, 30V
are manufactured using the
innovative UltraFET™ process. • Ultra Low On-Resistance, rDS(ON) = 0.016Ω
This advanced process technology • Temperature Compensating PSPICE® Model
achieves the lowest possible on-resistance per silicon area,
resulting in outstanding performance. This device is capable • Temperature Compensating SABER© Mode
of withstanding high energy in the avalanche mode and the • Thermal Impedance SPICE Model
diode exhibits very low reverse recovery time and stored
• Thermal Impedance SABER Model
charge. It was designed for use in applications where power
efficiency is important, such as switching regulators, • Peak Current vs Pulse Width Curve
switching converters, motor drivers, relay drivers, low- • UIS Rating Curve
voltage bus switches, and power management in portable
and battery-operated products. • Related Literature
- TB334, “Guidelines for Soldering Surface Mount
Formerly developmental type TA76129. Components to PC Boards”

Ordering Information Symbol

PART NUMBER PACKAGE BRAND D
HUF76129D3 TO-251AA 76129D
HUF76129D3S TO-252AA 76129D
G
NOTE: When ordering, use the entire part number. Add the suffix T to
obtain the TO-252AA variant in tape and reel, e.g., HUF76129D3ST.
S

Packaging
JEDEC TO-251AA JEDEC TO-252AA

SOURCE
DRAIN DRAIN
GATE DRAIN
(FLANGE)
GATE (FLANGE)

SOURCE

©2003 Fairchild Semiconductor Corporation HUF76129D3, HUF76129D3S Rev. B1

 HUF76129D3, HUF76129D3S

Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified

UNITS
Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS 30 V
Drain to Gate Voltage (R GS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDGR 30 V
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS ±20 V
Drain Current
Continuous (TC = 25oC, VGS = 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID 20 A
Continuous (TC = 100oC, VGS = 5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID 20 A
Continuous (TC = 100oC, VGS = 4.5V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID 20 A
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Figure 4
Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Figures 6, 17, 18
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD 105 W
Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 W/oC
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG -55 to 150 oC

Maximum Temperature for Soldering

Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL 300 oC
Package Body for 10s, See Techbrief 334. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Tpkg 260 oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:
1. TJ = 25oC to 150oC.

Electrical Specifications TA = 25oC, Unless Otherwise Specified

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

OFF STATE SPECIFICATIONS

Drain to Source Breakdown Voltage BVDSS ID = 250µA, VGS = 0V (Figure 12) 30 - - V

Zero Gate Voltage Drain Current IDSS VDS = 25V, VGS = 0V - - 1 µA

VDS = 25V, VGS = 0V, TC = 150oC - - 250 µA

Gate to Source Leakage Current IGSS VGS = ±20V - - ±100 nA

ON STATE SPECIFICATIONS

Gate to Source Threshold Voltage VGS(TH) VGS = VDS, ID = 250µA (Figure 11) 1 - 3 V

Drain to Source On Resistance rDS(ON) ID = 20A, VGS = 10V (Figure 9, 10) - 0.014 0.016 Ω

ID = 20A, VGS = 5V (Figure 9) - 0.0175 0.021 Ω

ID = 20A, VGS = 4.5V (Figure 9) - 0.0195 0.023 Ω

THERMAL SPECIFICATIONS

Thermal Resistance Junction to Case R θJC (Figure 3) - - 1.20 oC/W

Thermal Resistance Junction to Ambient RθJA TO-251, TO-252 - - 100 oC/W

SWITCHING SPECIFICATIONS (VGS = 4.5V)

Turn-On Time tON VDD = 15V, ID ≅ 20A, RL = 0.75Ω, - - 275 ns

VGS = 4.5V, RGS = 10Ω
Turn-On Delay Time td(ON) (Figures 15, 21, 22) - 20 - ns

Rise Time tr - 165 - ns

Turn-Off Delay Time td(OFF) - 30 - ns

Fall Time tf - 54 - ns

Turn-Off Time tOFF - - 125 ns

©2003 Fairchild Semiconductor Corporation HUF76129D3, HUF76129D3S Rev. B1

 HUF76129D3, HUF76129D3S

Electrical Specifications TA = 25oC, Unless Otherwise Specified (Continued)

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

SWITCHING SPECIFICATIONS (VGS = 10V)

Turn-On Time tON VDD = 15V, ID ≅ 20A, RL = 0.75Ω, - - 80 ns

VGS = 10V, RGS = 10Ω
Turn-On Delay Time td(ON) (Figures 16, 21, 22) - 7 - ns

Rise Time tr - 47 - ns

Turn-Off Delay Time td(OFF) - 60 - ns

Fall Time tf - 54 - ns

Turn-Off Time tOFF - - 110 ns

GATE CHARGE SPECIFICATIONS

Total Gate Charge Qg(TOT) VGS = 0V to 10V VDD = 15V, ID ≅ 20A, - 38 46 nC

RL = 0.75Ω
Gate Charge at 5V Qg(5) VGS = 0V to 5V Ig(REF) = 1.0mA - 22 26 nC

Threshold Gate Charge Qg(TH) VGS = 0V to 1V (Figures 14, 19, 20) - 1.4 1.7 nC

Gate to Source Gate Charge Qgs - 3.70 - nC

Gate to Drain “Miller” Chatge Qgd - 11.20 - nC

CAPACITANCE SPECIFICATIONS

Input Capacitance CISS VDS = 25V, VGS = 0V, f = 1MHz - 1425 - pF

(Figure 13)
Output Capacitance COSS - 720 - pF

Reverse Transfer Capacitance CRSS - 170 - pF

Source to Drain Diode Specifications

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Source to Drain Diode Voltage VSD ISD = 20A - - 1.25 V

Reverse Recovery Time trr ISD = 20A, dISD/dt = 100A/µs - - 72 ns

Reverse Recovered Charge QRR ISD = 20A, dISD/dt = 100A/µs - - 107 nC

Typical Performance Curves

1.2 25
POWER DISSIPATION MULTIPLIER

1.0
20
ID, DRAIN CURRENT (A)

0.8
15 VGS=10V

0.6
VGS=4.5V
10
0.4

5
0.2

0 0
0 25 50 75 100 125 150 25 50 75 100 125 150
TA , AMBIENT TEMPERATURE (oC) TC, CASE TEMPERATURE (oC)

FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
TEMPERATURE CASE TEMPERATURE

©2003 Fairchild Semiconductor Corporation HUF76129D3, HUF76129D3S Rev. B1

 HUF76129D3, HUF76129D3S

Typical Performance Curves (Continued)

2
DUTY CYCLE - DESCENDING ORDER
0.5
1 0.2
0.1
THERMAL IMPEDANCE

0.05
Zθ JC, NORMALIZED

0.02
0.01
PDM

0.1
t1
t2
NOTES:
SINGLE PULSE DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
0.01
10-5 10-4 10-3 10-2 10-1 10 0 101
t , RECTANGULAR PULSE DURATION (s)

FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE

2000
TC = 25 oC
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
IDM, PEAK CURRENT (A)

CURRENT AS FOLLOWS:
VGS = 10V
I = I25 150 - TC
125
100
VGS = 5V

TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
10
10-5 10-4 10-3 10-2 10-1 100 101
t, PULSE WIDTH (s)

FIGURE 4. PEAK CURRENT CAPABILITY

1000 500
TJ = MAX RATED If R = 0
TC = 25 oC tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
IAS, AVALANCHE CURRENT (A)

If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
100µs
ID, DRAIN CURRENT (A)

100
100

STARTING TJ = 25oC
1ms
10
10 STARTING TJ = 150oC
10ms
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON) BVDSS MAX = 30V
1
1
1 10 100 0.01 0.1 1 10 100
VDS, DRAIN TO SOURCE VOLTAGE (V) tAV, TIME IN AVALANCHE (ms)

NOTE: Refer to Fairchild Application Notes AN9321 and AN9322.

FIGURE 5. FORWARD BIAS SAFE OPERATING AREA FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING
CAPABILITY

©2003 Fairchild Semiconductor Corporation HUF76129D3, HUF76129D3S Rev. B1

 HUF76129D3, HUF76129D3S

Typical Performance Curves (Continued)

60 60
PULSE DURATION = 80µs 25oC VGS = 10V PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX VGS = 5V
-55 oC DUTY CYCLE = 0.5% MAX
VGS = 4.5V
ID, DRAIN CURRENT (A)

45 VGS = 4V

ID, DRAIN CURRENT (A)

45 VGS = 3.5V

150oC
30 30
VGS = 3V

15 15

VDD = 15V
0 0
0 1 2 3 4 0 1 2 3 4 5
VGS, GATE TO SOURCE VOLTAGE (V) VDS, DRAIN TO SOURCE VOLTAGE (V)

FIGURE 7. TRANSFER CHARACTERISTICS FIGURE 8. SATURATION CHARACTERISTICS

30 1.6
ID = 20A PULSE DURATION = 80µs PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX DUTY CYCLE = 0.5% MAX
27 NORMALIZED DRAIN TO SOURCE VGS = 10V, ID = 20A
rDS(ON), DRAIN TO SOURCE

1.4
ON RESISTANCE (mΩ)

ID = 10A
ON RESISTANCE

24
1.2
ID = 5A
21

1.0
18

15 0.8

12 0.6
2 4 6 8 10 -80 -40 0 40 80 120 160
VGS, GATE TO SOURCE VOLTAGE (V) TJ, JUNCTION TEMPERATURE (oC)

FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE FIGURE 10. NORMALIZED DRAIN TO SOURCE ON
VOLTAGE AND DRAIN CURRENT RESISTANCE vs JUNCTION TEMPERATURE

1.2 1.15
VGS = VDS, ID = 250µA I D = 250µA
NORMALIZED DRAIN TO SOURCE

1.1
1.10
BREAKDOWN VOLTAGE
THRESHOLD VOLTAGE
NORMALIZED GATE

1.0
1.05
0.9

1.00
0.8

0.95
0.7

0.6 0.90
-80 -40 0 40 80 120 160 -80 -40 0 40 80 120 160
TJ, JUNCTION TEMPERATURE (oC) TJ , JUNCTION TEMPERATURE (oC)

FIGURE 11. NORMALIZED GATE THRESHOLD VOLTAGE vs FIGURE 12. NORMALIZED DRAIN TO SOURCE BREAKDOWN
JUNCTION TEMPERATURE VOLTAGE vs JUNCTION TEMPERATURE

©2003 Fairchild Semiconductor Corporation HUF76129D3, HUF76129D3S Rev. B1

 HUF76129D3, HUF76129D3S

Typical Performance Curves (Continued)

2000 10
VDD = 15V

VGS , GATE TO SOURCE VOLTAGE (V)

1600 8
C, CAPACITANCE (pF)

CISS
VGS = 0V, f = 1MHz
1200 CISS = CGS + CGD
6
COSS CRSS = CGD
COSS ≈ C DS + CGD
800 4
WAVEFORMS IN
DESCENDING ORDER:
400 2 ID = 20A
CRSS ID = 10A
ID = 2A
0 0
0 5 10 15 20 25 30 0 10 20 30 40
VDS , DRAIN TO SOURCE VOLTAGE (V) Qg, GATE CHARGE (nC)

NOTE: Refer to Fairchild Application Notes 7254 and 7260.

FIGURE 13. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE FIGURE 14. GATE CHARGE WAVEFORMS FOR CONSTANT
GATE CURRENT

500 300
VGS = 4.5V, VDD = 15V, ID = 20A, RL= 0.75Ω VGS = 10V, VDD = 15V, I D = 20A, RL= 0.75Ω
250
400
tr
SWITCHING TIME (ns)

SWITCHING TIME (ns)

td(OFF)
200
300
tf
td(OFF) tf 150
200
100
tr
100
50
td(ON) td(ON)

0 0
0 10 20 30 40 50 0 10 20 30 40 50
R GS, GATE TO SOURCE RESISTANCE (Ω) RGS, GATE TO SOURCE RESISTANCE (Ω)

FIGURE 15. SWITCHING TIME vs GATE RESISTANCE FIGURE 16. SWITCHING TIME vs GATE RESISTANCE

Test Circuits and Waveforms

VDS

BVDSS

L tP
VDS

VARY tP TO OBTAIN IAS

+ VDD
REQUIRED PEAK IAS RG
VDD
VGS -
DUT

tP
0V IAS
0
0.01Ω
tAV

FIGURE 17. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 18. UNCLAMPED ENERGY WAVEFORMS

©2003 Fairchild Semiconductor Corporation HUF76129D3, HUF76129D3S Rev. B1

 HUF76129D3, HUF76129D3S

Test Circuits and Waveforms (Continued)

VDS
RL VDD Qg(TOT)

VDS
VGS = 10

VGS Qg(5)
+
VDD
VGS VGS = 5V
-

DUT VGS = 1V
Ig(REF) 0
Qg(TH)

Ig(REF)
0

FIGURE 19. GATE CHARGE TEST CIRCUIT FIGURE 20. GATE CHARGE WAVEFORMS

VDS tON tOFF

td(ON) td(OFF)

RL tr tf
VDS
90% 90%

+
VGS
VDD 10% 10%
- 0

DUT 90%
RGS
VGS 50% 50%
PULSE WIDTH
VGS 10%
0

FIGURE 21. SWITCHING TIME TEST CIRCUIT FIGURE 22. SWITCHING TIME WAVEFORM

©2003 Fairchild Semiconductor Corporation HUF76129D3, HUF76129D3S Rev. B1

 HUF76129D3, HUF76129D3S

PSPICE Electrical Model

SUBCKT HUF76129D 2 1 3 ; REV April 1998
CA 12 8 1.95e-9
CB 15 14 1.85e-9 LDRAIN
CIN 6 8 1.31e-9 DPLCAP 5 DRAIN
2
10
DBODY 7 5 DBODYMOD RLDRAIN
RSLC1
DBREAK 5 11 DBREAKMOD 51 DBREAK
DPLCAP 10 5 DPLCAPMOD RSLC2
+
5
ESLC 11
51
-
EBREAK 11 7 17 18 32
50 +
EDS 14 8 5 8 1 -
EGS 13 8 6 8 1 RDRAIN 17 DBODY
6 EBREAK 18
ESG 6 10 6 8 1 ESG 8
EVTHRES 6 21 19 8 1 + EVTHRES 16
-
EVTEMP 20 6 18 22 1 + 19 - 21
LGATE EVTEMP MWEAK
8
GATE RGATE + 18 - 6
1 22 MMED
IT 8 17 1 9 20
RLGATE MSTRO
LDRAIN 2 5 1e-9
LSOURCE
LGATE 1 9 2.20e-9 CIN SOURCE
8 7
LSOURCE 3 7 3.03e-9 3
RSOURCE
MMED 16 6 8 8 MMEDMOD RLSOURCE
MSTRO 16 6 8 8 MSTROMOD S1A S2A
MWEAK 16 21 8 8 MWEAKMOD 12 RBREAK
13 14 15
17 18
8 13
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 1.9e-3 S1B S2B RVTEMP
RGATE 9 20 3.5 13 CB
CA 19
RLDRAIN 2 5 10 14 IT -
RLGATE 1 9 22 + +
RLSOURCE 3 7 30.3 6 5 VBAT
EGS EDS +
RSLC1 5 51 RSLCMOD 1e-6 8 8
RSLC2 5 50 1e3 - - 8
RSOURCE 8 7 RSOURCEMOD 10e-3 22
RVTHRES 22 8 RVTHRESMOD 1 RVTHRES
RVTEMP 18 19 RVTEMPMOD 1

S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD

VBAT 22 19 DC 1

ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*1000),3.5))}

.MODEL DBODYMOD D (IS = 1.2e-12 IKF = 8 TIKF = 1e-2 RS = 7.7e-3 TRS1 = 3e-4 TRS2 = 1e-6 CJO = 2.23e-9 TT = 35e-9 M = 4e-1 XTI =4.75 )
.MODEL DBREAKMOD D (RS = 9.5e-2 TRS1 = 4e-3 TRS2 = 3e-5 IKF = 1e-1)
.MODEL DPLCAPMOD D (CJO = 1.12e-10 IS = 1e-30 N = 10 M = 6.5e-1 VJ = 1.45)
.MODEL MMEDMOD NMOS (VTO = 1.87 KP = 5.75 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 1)
.MODEL MSTROMOD NMOS (VTO = 2.15 KP = 90 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 1.49 KP =2e-2 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 10)
.MODEL RBREAKMOD RES (TC1 = 9.8e-4 TC2 = -1e-10)
.MODEL RDRAINMOD RES (TC1 = 1e-2 TC2 = 1e-5)
.MODEL RSLCMOD RES (TC1 = 1e-6 TC2 = 1.05e-6)
.MODEL RSOURCEMOD RES (TC1 = 2.5e-3 TC2 = 2e-6)
.MODEL RVTHRESMOD RES (TC1 = -1.8e-3 TC2 = -1.1e-5)
.MODEL RVTEMPMOD RES (TC1 = -1.65e-3 TC2 = 1.45e-6)

.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -10.0 VOFF= -0.50)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -0.50 VOFF= -10.0)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.00 VOFF= 0.50)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.50 VOFF= 0.00)

.ENDS

NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.

©2003 Fairchild Semiconductor Corporation HUF76129D3, HUF76129D3S Rev. B1

 HUF76129D3, HUF76129D3S

SABER Electrical Model

nom temp=25 deg c 30v LL Ultrafet
REV April 1998
template huf76129D n2,n1,n3
electrical n2,n1,n3
{
var i iscl
d..model dbodymod = (is=1.2e-12, xti=4.75, cjo=2.23e-9,tt=35e-8, m=4e-1)
d..model dbreakmod = (is=1e-14)
d..model dplcapmod = (cjo=1.12e-9,is=1e-30,n=10,m=6.5e-1, vj=1.45, fc=5e-1)
m..model mmedmod = (type=_n,vto=1.87,kp=5.75,is=1e-30, tox=1)
m..model mstrongmod = (type=_n,vto=2.15,kp=90,is=1e-30, tox=1)
LDRAIN
m..model mweakmod = (type=_n,vto=1.49,kp=2e-2,is=1e-30, tox=1) DPLCAP 5 DRAIN
sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-10.0,voff=-0.5) 2
sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-0.5,voff=10.0) 10
sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=0,voff=0.5) RLDRAIN
sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=0.5,voff=0) RSLC1
51 RDBREAK
c.ca n12 n8 = 1.95e-9 RSLC2
72 RDBODY
c.cb n15 n14 = 1.85e-9 ISCL
c.cin n6 n8 = 1.31e-9
50 DBREAK
-
d.dbody n7 n71 = model=dbodymod RDRAIN 71
6
d.dbreak n72 n11 = model=dbreakmod ESG 11
8
d.dplcap n10 n5 = model=dplcapmod + EVTHRES 16
+ 19 - 21
i.it n8 n17 = 1 LGATE EVTEMP MWEAK
8 DBODY
GATE RGATE +
18 - 6 EBREAK
l.ldrain n2 n5 = 1e-9 1 22 MMED
9 +
l.lgate n1 n9 = 2.2e-9 20
RLGATE MSTRO 17
l.lsource n3 n7 = 3.03e-9 18 LSOURCE
CIN - SOURCE
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u 8 7 3
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u RSOURCE
RLSOURCE
res.rbreak n17 n18 = 1, tc1=9.8e-4,tc2=-1e-10 S1A S2A
12 RBREAK
res.rdbody n71 n5 =7.7e-3, tc1=2.5e-3, tc2=1e-6 13 14 15
17 18
res.rdbreak n72 n5 =9.5e-2, tc1=4e-3, tc2=3e-5 8 13
res.rdrain n50 n16 = 1.9e-3, tc1=1e-2,tc2=1e-5 RVTEMP
S1B S2B
res.rgate n9 n20 = 3.6e-1
res.rldrain n2 n5 = 10 13 CB 19
CA
res.rlgate n1 n9 = 22 14 IT -
+ +
res.rlsource n3 n7 = 30.3 6 5 VBAT
res.rslc1 n5 n51 = 1e-6, tc1=1e-6,tc2=-1.05e-6 EGS EDS +
8 8
res.rslc2 n5 n50 = 1e3 - - 8
res.rsource n8 n7 = 10e-3, tc1=2.5e-3,tc2=2e-6 22
res.rvtemp n18 n19 = 1, tc1=-1.8e-3,tc2=1.1e-5 RVTHRES
res.rvthres n22 n8 = 1, tc1=-1.65e-3,tc2=-1.45e-6

spe.ebreak n11 n7 n17 n18 = 37

spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1

sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod

sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod

v.vbat n22 n19 = dc=1

equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/1000))** 3.5 ))
}
}

©2003 Fairchild Semiconductor Corporation HUF76129D3, HUF76129D3S Rev. B1

 HUF76129D3, HUF76129D3S

SPICE Thermal Model th JUNCTION

REV April 1998

HUF76129D

CTHERM1 th 6 1.10e-5 RTHERM1 CTHERM1

CTHERM2 6 5 2.70e-2
CTHERM3 5 4 3.90e-2
CTHERM4 4 3 1.00e-2 6
CTHERM5 3 2 2.30e-2
CTHERM6 2 tl 1.80

RTHERM2 CTHERM2
RTHERM1 th 6 1.00e-4
RTHERM2 6 5 5.00e-4
RTHERM3 5 4 2.90e-2
RTHERM4 4 3 4.80e-1 5
RTHERM5 3 2 2.80e-1
RTHERM6 2 tl 1.00e-1
RTHERM3 CTHERM3

SABER Thermal Model

Saber thermal model HUF76129D
4
template thermal_model th tl
thermal_c th, tl
{ RTHERM4 CTHERM4
ctherm.ctherm1 th c2 = 1.10e-5
ctherm.ctherm2 c2 c3 = 2.70e-2
ctherm.ctherm3 c3 c4 = 3.90e-2
ctherm.ctherm4 c4 c5 = 1.00e-2 3
ctherm.ctherm5 c5 c6 = 2.30e-2
ctherm.ctherm6 c6 tl = 1.80
RTHERM5 CTHERM5
rtherm.rtherm1 th c2 = 1.00e-4
rtherm.rtherm2 c2 c3 = 5.00e-4
rtherm.rtherm3 c3 c4 = 2.90e-2
rtherm.rtherm4 c4 c5 = 4.80e-1 2
rtherm.rtherm5 c5 c6 = 2.80e-1
rtherm.rtherm6 c6 tl = 1.00e-1
} RTHERM6 CTHERM6

tl CASE

©2003 Fairchild Semiconductor Corporation HUF76129D3, HUF76129D3S Rev. B1

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Rev. I2