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TMS320F2807x Microcontrollers
– Two I2C interfaces (pin-bootable)
1 Features
• Analog subsystem
• TMS320C28x 32-bit CPU – Up to three Analog-to-Digital Converters
– 120 MHz (ADCs)
– IEEE 754 single-precision Floating-Point Unit • 12-bit mode
(FPU) – 3.1 MSPS each (up to 9.3-MSPS system
– Trigonometric Math Unit (TMU) throughput)
• Programmable Control Law Accelerator (CLA) – Single-ended inputs
– 120 MHz – Up to 17 external channels
– IEEE 754 single-precision floating-point • Single Sample-and-Hold (S/H) on each ADC
instructions • Hardware-integrated post-processing of
– Executes code independently of main CPU ADC conversions
• On-chip memory – Saturating offset calibration
– 512KB (256KW) of flash (ECC-protected) – Error from setpoint calculation
– 100KB (50KW) of RAM (ECC-protected or – High, low, and zero-crossing compare,
parity-protected) with interrupt capability
– Dual-zone security supporting third-party – Trigger-to-sample delay capture
development – Eight windowed comparators with 12-bit Digital-
– Unique identification number to-Analog Converter (DAC) references
• Clock and system control – Three 12-bit buffered DAC outputs
– Two internal zero-pin 10-MHz oscillators • Enhanced control peripherals
– On-chip crystal oscillator – 24 PWM channels with enhanced features
– Windowed watchdog timer module – 16 High-Resolution Pulse Width Modulator
– Missing clock detection circuitry (HRPWM) channels
• 3.3-V I/O with available internal voltage regulator • High resolution on both A and B channels of
for 1.2-V core supply 8 PWM modules
• System peripherals • Dead-band support (on both standard and
– External Memory Interface (EMIF) with ASRAM high resolution)
and SDRAM support – Six Enhanced Capture (eCAP) modules
– 6-channel Direct Memory Access (DMA) – Three Enhanced Quadrature Encoder Pulse
controller (eQEP) modules
– Up to 97 individually programmable, – Up to eight Sigma-Delta Filter Module (SDFM)
multiplexed General-Purpose Input/Output input channels, 2 parallel filters per channel
(GPIO) pins with input filtering • Standard SDFM data filtering
– Expanded Peripheral Interrupt controller (ePIE) • Comparator filter for fast action for out of
– Multiple Low-Power Mode (LPM) support with range
external wakeup • Configurable Logic Block (CLB)
• Communications peripherals – Augments existing peripheral capability
– USB 2.0 (MAC + PHY) – Supports position manager solutions
– Two Controller Area Network (CAN) modules • Functional Safety-Compliant
(pin-bootable) – Developed for functional safety applications
– Three high-speed (up to 30-MHz) SPI ports – Documentation available to aid ISO 26262
(pin-bootable) system design up to ASIL D; IEC 61508 up to
– Two Multichannel Buffered Serial Ports SIL 3; IEC 60730 up to Class C; and UL 1998
(McBSPs) up to Class 2
– Four Serial Communications Interfaces (SCI/ – Hardware integrity up to ASIL B, SIL 2
UART) (pin-bootable) • Safety-related certification

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– ISO 26262 certified up to ASIL B and IEC • EV charging station power module
61508 certified up to SIL 2 by TUV SUD • Energy storage power conversion system (PCS)
• Package options: • Central inverter
– 176-pin PowerPAD™ Thermally Enhanced Low- • Solar power optimizer
Profile Quad Flatpack (HLQFP) [PTP suffix] • String inverter
– 100-pin PowerPAD Thermally Enhanced Thin • Inverter & motor control
Quad Flatpack (HTQFP) [PZP suffix] • On-board (OBC) & wireless charger
• Temperature options: • AC drive control module
– T: –40°C to 105°C junction • AC drive power stage module
– S: –40°C to 125°C junction • Linear motor power stage
– Q: –40°C to 125°C free-air • Servo drive control module
(AEC Q100 qualification for automotive
• AC-input BLDC motor drive
applications)
• DC-input BLDC motor drive
2 Applications • Industrial AC-DC
• Medium/short range radar • Three phase UPS
• Traction inverter motor control
• HVAC large commercial motor control
• Automated sorting equipment
• CNC control
• AC charging (pile) station
• DC charging (pile) station

3 Description
C2000™ 32-bit microcontrollers are optimized for processing, sensing, and actuation to improve closed-loop
performance in real-time control applications such as industrial motor drives; solar inverters and digital power;
electrical vehicles and transportation; motor control; and sensing and signal processing. The C2000 line includes
the Premium performance MCUs and the Entry performance MCUs.
The TMS320F2807x microcontroller family is suited for advanced closed-loop control applications such as
industrial motor drives; solar inverters and digital power; electrical vehicles and transportation; and sensing and
signal processing. To accelerate application development, the DigitalPower software development kit (SDK) for
C2000 MCUs and the MotorControl software development kit (SDK) for C2000™ MCUs are available.
The F2807x is a 32-bit floating-point microcontroller based on TI’s industry-leading C28x core. This core is
boosted by the trigonometric hardware accelerator which improves performance of trigonometric-based
algorithms with CPU instructions such as sine, cosine, and arctangent functions, which are common in torque-
loop and position calculations.
The F2807x microcontroller family features a CLA real-time control coprocessor. The CLA is an independent 32-
bit floating-point processor that runs at the same speed as the main CPU. The CLA responds to peripheral
triggers and executes code concurrently with the main C28x CPU. This parallel processing capability can
effectively double the computational performance of a real-time control system. By using the CLA to service
time-critical functions, the main C28x CPU is free to perform other tasks, such as communications and
diagnostics.
The F2807x device supports up to 512KB (256KW) of ECC-protected onboard flash memory and up to 100KB
(50KW) of SRAM with parity. Two independent security zones are also available for 128-bit code protection of
the main C28x.
The analog subsystem boasts up to three 12-bit ADCs, which enable simultaneous management of three
independent power phases, and up to eight windowed comparator subsystems (CMPSSs), allowing very fast,
direct trip of the PWMs in overvoltage or overcurrent conditions. In addition, the device has three 12-bit DACs,
and precision control peripherals such as enhanced pulse width modulators (ePWMs) with fault protection,
eQEP peripherals, and eCAP units.

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Connectivity peripherals such as dual Controller Area Network (CAN) modules (ISO 11898-1/CAN 2.0B-
compliant) and a USB 2.0 port with MAC and full-speed PHY let users add universal serial bus (USB)
connectivity to their application.
To learn more about the C2000 MCUs, visit the C2000 Overview at www.ti.com/c2000.
Device Information
PART NUMBER(1) PACKAGE BODY SIZE
TMS320F28076PTP HLQFP (176) 24.0 mm × 24.0 mm
TMS320F28075PTP HLQFP (176) 24.0 mm × 24.0 mm
TMS320F28076PZP HTQFP (100) 14.0 mm × 14.0 mm
TMS320F28075PZP HTQFP (100) 14.0 mm × 14.0 mm

(1) For more information, see Mechanical, Packaging, and Orderable Information.

Functional Block Diagram

Figure 4-1 shows the CPU system and associated peripherals.
MEMCPU1 Low-Power
Mode Control GPIO MUX
CPU1.CLA1 to CPU1 C28 CPU-1 User
CPU1.CLA1 128x16 MSG RAM
FPU Configurable
CPU1 to CPU1.CLA1 Dual PSWD DCSM
128x16 MSG RAM TMU Code OTP
Security 1K x 16 Watchdog INTOSC1
Module
+
Emulation
FLASH
CPU1 Local Shared 256K x 16
Code
Secure Memories 6x 2Kx16 Security Secure
LS0-LS5 RAMs Logic
shown in Red (ECSL) PUMP
CPU1.D0 RAM 2Kx16 OTP/Flash Main PLL INTOSC2
Wrapper
CPU1.D1 RAM 2Kx16 WD Timer
NMI-WDT External Crystal or
Oscillator
CPU Timer 0
CPU1.M0 RAM 1Kx16
CPU Timer 1
12-bit ADC CPU Timer 2 Aux PLL
A5:0 CPU1.M1 RAM 1Kx16
A x3 AUXCLKIN

B ePIE Global Shared

B3:0 (up to 192 8x 4Kx16
D ADC TRST
Analog Result
Secure-ROM 32Kx16 interrupts) GS0-GS7 RAMs
Secure TCK
D4:0 MUX Config Regs
Boot-ROM 32Kx16
CPU1.CLA1 Bus

Nonsecure JTAG TDI

ADCIN14 TMS
ADCIN15
Data Bus TDO
Bridge CPU1.CLA1 Data ROM CPU1.DMA
(4Kx16)

Comparator
DAC CPU1 Buses
Subsystem
(CMPSS) x3

Data Bus Data Bus Data Bus Data Bus

Peripheral Frame 1 Data Bus Bridge Bridge Bridge Peripheral Frame 2 Bridge Bridge

ePWM-1/../12 SCI- USB CAN- SPI-

eCAP- I2C-A/B
1/../6
eQEP-1/2/3 SDFM-1/2 A/B/C/D Ctrl / A/B A/B/C McBSP-A/B EMIF1 GPIO
(16L FIFO)
HRPWM-1/../8 (16L FIFO) PHY (32-MBOX) (16L FIFO)
EXTSYNCOUT
EPWMxB
EPWMxA

SCITXDx

CANTXx

SPISIMOx
SPISOMIx

EM1CTLx
SPICLKx

MCLKRx
SPISTEx

MCLKXx
EQEPxS
EXTSYNCIN

USBDM
SDx_Dy

SDx_Cy
EQEPxI

MDXx
USBDP

MFSRx
SCIRXDx

MFSXx

EM1Dx
EM1Ax

GPIOn
CANRXx
EQEPxB
ECAPx

EQEPxA
TZ1-TZ6

MDRx
SDAx

SCLx

GPIO MUX, Input X-BAR, Output X-BAR

Figure 4-1. Functional Block Diagram

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Table of Contents
1 Features............................................................................1 8.4 Identification............................................................160
2 Applications..................................................................... 2 8.5 Bus Architecture – Peripheral Connectivity.............161
3 Description.......................................................................2 8.6 C28x Processor...................................................... 161
4 Revision History.............................................................. 4 8.7 Control Law Accelerator..........................................163
5 Device Comparison......................................................... 5 8.8 Direct Memory Access............................................ 164
5.1 Related Products........................................................ 6 8.9 Boot ROM and Peripheral Booting..........................166
6 Terminal Configuration and Functions..........................7 8.10 Dual Code Security Module.................................. 169
6.1 Pin Diagrams.............................................................. 7 8.11 Timers................................................................... 170
6.2 Signal Descriptions................................................... 10 8.12 Nonmaskable Interrupt With Watchdog Timer
6.3 Pins With Internal Pullup and Pulldown.................... 25 (NMIWD)................................................................... 170
6.4 Pin Multiplexing.........................................................26 8.13 Watchdog.............................................................. 171
6.5 Connections for Unused Pins................................... 32 8.14 Configurable Logic Block (CLB)............................172
7 Specifications................................................................ 33 8.15 Functional Safety.................................................. 174
7.1 Absolute Maximum Ratings...................................... 33 9 Applications, Implementation, and Layout............... 176
7.2 ESD Ratings – Commercial...................................... 34 9.1 TI Reference Design............................................... 176
7.3 ESD Ratings – Automotive....................................... 34 10 Device and Documentation Support........................177
7.4 Recommended Operating Conditions.......................35 10.1 Device and Development Support Tool
7.5 Power Consumption Summary................................. 36 Nomenclature............................................................ 177
7.6 Electrical Characteristics...........................................41 10.2 Markings............................................................... 178
7.7 Thermal Resistance Characteristics......................... 42 10.3 Tools and Software............................................... 179
7.8 Thermal Design Considerations................................43 10.4 Documentation Support........................................ 181
7.9 System...................................................................... 44 10.5 Support Resources............................................... 181
7.10 Analog Peripherals..................................................79 10.6 Trademarks........................................................... 182
7.11 Control Peripherals............................................... 104 10.7 Electrostatic Discharge Caution............................182
7.12 Communications Peripherals................................ 123 10.8 Glossary................................................................182
8 Detailed Description....................................................151 11 Mechanical, Packaging, and Orderable
8.1 Overview................................................................. 151 Information.................................................................. 183
8.2 Functional Block Diagram....................................... 151 11.1 Packaging Information.......................................... 183
8.3 Memory................................................................... 153

4 Revision History
Changes from June 25, 2020 to January 15, 2021 (from Revision I (June 2020) to Revision J
(January 2021)) Page
• Device Comparison: Updated part numbers.......................................................................................................5
• ESD Ratings – Commercial: Updated part numbers........................................................................................ 34
• ESD Ratings – Automotive: Updated part numbers......................................................................................... 34

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5 Device Comparison
Table 5-1 lists the features of each 2807x device.
Table 5-1. Device Comparison
28076 28075
FEATURE(1)
28076-Q1 28075-Q1
Package Type (PTP is an HLQFP package. PZP is an HTQFP package.) 176-Pin PTP 100-Pin PZP 176-Pin PTP 100-Pin PZP
Processor and Accelerators
Number 1
Frequency (MHz) 120
C28x
Floating-Point Unit (FPU) Yes
TMU – Type 0 Yes
Number 1
CLA – Type 1
Frequency (MHz) 120
6-Channel Direct Memory Access (DMA) – Type 0 1
Memory
Flash (16-bit words) 512KB (256KW)
Dedicated and Local Shared RAM 36KB (18KW)
RAM (16-bit words) Global Shared RAM 64KB (32KW)
Total RAM 100KB (50KW)
Code security for on-chip flash, RAM, and OTP blocks Yes
Boot ROM Yes
System
Configurable Logic Block (CLB) 4 tiles No
32-bit CPU timers 3
Watchdog timers 1
Nonmaskable Interrupt Watchdog (NMIWD) timers 1
Crystal oscillator/External clock input 1
0-pin internal oscillator 2
I/O pins GPIO 97 41 97 41
External interrupts 5
EMIF EMIF1 (16-bit or 32-bit) 1 – 1 –
Analog Peripherals
MSPS 3.1
ADC 12-bit mode Conversion Time (ns)(2) 325
Input pins 17 14 17 14
Number of 12-bit ADCs 3 2 3 2
Temperature sensor 1
CMPSS (each CMPSS has two comparators and two internal DACs) 8 4 8 4
Buffered DAC 3

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Table 5-1. Device Comparison (continued)

28076 28075
FEATURE(1)
28076-Q1 28075-Q1
Package Type (PTP is an HLQFP package. PZP is an HTQFP package.) 176-Pin PTP 100-Pin PZP 176-Pin PTP 100-Pin PZP
Control Peripherals (3)
eCAP inputs – Type 0 6
ePWM channels – Type 4 24 15 24 15
eQEP modules – Type 0 3 2 3 2
High-resolution ePWM channels – Type 4 16 9 16 9
Sigma-Delta Filter Module (SDFM) channels 8 6 8 6
Communication Peripherals (3)
Controller Area Network (CAN) – Type 0(4) 2
Inter-Integrated Circuit (I2C) – Type 0 2
Multichannel Buffered Serial Port (McBSP) – Type 1 2
SCI – Type 0 4 3 4 3
Serial Peripheral Interface (SPI) – Type 2 3
Universal Serial Bus (USB) – Type 0 1
Temperature and Qualification
T: –40°C to 105°C No Yes
Junction Temperature (TJ) S: –40°C to 125°C Yes
Q: –40°C to 150°C(5) No Yes
Free-Air Temperature (TA) Q: –40°C to 125°C(5) No Yes

(1) A type change represents a major functional feature difference in a peripheral module. Within a peripheral type, there may be minor
differences between devices that do not affect the basic functionality of the module. For more information, see the C2000 Real-Time
Control Peripherals Reference Guide.
(2) Time between start of sample-and-hold window to start of sample-and-hold window of the next conversion.
(3) For devices that are available in more than one package, the peripheral count listed in the smaller package is reduced because the
smaller package has less device pins available. The number of peripherals internally present on the device is not reduced compared to
the largest package offered within a part number. See Section 6 to identify which peripheral instances are accessible on pins in the
smaller package.
(4) The CAN module uses the IP known as D_CAN. This document uses the names CAN and D_CAN interchangeably to reference this
peripheral.
(5) The letter Q refers to AEC Q100 qualification for automotive applications.

5.1 Related Products

For information about similar products, see the following links:
TMS320F2807x Microcontrollers
The F2807x series offers the most performance, largest pin counts, flash memory sizes, and peripheral options.
The F2807x series includes the latest generation of accelerators, ePWM peripherals, and analog technology.
TMS320F28004x Microcontrollers
The F28004x series is a reduced version of the F2807x series with the latest generational enhancements. The
F28004x series is the best roadmap option for those using the F2806x series. InstaSPIN-FOC and configurable
logic block (CLB) versions are available.

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6 Terminal Configuration and Functions

6.1 Pin Diagrams
Figure 6-1 shows the pin assignments on the 176-pin PTP PowerPAD Thermally Enhanced Low-Profile Quad
Flatpack. Figure 6-2 shows the pin assignments on the 100-pin PZP PowerPAD Thermally Enhanced Thin Quad
Flatpack.

ERRORSTS
VREGENZ
GPIO133
VDDOSC

VDDOSC
VSSOSC
GPIO67
GPIO43
GPIO42
GPIO47
GPIO46

GPIO45

GPIO44
GPIO66
GPIO65
GPIO64
GPIO63
GPIO62
GPIO61

GPIO60
GPIO59
GPIO58
GPIO57
GPIO56
GPIO55

GPIO54
GPIO53
GPIO52
GPIO51
GPIO50
GPIO49

GPIO48
GPIO41
VDDIO

VDDIO

VDDIO

VDDIO

VDDIO

VDDIO
XRS
VDD

VDD
X1

X2
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
GPIO68 133 88 VDDIO
GPIO69 134 87 GPIO40
GPIO70 135 86 GPIO39
GPIO71 136 85 GPIO38
VDD 137 84 GPIO37
VDDIO 138 83 GPIO36
GPIO72 139 82 VDDIO
GPIO73 140 81 TCK
GPIO74 141 80 TMS
GPIO75 142 79 TRST
GPIO76 143 78 TDO
GPIO77 144 77 TDI
GPIO78 145 76 VDD
GPIO79 146 75 VDDIO
VDDIO 147 74 FLT2
GPIO80 148 73 FLT1
GPIO81 149 72 VDD3VFL
GPIO82 150 71 GPIO35
GPIO83 151 70 GPIO34
VDDIO 152 69 GPIO33
VDD 153 68 VDDIO
GPIO84 154 67 GPIO32
GPIO85 155 66 GPIO31
GPIO86 156 65 GPIO29
GPIO87 157 64 GPIO28
VDD 158 63 GPIO30
VDDIO 159 62 VDDIO
GPIO0 160 61 VDD
GPIO1 161 60 ADCIND4
GPIO2 162 59 ADCIND3
GPIO3 163 58 ADCIND2
GPIO4 164 57 ADCIND1
GPIO5 165 56 ADCIND0
GPIO6 166 55 VREFHID
GPIO7 167 54 VDDA
VDDIO 168 53 VREFHIB
VDD 169 52 VSSA
GPIO88 170 51 VREFLOD
GPIO89 171 50 VREFLOB
GPIO90 172 49 ADCINB3
GPIO91 173 48 ADCINB2
GPIO92 174 47 ADCINB1
GPIO93 175 46 ADCINB0
GPIO94 176 45 ADCIN15
10
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
11
1
2
3
4
5
6
7
8
9
GPIO11

GPIO21

ADCINA1
CMPIN6N
GPIO12

GPIO22

ADCINA2
GPIO10

GPIO14

GPIO20

VDD

VDD

GPIO24

ADCINA4

ADCINA0
ADCIN14
GPIO13

GPIO16
GPIO17

GPIO26
GPIO27
GPIO18

GPIO19

GPIO99
GPIO8

GPIO23
GPIO9

ADCINA3
CMPIN5P

CMPIN6P
VDDIO

GPIO15

VDDIO

VDDIO

VDDIO

GPIO25
VDDIO

ADCINA5
VSSA
VREFLOA
VSSA
VDDA
VDDA
VREFHIA

A. Only the GPIO function is shown on GPIO pins. See Section 6.2.1 for the complete, muxed signal name.

Figure 6-1. 176-Pin PTP PowerPAD Thermally Enhanced Low-Profile Quad Flatpack (Top View)

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VREGENZ
GPIO69
GPIO43
GPIO42

GPIO66
GPIO65
GPIO64
GPIO63
GPIO62
GPIO61

GPIO60
GPIO59
GPIO58
GPIO41
VDDOSC

VDDOSC
VSSOSC
VDDIO

VDDIO

VDDIO
XRS
VDD

VDD
X1

X2
71

61

51
72

62

52
74

70

64
73

66

60

54
69
68
67

63

56

53
59
58
57
75

65

55
GPIO70 76 50 TCK
GPIO71 77 49 TMS
VDD 78 48 TRST
VDDIO 79 47 TDO
GPIO72 80 46 TDI
GPIO73 81 45 VDD
GPIO78 82 44 VDDIO
VDDIO 83 43 FLT2
VDD 84 42 FLT1
GPIO84 85 41 VDD3VFL
GPIO85 86 40 VDDIO
GPIO86 87 39 VDD
GPIO87 88 38 VDDA
VDD 89 37 VREFHIB
VDDIO 90 36 VSSA
GPIO2 91 35 VSSA
GPIO3 92 34 VREFLOB
GPIO4 93 33 ADCINB5
VDDIO 94 32 ADCINB4
VDD 95 31 ADCINB3
GPIO89 96 30 ADCINB2
GPIO90 97 29 ADCINB1
GPIO91 98 28 ADCINB0
GPIO92 99 27 ADCIN15
GPIO10 100 26 ADCIN14
10

12
13
14
15
16
17
18
19
20
21
22
23
24
25
11
1
2
3
4
5
6
7
8
9
GPIO11

GPIO21

ADCINA1
GPIO12

ADCINA2
GPIO14

GPIO20

ADCINA4

ADCINA0
GPIO13

GPIO16
GPIO17
GPIO18

GPIO19

GPIO99

ADCINA3
VDD
GPIO15

ADCINA5
VDDIO

VDDIO

VDDIO

VSSA/VREFLOA
VDDA
VREFHIA

A. Only the GPIO function is shown on GPIO pins. See Section 6.2.1 for the complete, muxed signal name.

Figure 6-2. 100-Pin PZP PowerPAD HTQFP (Top View)

Note
The exposed lead frame die pad of the PowerPAD™ package serves two functions: to remove heat
from the die and to provide ground path for the digital ground (analog ground is provided through
dedicated pins). Thus, the PowerPAD should be soldered to the ground (GND) plane of the PCB
because this will provide both the digital ground path and good thermal conduction path. To make
optimum use of the thermal efficiencies designed into the PowerPAD package, the PCB must be
designed with this technology in mind. A thermal land is required on the surface of the PCB directly
underneath the body of the PowerPAD. The thermal land should be soldered to the exposed lead
frame die pad of the PowerPAD package; the thermal land should be as large as needed to dissipate
the required heat. An array of thermal vias should be used to connect the thermal pad to the internal
GND plane of the board. See PowerPAD™ Thermally Enhanced Package for more details on using
the PowerPAD package.

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Note
PCB footprints and schematic symbols are available for download in a vendor-neutral format, which
can be exported to the leading EDA CAD/CAE design tools. See the CAD/CAE Symbols section in the
product folder for each device, under the Packaging section. These footprints and symbols can also
be searched for at http://webench.ti.com/cad/.

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6.2 Signal Descriptions

Section 6.2.1 describes the signals. The GPIO function is the default at reset, unless otherwise mentioned. The
peripheral signals that are listed under them are alternate functions. Some peripheral functions may not be
available in all devices. See Table 5-1 for details. All GPIO pins are I/O/Z and have an internal pullup, which can
be selectively enabled or disabled on a per-pin basis. This feature only applies to the GPIO pins. The pullups are
not enabled at reset.
6.2.1 Signal Descriptions
TERMINAL
PTP PZP I/O/Z
(1)
DESCRIPTION
MUX
NAME PIN PIN
POSITION
NO. NO.
ADC, DAC, AND COMPARATOR SIGNALS
ADC-A high reference. This voltage must be driven into the
pin from external circuitry. Place at least a 1-µF capacitor on
VREFHIA 37 19 I this pin. This capacitor should be placed as close to the
device as possible between the VREFHIA and VREFLOA pins.
NOTE: Do not load this pin externally.
ADC-B high reference. This voltage must be driven into the
pin from external circuitry. Place at least a 1-µF capacitor on
VREFHIB 53 37 I this pin. This capacitor should be placed as close to the
device as possible between the VREFHIB and VREFLOB pins.
NOTE: Do not load this pin externally.
ADC-D high reference. This voltage must be driven into the
pin from external circuitry. Place at least a 1-µF capacitor on
VREFHID 55 – I this pin. This capacitor should be placed as close to the
device as possible between the VREFHID and VREFLOD pins.
NOTE: Do not load this pin externally.
ADC-A low reference.
On the PZP package, pin 17 is double-bonded to VSSA and
VREFLOA 33 17 I
VREFLOA. On the PZP package, pin 17 must be connected to
VSSA on the system board.
VREFLOB 50 34 I ADC-B low reference
VREFLOD 51 – I ADC-D low reference
ADCIN14 I Input 14 to all ADCs. This pin can be used as a general-
purpose ADCIN pin or it can be used to calibrate all ADCs
44 26 together from an external reference.
CMPIN4P I Comparator 4 positive input
ADCIN15 I Input 15 to all ADCs. This pin can be used as a general-
purpose ADCIN pin or it can be used to calibrate all ADCs
45 27 together from an external reference.
CMPIN4N I Comparator 4 negative input
ADCINA0 I ADC-A input 0. There is a 50-kΩ internal pulldown on this pin
in both an ADC input or DAC output mode which cannot be
43 25 disabled.
DACOUTA O DAC-A output
ADCINA1 I ADC-A input 1. There is a 50-kΩ internal pulldown on this pin
in both an ADC input or DAC output mode which cannot be
42 24 disabled.
DACOUTB O DAC-B output
ADCINA2 I ADC-A input 2
41 23
CMPIN1P I Comparator 1 positive input
ADCINA3 I ADC-A input 3
40 22
CMPIN1N I Comparator 1 negative input
ADCINA4 I ADC-A input 4
39 21
CMPIN2P I Comparator 2 positive input

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TERMINAL
PTP PZP I/O/Z
(1)
DESCRIPTION
MUX
NAME PIN PIN
POSITION
NO. NO.
ADCINA5 I ADC-A input 5
38 20
CMPIN2N I Comparator 2 negative input
ADCINB0 I ADC-B input 0. There is a 100-pF capacitor to VSSA on this pin
in both ADC input or DAC reference mode which cannot be
disabled. If this pin is being used as a reference for the on-
chip DACs, place at least a 1-µF capacitor on this pin.
VDAC 46 28 I Optional external reference voltage for on-chip DACs. There is
a 100-pF capacitor to VSSA on this pin in both ADC input or
DAC reference mode which cannot be disabled. If this pin is
being used as a reference for the on-chip DACs, place at least
a 1-µF capacitor on this pin.
ADCINB1 I ADC-B input 1. There is a 50-kΩ internal pulldown on this pin
in both an ADC input or DAC output mode which cannot be
47 29 disabled.
DACOUTC O DAC-C output
ADCINB2 I ADC-B input 2
48 30
CMPIN3P I Comparator 3 positive input
ADCINB3 I ADC-B input 3
49 31
CMPIN3N I Comparator 3 negative input
ADCINB4 – 32 I ADC-B input 4
ADCINB5 – 33 I ADC-B input 5
CMPIN6P 31 – I Comparator 6 positive input
CMPIN6N 30 – I Comparator 6 negative input
CMPIN5P 29 – I Comparator 5 positive input
ADCIND0 I ADC-D input 0
56 –
CMPIN7P I Comparator 7 positive input
ADCIND1 I ADC-D input 1
57 –
CMPIN7N I Comparator 7 negative input
ADCIND2 I ADC-D input 2
58 –
CMPIN8P I Comparator 8 positive input
ADCIND3 I ADC-D input 3
59 –
CMPIN8N I Comparator 8 negative input
ADCIND4 60 – I ADC-D input 4
GPIO AND PERIPHERAL SIGNALS
GPIO0 0, 4, 8, 12 I/O General-purpose input/output 0
EPWM1A 1 160 – O Enhanced PWM1 output A (HRPWM-capable)
SDAA 6 I/OD I2C-A data open-drain bidirectional port
GPIO1 0, 4, 8, 12 I/O General-purpose input/output 1
EPWM1B 1 O Enhanced PWM1 output B (HRPWM-capable)
161 –
MFSRB 3 I/O McBSP-B receive frame synch
SCLA 6 I/OD I2C-A clock open-drain bidirectional port
GPIO2 0, 4, 8, 12 I/O General-purpose input/output 2
EPWM2A 1 O Enhanced PWM2 output A (HRPWM-capable)
162 91
OUTPUTXBAR1 5 O Output 1 of the output XBAR
SDAB 6 I/OD I2C-B data open-drain bidirectional port

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TERMINAL
PTP PZP I/O/Z
(1)
DESCRIPTION
MUX
NAME PIN PIN
POSITION
NO. NO.
GPIO3 0, 4, 8, 12 I/O General-purpose input/output 3
EPWM2B 1 O Enhanced PWM2 output B (HRPWM-capable)
OUTPUTXBAR2 2 O Output 2 of the output XBAR
163 92
MCLKRB 3 I/O McBSP-B receive clock
OUTPUTXBAR2 5 O Output 2 of the output XBAR
SCLB 6 I/OD I2C-B clock open-drain bidirectional port
GPIO4 0, 4, 8, 12 I/O General-purpose input/output 4
EPWM3A 1 O Enhanced PWM3 output A (HRPWM-capable)
164 93
OUTPUTXBAR3 5 O Output 3 of the output XBAR
CANTXA 6 O CAN-A transmit
GPIO5 0, 4, 8, 12 I/O General-purpose input/output 5
EPWM3B 1 O Enhanced PWM3 output B (HRPWM-capable)
MFSRA 2 165 – I/O McBSP-A receive frame synch
OUTPUTXBAR3 3 O Output 3 of the output XBAR
CANRXA 6 I CAN-A receive
GPIO6 0, 4, 8, 12 I/O General-purpose input/output 6
EPWM4A 1 O Enhanced PWM4 output A (HRPWM-capable)
OUTPUTXBAR4 2 O Output 4 of the output XBAR
166 –
EXTSYNCOUT 3 O External ePWM synch pulse output
EQEP3A 5 I Enhanced QEP3 input A
CANTXB 6 O CAN-B transmit
GPIO7 0, 4, 8, 12 I/O General-purpose input/output 7
EPWM4B 1 O Enhanced PWM4 output B (HRPWM-capable)
MCLKRA 2 I/O McBSP-A receive clock
167 –
OUTPUTXBAR5 3 O Output 5 of the output XBAR
EQEP3B 5 I Enhanced QEP3 input B
CANRXB 6 I CAN-B receive
GPIO8 0, 4, 8, 12 I/O General-purpose input/output 8
EPWM5A 1 O Enhanced PWM5 output A (HRPWM-capable)
CANTXB 2 O CAN-B transmit
18 –
ADCSOCAO 3 O ADC start-of-conversion A output for external ADC
EQEP3S 5 I/O Enhanced QEP3 strobe
SCITXDA 6 O SCI-A transmit data
GPIO9 0, 4, 8, 12 I/O General-purpose input/output 9
EPWM5B 1 O Enhanced PWM5 output B (HRPWM-capable)
SCITXDB 2 O SCI-B transmit data
19 –
OUTPUTXBAR6 3 O Output 6 of the output XBAR
EQEP3I 5 I/O Enhanced QEP3 index
SCIRXDA 6 I SCI-A receive data
GPIO10 0, 4, 8, 12 I/O General-purpose input/output 10
EPWM6A 1 O Enhanced PWM6 output A (HRPWM-capable)
CANRXB 2 I CAN-B receive
1 100
ADCSOCBO 3 O ADC start-of-conversion B output for external ADC
EQEP1A 5 I Enhanced QEP1 input A
SCITXDB 6 O SCI-B transmit data

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TERMINAL
PTP PZP I/O/Z
(1)
DESCRIPTION
MUX
NAME PIN PIN
POSITION
NO. NO.
GPIO11 0, 4, 8, 12 I/O General-purpose input/output 11
EPWM6B 1 O Enhanced PWM6 output B (HRPWM-capable)
SCIRXDB 2, 6 2 1 I SCI-B receive data
OUTPUTXBAR7 3 O Output 7 of the output XBAR
EQEP1B 5 I Enhanced QEP1 input B
GPIO12 0, 4, 8, 12 I/O General-purpose input/output 12
EPWM7A 1 O Enhanced PWM7 output A (HRPWM-capable)
CANTXB 2 O CAN-B transmit
4 3
MDXB 3 O McBSP-B transmit serial data
EQEP1S 5 I/O Enhanced QEP1 strobe
SCITXDC 6 O SCI-C transmit data
GPIO13 0, 4, 8, 12 I/O General-purpose input/output 13
EPWM7B 1 O Enhanced PWM7 output B (HRPWM-capable)
CANRXB 2 I CAN-B receive
5 4
MDRB 3 I McBSP-B receive serial data
EQEP1I 5 I/O Enhanced QEP1 index
SCIRXDC 6 I SCI-C receive data
GPIO14 0, 4, 8, 12 I/O General-purpose input/output 14
EPWM8A 1 O Enhanced PWM8 output A (HRPWM-capable)
SCITXDB 2 6 5 O SCI-B transmit data
MCLKXB 3 I/O McBSP-B transmit clock
OUTPUTXBAR3 6 O Output 3 of the output XBAR
GPIO15 0, 4, 8, 12 I/O General-purpose input/output 15
EPWM8B 1 O Enhanced PWM8 output B (HRPWM-capable)
SCIRXDB 2 7 6 I SCI-B receive data
MFSXB 3 I/O McBSP-B transmit frame synch
OUTPUTXBAR4 6 O Output 4 of the output XBAR
GPIO16 0, 4, 8, 12 I/O General-purpose input/output 16
SPISIMOA 1 I/O SPI-A slave in, master out
CANTXB 2 O CAN-B transmit
8 7
OUTPUTXBAR7 3 O Output 7 of the output XBAR
EPWM9A 5 O Enhanced PWM9 output A
SD1_D1 7 I Sigma-Delta 1 channel 1 data input
GPIO17 0, 4, 8, 12 I/O General-purpose input/output 17
SPISOMIA 1 I/O SPI-A slave out, master in
CANRXB 2 I CAN-B receive
9 8
OUTPUTXBAR8 3 O Output 8 of the output XBAR
EPWM9B 5 O Enhanced PWM9 output B
SD1_C1 7 I Sigma-Delta 1 channel 1 clock input
GPIO18 0, 4, 8, 12 I/O General-purpose input/output 18
SPICLKA 1 I/O SPI-A clock
SCITXDB 2 O SCI-B transmit data
10 9
CANRXA 3 I CAN-A receive
EPWM10A 5 O Enhanced PWM10 output A
SD1_D2 7 I Sigma-Delta 1 channel 2 data input

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TERMINAL
PTP PZP I/O/Z
(1)
DESCRIPTION
MUX
NAME PIN PIN
POSITION
NO. NO.
GPIO19 0, 4, 8, 12 I/O General-purpose input/output 19
SPISTEA 1 I/O SPI-A slave transmit enable
SCIRXDB 2 I SCI-B receive data
12 11
CANTXA 3 O CAN-A transmit
EPWM10B 5 O Enhanced PWM10 output B
SD1_C2 7 I Sigma-Delta 1 channel 2 clock input
GPIO20 0, 4, 8, 12 I/O General-purpose input/output 20
EQEP1A 1 I Enhanced QEP1 input A
MDXA 2 O McBSP-A transmit serial data
13 12
CANTXB 3 O CAN-B transmit
EPWM11A 5 O Enhanced PWM11 output A
SD1_D3 7 I Sigma-Delta 1 channel 3 data input
GPIO21 0, 4, 8, 12 I/O General-purpose input/output 21
EQEP1B 1 I Enhanced QEP1 input B
MDRA 2 I McBSP-A receive serial data
14 13
CANRXB 3 I CAN-B receive
EPWM11B 5 O Enhanced PWM11 output B
SD1_C3 7 I Sigma-Delta 1 channel 3 clock input
GPIO22 0, 4, 8, 12 I/O General-purpose input/output 22
EQEP1S 1 I/O Enhanced QEP1 strobe
MCLKXA 2 I/O McBSP-A transmit clock
SCITXDB 3 22 – O SCI-B transmit data
EPWM12A 5 O Enhanced PWM12 output A
SPICLKB 6 I/O SPI-B clock
SD1_D4 7 I Sigma-Delta 1 channel 4 data input
GPIO23 0, 4, 8, 12 I/O General-purpose input/output 23
EQEP1I 1 I/O Enhanced QEP1 index
MFSXA 2 I/O McBSP-A transmit frame synch
SCIRXDB 3 23 – I SCI-B receive data
EPWM12B 5 O Enhanced PWM12 output B
SPISTEB 6 I/O SPI-B slave transmit enable
SD1_C4 7 I Sigma-Delta 1 channel 4 clock input
GPIO24 0, 4, 8, 12 I/O General-purpose input/output 24
OUTPUTXBAR1 1 O Output 1 of the output XBAR
EQEP2A 2 I Enhanced QEP2 input A
24 –
MDXB 3 O McBSP-B transmit serial data
SPISIMOB 6 I/O SPI-B slave in, master out
SD2_D1 7 I Sigma-Delta 2 channel 1 data input
GPIO25 0, 4, 8, 12 I/O General-purpose input/output 25
OUTPUTXBAR2 1 O Output 2 of the output XBAR
EQEP2B 2 I Enhanced QEP2 input B
25 –
MDRB 3 I McBSP-B receive serial data
SPISOMIB 6 I/O SPI-B slave out, master in
SD2_C1 7 I Sigma-Delta 2 channel 1 clock input

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TERMINAL
PTP PZP I/O/Z
(1)
DESCRIPTION
MUX
NAME PIN PIN
POSITION
NO. NO.
GPIO26 0, 4, 8, 12 I/O General-purpose input/output 26
OUTPUTXBAR3 1 O Output 3 of the output XBAR
EQEP2I 2 I/O Enhanced QEP2 index
MCLKXB 3 27 – I/O McBSP-B transmit clock
OUTPUTXBAR3 5 O Output 3 of the output XBAR
SPICLKB 6 I/O SPI-B clock
SD2_D2 7 I Sigma-Delta 2 channel 2 data input
GPIO27 0, 4, 8, 12 I/O General-purpose input/output 27
OUTPUTXBAR4 1 O Output 4 of the output XBAR
EQEP2S 2 I/O Enhanced QEP2 strobe
MFSXB 3 28 – I/O McBSP-B transmit frame synch
OUTPUTXBAR4 5 O Output 4 of the output XBAR
SPISTEB 6 I/O SPI-B slave transmit enable
SD2_C2 7 I Sigma-Delta 2 channel 2 clock input
GPIO28 0, 4, 8, 12 I/O General-purpose input/output 28
SCIRXDA 1 I SCI-A receive data
EM1CS4 2 O External memory interface 1 chip select 4
64 –
OUTPUTXBAR5 5 O Output 5 of the output XBAR
EQEP3A 6 I Enhanced QEP3 input A
SD2_D3 7 I Sigma-Delta 2 channel 3 data input
GPIO29 0, 4, 8, 12 I/O General-purpose input/output 29
SCITXDA 1 O SCI-A transmit data
EM1SDCKE 2 O External memory interface 1 SDRAM clock enable
65 –
OUTPUTXBAR6 5 O Output 6 of the output XBAR
EQEP3B 6 I Enhanced QEP3 input B
SD2_C3 7 I Sigma-Delta 2 channel 3 clock input
GPIO30 0, 4, 8, 12 I/O General-purpose input/output 30
CANRXA 1 I CAN-A receive
EM1CLK 2 O External memory interface 1 clock
63 –
OUTPUTXBAR7 5 O Output 7 of the output XBAR
EQEP3S 6 I/O Enhanced QEP3 strobe
SD2_D4 7 I Sigma-Delta 2 channel 4 data input
GPIO31 0, 4, 8, 12 I/O General-purpose input/output 31
CANTXA 1 O CAN-A transmit
EM1WE 2 O External memory interface 1 write enable
66 –
OUTPUTXBAR8 5 O Output 8 of the output XBAR
EQEP3I 6 I/O Enhanced QEP3 index
SD2_C4 7 I Sigma-Delta 2 channel 4 clock input
GPIO32 0, 4, 8, 12 I/O General-purpose input/output 32
SDAA 1 67 – I/OD I2C-A data open-drain bidirectional port
EM1CS0 2 O External memory interface 1 chip select 0
GPIO33 0, 4, 8, 12 I/O General-purpose input/output 33
SCLA 1 69 – I/OD I2C-A clock open-drain bidirectional port
EM1RNW 2 O External memory interface 1 read not write

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TERMINAL
PTP PZP I/O/Z
(1)
DESCRIPTION
MUX
NAME PIN PIN
POSITION
NO. NO.
GPIO34 0, 4, 8, 12 I/O General-purpose input/output 34
OUTPUTXBAR1 1 O Output 1 of the output XBAR
70 –
EM1CS2 2 O External memory interface 1 chip select 2
SDAB 6 I/OD I2C-B data open-drain bidirectional port
GPIO35 0, 4, 8, 12 I/O General-purpose input/output 35
SCIRXDA 1 I SCI-A receive data
71 –
EM1CS3 2 O External memory interface 1 chip select 3
SCLB 6 I/OD I2C-B clock open-drain bidirectional port
GPIO36 0, 4, 8, 12 I/O General-purpose input/output 36
SCITXDA 1 O SCI-A transmit data
83 –
EM1WAIT 2 I External memory interface 1 Asynchronous SRAM WAIT
CANRXA 6 I CAN-A receive
GPIO37 0, 4, 8, 12 I/O General-purpose input/output 37
OUTPUTXBAR2 1 O Output 2 of the output XBAR
84 –
EM1OE 2 O External memory interface 1 output enable
CANTXA 6 O CAN-A transmit
GPIO38 0, 4, 8, 12 I/O General-purpose input/output 38
EM1A0 2 O External memory interface 1 address line 0
85 –
SCITXDC 5 O SCI-C transmit data
CANTXB 6 O CAN-B transmit
GPIO39 0, 4, 8, 12 I/O General-purpose input/output 39
EM1A1 2 O External memory interface 1 address line 1
86 –
SCIRXDC 5 I SCI-C receive data
CANRXB 6 I CAN-B receive
GPIO40 0, 4, 8, 12 I/O General-purpose input/output 40
EM1A2 2 87 – O External memory interface 1 address line 2
SDAB 6 I/OD I2C-B data open-drain bidirectional port
GPIO41 0, 4, 8, 12 I/O General-purpose input/output 41. For applications using the
Hibernate low-power mode, this pin serves as the
GPIOHIBWAKE signal. For details, see the Low Power Modes
section of the System Control chapter in the TMS320F2807x
89 51
Microcontrollers Technical Reference Manual.
EM1A3 2 O External memory interface 1 address line 3
SCLB 6 I/OD I2C-B clock open-drain bidirectional port
GPIO42 0, 4, 8, 12 I/O General-purpose input/output 42
SDAA 6 I/OD I2C-A data open-drain bidirectional port
130 73
SCITXDA 15 O SCI-A transmit data
USB0DM Analog I/O USB PHY differential data
GPIO43 0, 4, 8, 12 I/O General-purpose input/output 43
SCLA 6 I/OD I2C-A clock open-drain bidirectional port
131 74
SCIRXDA 15 I SCI-A receive data
USB0DP Analog I/O USB PHY differential data
GPIO44 0, 4, 8, 12 I/O General-purpose input/output 44
113 –
EM1A4 2 O External memory interface 1 address line 4
GPIO45 0, 4, 8, 12 I/O General-purpose input/output 45
115 –
EM1A5 2 O External memory interface 1 address line 5

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TERMINAL
PTP PZP I/O/Z
(1)
DESCRIPTION
MUX
NAME PIN PIN
POSITION
NO. NO.
GPIO46 0, 4, 8, 12 I/O General-purpose input/output 46
EM1A6 2 128 – O External memory interface 1 address line 6
SCIRXDD 6 I SCI-D receive data
GPIO47 0, 4, 8, 12 I/O General-purpose input/output 47
EM1A7 2 129 – O External memory interface 1 address line 7
SCITXDD 6 O SCI-D transmit data
GPIO48 0, 4, 8, 12 I/O General-purpose input/output 48
OUTPUTXBAR3 1 O Output 3 of the output XBAR
EM1A8 2 90 – O External memory interface 1 address line 8
SCITXDA 6 O SCI-A transmit data
SD1_D1 7 I Sigma-Delta 1 channel 1 data input
GPIO49 0, 4, 8, 12 I/O General-purpose input/output 49
OUTPUTXBAR4 1 O Output 4 of the output XBAR
EM1A9 2 93 – O External memory interface 1 address line 9
SCIRXDA 6 I SCI-A receive data
SD1_C1 7 I Sigma-Delta 1 channel 1 clock input
GPIO50 0, 4, 8, 12 I/O General-purpose input/output 50
EQEP1A 1 I Enhanced QEP1 input A
EM1A10 2 94 – O External memory interface 1 address line 10
SPISIMOC 6 I/O SPI-C slave in, master out
SD1_D2 7 I Sigma-Delta 1 channel 2 data input
GPIO51 0, 4, 8, 12 I/O General-purpose input/output 51
EQEP1B 1 I Enhanced QEP1 input B
EM1A11 2 95 – O External memory interface 1 address line 11
SPISOMIC 6 I/O SPI-C slave out, master in
SD1_C2 7 I Sigma-Delta 1 channel 2 clock input
GPIO52 0, 4, 8, 12 I/O General-purpose input/output 52
EQEP1S 1 I/O Enhanced QEP1 strobe
EM1A12 2 96 – O External memory interface 1 address line 12
SPICLKC 6 I/O SPI-C clock
SD1_D3 7 I Sigma-Delta 1 channel 3 data input
GPIO53 0, 4, 8, 12 I/O General-purpose input/output 53
EQEP1I 1 I/O Enhanced QEP1 index
EM1D31 2 97 – I/O External memory interface 1 data line 31
SPISTEC 6 I/O SPI-C slave transmit enable
SD1_C3 7 I Sigma-Delta 1 channel 3 clock input
GPIO54 0, 4, 8, 12 I/O General-purpose input/output 54
SPISIMOA 1 I/O SPI-A slave in, master out
EM1D30 2 I/O External memory interface 1 data line 30
98 –
EQEP2A 5 I Enhanced QEP2 input A
SCITXDB 6 O SCI-B transmit data
SD1_D4 7 I Sigma-Delta 1 channel 4 data input

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TERMINAL
PTP PZP I/O/Z
(1)
DESCRIPTION
MUX
NAME PIN PIN
POSITION
NO. NO.
GPIO55 0, 4, 8, 12 I/O General-purpose input/output 55
SPISOMIA 1 I/O SPI-A slave out, master in
EM1D29 2 I/O External memory interface 1 data line 29
100 –
EQEP2B 5 I Enhanced QEP2 input B
SCIRXDB 6 I SCI-B receive data
SD1_C4 7 I Sigma-Delta 1 channel 4 clock input
GPIO56 0, 4, 8, 12 I/O General-purpose input/output 56
SPICLKA 1 I/O SPI-A clock
EM1D28 2 I/O External memory interface 1 data line 28
101 –
EQEP2S 5 I/O Enhanced QEP2 strobe
SCITXDC 6 O SCI-C transmit data
SD2_D1 7 I Sigma-Delta 2 channel 1 data input
GPIO57 0, 4, 8, 12 I/O General-purpose input/output 57
SPISTEA 1 I/O SPI-A slave transmit enable
EM1D27 2 I/O External memory interface 1 data line 27
102 –
EQEP2I 5 I/O Enhanced QEP2 index
SCIRXDC 6 I SCI-C receive data
SD2_C1 7 I Sigma-Delta 2 channel 1 clock input
GPIO58 0, 4, 8, 12 I/O General-purpose input/output 58
MCLKRA 1 I/O McBSP-A receive clock
EM1D26 2 I/O External memory interface 1 data line 26
OUTPUTXBAR1 5 103 52 O Output 1 of the output XBAR
SPICLKB 6 I/O SPI-B clock
SD2_D2 7 I Sigma-Delta 2 channel 2 data input
(2)
SPISIMOA 15 I/O SPI-A slave in, master out
(3)
GPIO59 0, 4, 8, 12 I/O General-purpose input/output 59
MFSRA 1 I/O McBSP-A receive frame synch
EM1D25 2 I/O External memory interface 1 data line 25
OUTPUTXBAR2 5 104 53 O Output 2 of the output XBAR
SPISTEB 6 I/O SPI-B slave transmit enable
SD2_C2 7 I Sigma-Delta 2 channel 2 clock input
(2)
SPISOMIA 15 I/O SPI-A slave out, master in
GPIO60 0, 4, 8, 12 I/O General-purpose input/output 60
MCLKRB 1 I/O McBSP-B receive clock
EM1D24 2 I/O External memory interface 1 data line 24
OUTPUTXBAR3 5 105 54 O Output 3 of the output XBAR
SPISIMOB 6 I/O SPI-B slave in, master out
SD2_D3 7 I Sigma-Delta 2 channel 3 data input
(2)
SPICLKA 15 I/O SPI-A clock

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TERMINAL
PTP PZP I/O/Z
(1)
DESCRIPTION
MUX
NAME PIN PIN
POSITION
NO. NO.
(3)
GPIO61 0, 4, 8, 12 I/O General-purpose input/output 61
MFSRB 1 I/O McBSP-B receive frame synch
EM1D23 2 I/O External memory interface 1 data line 23
OUTPUTXBAR4 5 107 56 O Output 4 of the output XBAR
SPISOMIB 6 I/O SPI-B slave out, master in
SD2_C3 7 I Sigma-Delta 2 channel 3 clock input
(2)
SPISTEA 15 I/O SPI-A slave transmit enable
GPIO62 0, 4, 8, 12 I/O General-purpose input/output 62
SCIRXDC 1 I SCI-C receive data
EM1D22 2 I/O External memory interface 1 data line 22
108 57
EQEP3A 5 I Enhanced QEP3 input A
CANRXA 6 I CAN-A receive
SD2_D4 7 I Sigma-Delta 2 channel 4 data input
GPIO63 0, 4, 8, 12 I/O General-purpose input/output 63
SCITXDC 1 O SCI-C transmit data
EM1D21 2 I/O External memory interface 1 data line 21
EQEP3B 5 109 58 I Enhanced QEP3 input B
CANTXA 6 O CAN-A transmit
SD2_C4 7 I Sigma-Delta 2 channel 4 clock input
(2)
SPISIMOB 15 I/O SPI-B slave in, master out
(3)
GPIO64 0, 4, 8, 12 I/O General-purpose input/output 64
EM1D20 2 I/O External memory interface 1 data line 20
EQEP3S 5 110 59 I/O Enhanced QEP3 strobe
SCIRXDA 6 I SCI-A receive data
(2)
SPISOMIB 15 I/O SPI-B slave out, master in
GPIO65 0, 4, 8, 12 I/O General-purpose input/output 65
EM1D19 2 I/O External memory interface 1 data line 19
EQEP3I 5 111 60 I/O Enhanced QEP3 index
SCITXDA 6 O SCI-A transmit data
(2)
SPICLKB 15 I/O SPI-B clock
(3)
GPIO66 0, 4, 8, 12 I/O General-purpose input/output 66
EM1D18 2 I/O External memory interface 1 data line 18
112 61
SDAB 6 I/OD I2C-B data open-drain bidirectional port
(2)
SPISTEB 15 I/O SPI-B slave transmit enable
GPIO67 0, 4, 8, 12 I/O General-purpose input/output 67
132 –
EM1D17 2 I/O External memory interface 1 data line 17
GPIO68 0, 4, 8, 12 I/O General-purpose input/output 68
133 –
EM1D16 2 I/O External memory interface 1 data line 16
GPIO69 0, 4, 8, 12 I/O General-purpose input/output 69
EM1D15 2 I/O External memory interface 1 data line 15
134 75
SCLB 6 I/OD I2C-B clock open-drain bidirectional port
(2)
SPISIMOC 15 I/O SPI-C slave in, master out

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TERMINAL
PTP PZP I/O/Z
(1)
DESCRIPTION
MUX
NAME PIN PIN
POSITION
NO. NO.
(3)
GPIO70 0, 4, 8, 12 I/O General-purpose input/output 70
EM1D14 2 I/O External memory interface 1 data line 14
CANRXA 5 135 76 I CAN-A receive
SCITXDB 6 O SCI-B transmit data
(2)
SPISOMIC 15 I/O SPI-C slave out, master in
GPIO71 0, 4, 8, 12 I/O General-purpose input/output 71
EM1D13 2 I/O External memory interface 1 data line 13
CANTXA 5 136 77 O CAN-A transmit
SCIRXDB 6 I SCI-B receive data
(2)
SPICLKC 15 I/O SPI-C clock
(3)
GPIO72 General-purpose input/output 72. This is the factory default
0, 4, 8, 12 I/O
boot mode select pin 1.
EM1D12 2 I/O External memory interface 1 data line 12
139 80
CANTXB 5 O CAN-B transmit
SCITXDC 6 O SCI-C transmit data
(2)
SPISTEC 15 I/O SPI-C slave transmit enable
GPIO73 0, 4, 8, 12 I/O General-purpose input/output 73
EM1D11 2 I/O External memory interface 1 data line 11
XCLKOUT 3 O/Z External clock output. This pin outputs a divided-down version
of a chosen clock signal from within the device. The clock
140 81 signal is chosen using the CLKSRCCTL3.XCLKOUTSEL bit
field while the divide ratio is chosen using the
XCLKOUTDIVSEL.XCLKOUTDIV bit field.
CANRXB 5 I CAN-B receive
SCIRXDC 6 I SCI-C receive
GPIO74 0, 4, 8, 12 I/O General-purpose input/output 74
141 –
EM1D10 2 I/O External memory interface 1 data line 10
GPIO75 0, 4, 8, 12 I/O General-purpose input/output 75
142 –
EM1D9 2 I/O External memory interface 1 data line 9
GPIO76 0, 4, 8, 12 I/O General-purpose input/output 76
EM1D8 2 143 – I/O External memory interface 1 data line 8
SCITXDD 6 O SCI-D transmit data
GPIO77 0, 4, 8, 12 I/O General-purpose input/output 77
EM1D7 2 144 – I/O External memory interface 1 data line 7
SCIRXDD 6 I SCI-D receive data
GPIO78 0, 4, 8, 12 I/O General-purpose input/output 78
EM1D6 2 145 82 I/O External memory interface 1 data line 6
EQEP2A 6 I Enhanced QEP2 input A
GPIO79 0, 4, 8, 12 I/O General-purpose input/output 79
EM1D5 2 146 – I/O External memory interface 1 data line 5
EQEP2B 6 I Enhanced QEP2 input B
GPIO80 0, 4, 8, 12 I/O General-purpose input/output 80
EM1D4 2 148 – I/O External memory interface 1 data line 4
EQEP2S 6 I/O Enhanced QEP2 strobe

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TERMINAL
PTP PZP I/O/Z
(1)
DESCRIPTION
MUX
NAME PIN PIN
POSITION
NO. NO.
GPIO81 0, 4, 8, 12 I/O General-purpose input/output 81
EM1D3 2 149 – I/O External memory interface 1 data line 3
EQEP2I 6 I/O Enhanced QEP2 index
GPIO82 0, 4, 8, 12 I/O General-purpose input/output 82
150 –
EM1D2 2 I/O External memory interface 1 data line 2
GPIO83 0, 4, 8, 12 I/O General-purpose input/output 83
151 –
EM1D1 2 I/O External memory interface 1 data line 1
General-purpose input/output 84. This is the factory default
GPIO84 0, 4, 8, 12 I/O
boot mode select pin 0.
SCITXDA 5 154 85 O SCI-A transmit data
MDXB 6 O McBSP-B transmit serial data
MDXA 15 O McBSP-A transmit serial data
GPIO85 0, 4, 8, 12 I/O General-purpose input/output 85
EM1D0 2 I/O External memory interface 1 data line 0
SCIRXDA 5 155 86 I SCI-A receive data
MDRB 6 I McBSP-B receive serial data
MDRA 15 I McBSP-A receive serial data
GPIO86 0, 4, 8, 12 I/O General-purpose input/output 86
EM1A13 2 O External memory interface 1 address line 13
EM1CAS 3 O External memory interface 1 column address strobe
156 87
SCITXDB 5 O SCI-B transmit data
MCLKXB 6 I/O McBSP-B transmit clock
MCLKXA 15 I/O McBSP-A transmit clock
GPIO87 0, 4, 8, 12 I/O General-purpose input/output 87
EM1A14 2 O External memory interface 1 address line 14
EM1RAS 3 O External memory interface 1 row address strobe
157 88
SCIRXDB 5 I SCI-B receive data
MFSXB 6 I/O McBSP-B transmit frame synch
MFSXA 15 I/O McBSP-A transmit frame synch
GPIO88 0, 4, 8, 12 I/O General-purpose input/output 88
EM1A15 2 170 – O External memory interface 1 address line 15
EM1DQM0 3 O External memory interface 1 Input/output mask for byte 0
GPIO89 0, 4, 8, 12 I/O General-purpose input/output 89
EM1A16 2 O External memory interface 1 address line 16
171 96
EM1DQM1 3 O External memory interface 1 Input/output mask for byte 1
SCITXDC 6 O SCI-C transmit data
GPIO90 0, 4, 8, 12 I/O General-purpose input/output 90
EM1A17 2 O External memory interface 1 address line 17
172 97
EM1DQM2 3 O External memory interface 1 Input/output mask for byte 2
SCIRXDC 6 I SCI-C receive data
GPIO91 0, 4, 8, 12 I/O General-purpose input/output 91
EM1A18 2 O External memory interface 1 address line 18
173 98
EM1DQM3 3 O External memory interface 1 Input/output mask for byte 3
SDAA 6 I/OD I2C-A data open-drain bidirectional port

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TERMINAL
PTP PZP I/O/Z
(1)
DESCRIPTION
MUX
NAME PIN PIN
POSITION
NO. NO.
GPIO92 0, 4, 8, 12 I/O General-purpose input/output 92
EM1A19 2 O External memory interface 1 address line 19
174 99
EM1BA1 3 O External memory interface 1 bank address 1
SCLA 6 I/OD I2C-A clock open-drain bidirectional port
GPIO93 0, 4, 8, 12 I/O General-purpose input/output 93
EM1BA0 3 175 – O External memory interface 1 bank address 0
SCITXDD 6 O SCI-D transmit data
GPIO94 0, 4, 8, 12 I/O General-purpose input/output 94
176 –
SCIRXDD 6 I SCI-D receive data
GPIO99 0, 4, 8, 12 I/O General-purpose input/output 99
17 14
EQEP1I 5 I/O Enhanced QEP1 index
GPIO133/AUXCLKIN 0, 4, 8, 12 I/O General-purpose input/output 133. The AUXCLKIN function of
this GPIO pin could be used to provide a single-ended 3.3-V
level clock signal to the Auxiliary Phase-Locked Loop
118 – (AUXPLL), whose output is used for the USB module. The
AUXCLKIN clock may also be used for the CAN module.
SD2_C2 7 I Sigma-Delta 2 channel 2 clock input
RESET
Device Reset (in) and Watchdog Reset (out). The devices
have a built-in power-on reset (POR) circuit. During a power-
on condition, this pin is driven low by the device. An external
circuit may also drive this pin to assert a device reset. This pin
is also driven low by the MCU when a watchdog reset or NMI
watchdog reset occurs. During watchdog reset, the XRS pin is
driven low for the watchdog reset duration of 512 OSCCLK
XRS 124 69 I/OD cycles. A resistor with a value from 2.2 kΩ to 10 kΩ should be
placed between XRS and VDDIO. If a capacitor is placed
between XRS and VSS for noise filtering, it should be 100 nF
or smaller. These values will allow the watchdog to properly
drive the XRS pin to VOL within 512 OSCCLK cycles when the
watchdog reset is asserted. The output buffer of this pin is an
open drain with an internal pullup. If this pin is driven by an
external device, it should be done using an open-drain device.
CLOCKS
On-chip crystal-oscillator input. To use this oscillator, a quartz
crystal must be connected across X1 and X2. If this pin is not
X1 123 68 I used, it must be tied to GND.
This pin can also be used to feed a single-ended 3.3-V level
clock. In this case, X2 is a No Connect (NC).
On-chip crystal-oscillator output. A quartz crystal may be
X2 121 66 O connected across X1 and X2. If X2 is not used, it must be left
unconnected.

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TERMINAL
PTP PZP I/O/Z
(1)
DESCRIPTION
MUX
NAME PIN PIN
POSITION
NO. NO.
JTAG
TCK 81 50 I JTAG test clock with internal pullup (see Section 7.6)
JTAG test data input (TDI) with internal pullup. TDI is clocked
TDI 77 46 I into the selected register (instruction or data) on a rising edge
of TCK.
JTAG scan out, test data output (TDO). The contents of the
TDO 78 47 O/Z selected register (instruction or data) are shifted out of TDO
(3)
on the falling edge of TCK.
JTAG test-mode select (TMS) with internal pullup. This serial
TMS 80 49 I control input is clocked into the TAP controller on the rising
edge of TCK.
JTAG test reset with internal pulldown. TRST, when driven
high, gives the scan system control of the operations of the
device. If this signal is driven low, the device operates in its
functional mode, and the test reset signals are ignored.
NOTE: TRST must be maintained low at all times during
normal device operation. An external pulldown resistor is
TRST 79 48 I required on this pin. The value of this resistor should be based
on drive strength of the debugger pods applicable to the
design. A 2.2-kΩ or smaller resistor generally offers adequate
protection. The value of the resistor is application-specific. TI
recommends that each target board be validated for proper
operation of the debugger and the application. This pin has an
internal 50-ns (nominal) glitch filter.
INTERNAL VOLTAGE REGULATOR CONTROL
Internal voltage regulator enable with internal pulldown. To
VREGENZ 119 64 I enable the 1.2-V VREG, pull low to VSS. To disable, pull high
to VDDIO.
ANALOG, DIGITAL, AND I/O POWER
16 16
21 39
61 45
1.2-V digital logic power pins. If the internal 1.2-V VREG is
76 63 used, place a decoupling capacitor near each VDD pin and
117 71 distribute 12 µF to 26 µF evenly across all VDD pins. If an
VDD external supply is used, TI recommends a minimum total
126 78 capacitance of 20 µF. The exact value of the decoupling
137 84 capacitance should be determined by your system voltage
regulation solution.
153 89
158 95
169 –
3.3-V Flash power pin. Place a minimum 0.1-µF decoupling
VDD3VFL 72 41
capacitor on each pin.
35 18
3.3-V analog power pins. Place a minimum 2.2-µF decoupling
VDDA 36 38
capacitor to VSSA on each pin.
54 –

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TERMINAL
PTP PZP I/O/Z
(1)
DESCRIPTION
MUX
NAME PIN PIN
POSITION
NO. NO.
3 2
11 10
15 15
20 40
26 44
62 55
68 62
75 72
82 79
88 83 3.3-V digital I/O power pins. Place a minimum 0.1-µF
decoupling capacitor on each pin. The exact value of the
VDDIO 91 90
decoupling capacitance should be determined by your system
99 94 voltage regulation solution.
106 –
114 –
116 –
127 –
138 –
147 –
152 –
159 –
168 –
120 65 Power pins for the 3.3-V on-chip crystal oscillator (X1 and X2)
VDDOSC and the two zero-pin internal oscillators (INTOSC). Place a
125 70 0.1-μF (minimum) decoupling capacitor on each pin.
Device ground. For Quad Flatpacks (QFPs), the PowerPAD
PWR PWR
VSS on the bottom of the package must be soldered to the ground
PAD PAD
plane of the PCB.
Crystal oscillator (X1 and X2) ground pin. When using an
external crystal, do not connect this pin to the board ground.
Instead, connect it to the ground reference of the external
VSSOSC 122 67
crystal oscillator circuit.
If an external crystal is not used, this pin may be connected to
the board ground.
32 17
Analog ground.
VSSA 34 35 On the PZP package, pin 17 is double-bonded to VSSA and
VREFLOA. This pin must be connect to VSSA.
52 36
SPECIAL FUNCTIONS
ERRORSTS 92 – O Error status output. This pin has an internal pulldown.
TEST PINS
FLT1 73 42 I/O Flash test pin 1. Reserved for TI. Must be left unconnected.
FLT2 74 43 I/O Flash test pin 2. Reserved for TI. Must be left unconnected.

(1) I = Input, O = Output, OD = Open Drain, Z = High Impedance

(2) High-Speed SPI-enabled GPIO mux option. This pin mux option is required when using the SPI in High-Speed Mode (HS_MODE = 1
in SPICCR). This mux option is still available when not using the SPI in High-Speed Mode (HS_MODE = 0 in SPICCR).
(3) This pin has output impedance that can be as low as 22 Ω. This output could have fast edges and ringing depending on the system
PCB characteristics. If this is a concern, the user should take precautions such as adding a 39Ω (10% tolerance) series termination
resistor or implement some other termination scheme. It is also recommended that a system-level signal integrity analysis be
performed with the provided IBIS models. The termination is not required if this pin is used for input function.

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6.3 Pins With Internal Pullup and Pulldown

Some pins on the device have internal pullups or pulldowns. Table 6-1 lists the pull direction and when it is
active. The pullups on GPIO pins are disabled by default and can be enabled through software. In order to avoid
any floating unbonded inputs, the Boot ROM will enable internal pullups on GPIO pins that are not bonded out in
a particular package. Other pins noted in Table 6-1 with pullups and pulldowns are always on and cannot be
disabled.
Table 6-1. Pins With Internal Pullup and Pulldown
RESET
PIN DEVICE BOOT APPLICATION SOFTWARE
( XRS = 0)
Pullup enable is application-
GPIOx Pullup disabled Pullup disabled(1)
defined
TRST Pulldown active
TCK Pullup active
TMS Pullup active
TDI Pullup active
XRS Pullup active
VREGENZ Pulldown active
ERRORSTS Pulldown active
Other pins No pullup or pulldown present

(1) Pins not bonded out in a given package will have the internal pullups enabled by the Boot ROM.

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6.4 Pin Multiplexing

6.4.1 GPIO Muxed Pins
Table 6-2 shows the GPIO muxed pins. The default for each pin is the GPIO function, secondary functions can
be selected by setting both the GPyGMUXn.GPIOz and GPyMUXn.GPIOz register bits. The GPyGMUXn
register should be configured prior to the GPyMUXn to avoid transient pulses on GPIO's from alternate mux
selections. Columns not shown and blank cells are reserved GPIO Mux settings.
Table 6-2. GPIO Muxed Pins
GPIO Mux Selection(1) (2)
GPIO Index 0, 4, 8, 12 1 2 3 5 6 7 15
GPyGMUXn. 00b, 01b,
00b 01b 11b
GPIOz = 10b, 11b
GPyMUXn.
00b 01b 10b 11b 01b 10b 11b 11b
GPIOz =
GPIO0 EPWM1A (O) SDAA (I/OD)
GPIO1 EPWM1B (O) MFSRB (I/O) SCLA (I/OD)
GPIO2 EPWM2A (O) OUTPUTXBAR1 (O) SDAB (I/OD)
GPIO3 EPWM2B (O) OUTPUTXBAR2 (O) MCLKRB (I/O) OUTPUTXBAR2 (O) SCLB (I/OD)
GPIO4 EPWM3A (O) OUTPUTXBAR3 (O) CANTXA (O)
GPIO5 EPWM3B (O) MFSRA (I/O) OUTPUTXBAR3 (O) CANRXA (I)
GPIO6 EPWM4A (O) OUTPUTXBAR4 (O) EXTSYNCOUT (O) EQEP3A (I) CANTXB (O)
GPIO7 EPWM4B (O) MCLKRA (I/O) OUTPUTXBAR5 (O) EQEP3B (I) CANRXB (I)
GPIO8 EPWM5A (O) CANTXB (O) ADCSOCAO (O) EQEP3S (I/O) SCITXDA (O)
GPIO9 EPWM5B (O) SCITXDB (O) OUTPUTXBAR6 (O) EQEP3I (I/O) SCIRXDA (I)
GPIO10 EPWM6A (O) CANRXB (I) ADCSOCBO (O) EQEP1A (I) SCITXDB (O)
GPIO11 EPWM6B (O) SCIRXDB (I) OUTPUTXBAR7 (O) EQEP1B (I) SCIRXDB (I)
GPIO12 EPWM7A (O) CANTXB (O) MDXB (O) EQEP1S (I/O) SCITXDC (O)
GPIO13 EPWM7B (O) CANRXB (I) MDRB (I) EQEP1I (I/O) SCIRXDC (I)
GPIO14 EPWM8A (O) SCITXDB (O) MCLKXB (I/O) OUTPUTXBAR3 (O)
GPIO15 EPWM8B (O) SCIRXDB (I) MFSXB (I/O) OUTPUTXBAR4 (O)
GPIO16 SPISIMOA (I/O) CANTXB (O) OUTPUTXBAR7 (O) EPWM9A (O) SD1_D1 (I)
GPIO17 SPISOMIA (I/O) CANRXB (I) OUTPUTXBAR8 (O) EPWM9B (O) SD1_C1 (I)
GPIO18 SPICLKA (I/O) SCITXDB (O) CANRXA (I) EPWM10A (O) SD1_D2 (I)
GPIO19 SPISTEA (I/O) SCIRXDB (I) CANTXA (O) EPWM10B (O) SD1_C2 (I)
GPIO20 EQEP1A (I) MDXA (O) CANTXB (O) EPWM11A (O) SD1_D3 (I)
GPIO21 EQEP1B (I) MDRA (I) CANRXB (I) EPWM11B (O) SD1_C3 (I)
GPIO22 EQEP1S (I/O) MCLKXA (I/O) SCITXDB (O) EPWM12A (O) SPICLKB (I/O) SD1_D4 (I)
GPIO23 EQEP1I (I/O) MFSXA (I/O) SCIRXDB (I) EPWM12B (O) SPISTEB (I/O) SD1_C4 (I)
GPIO24 OUTPUTXBAR1 (O) EQEP2A (I) MDXB (O) SPISIMOB (I/O) SD2_D1 (I)
GPIO25 OUTPUTXBAR2 (O) EQEP2B (I) MDRB (I) SPISOMIB (I/O) SD2_C1 (I)
GPIO26 OUTPUTXBAR3 (O) EQEP2I (I/O) MCLKXB (I/O) OUTPUTXBAR3 (O) SPICLKB (I/O) SD2_D2 (I)
GPIO27 OUTPUTXBAR4 (O) EQEP2S (I/O) MFSXB (I/O) OUTPUTXBAR4 (O) SPISTEB (I/O) SD2_C2 (I)
GPIO28 SCIRXDA (I) EM1CS4 (O) OUTPUTXBAR5 (O) EQEP3A (I) SD2_D3 (I)
GPIO29 SCITXDA (O) EM1SDCKE (O) OUTPUTXBAR6 (O) EQEP3B (I) SD2_C3 (I)
GPIO30 CANRXA (I) EM1CLK (O) OUTPUTXBAR7 (O) EQEP3S (I/O) SD2_D4 (I)
GPIO31 CANTXA (O) EM1WE (O) OUTPUTXBAR8 (O) EQEP3I (I/O) SD2_C4 (I)
GPIO32 SDAA (I/OD) EM1CS0 (O)
GPIO33 SCLA (I/OD) EM1RNW (O)
GPIO34 OUTPUTXBAR1 (O) EM1CS2 (O) SDAB (I/OD)
GPIO35 SCIRXDA (I) EM1CS3 (O) SCLB (I/OD)
GPIO36 SCITXDA (O) EM1WAIT (I) CANRXA (I)
GPIO37 OUTPUTXBAR2 (O) EM1OE (O) CANTXA (O)
GPIO38 EM1A0 (O) SCITXDC (O) CANTXB (O)
GPIO39 EM1A1 (O) SCIRXDC (I) CANRXB (I)
GPIO40 EM1A2 (O) SDAB (I/OD)
GPIO41 EM1A3 (O) SCLB (I/OD)
GPIO42 SDAA (I/OD) SCITXDA (O)

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Table 6-2. GPIO Muxed Pins (continued)

GPIO Mux Selection(1) (2)
GPIO Index 0, 4, 8, 12 1 2 3 5 6 7 15
GPyGMUXn. 00b, 01b,
00b 01b 11b
GPIOz = 10b, 11b
GPyMUXn.
00b 01b 10b 11b 01b 10b 11b 11b
GPIOz =
GPIO43 SCLA (I/OD) SCIRXDA (I)
GPIO44 EM1A4 (O)
GPIO45 EM1A5 (O)
GPIO46 EM1A6 (O) SCIRXDD (I)
GPIO47 EM1A7 (O) SCITXDD (O)
GPIO48 OUTPUTXBAR3 (O) EM1A8 (O) SCITXDA (O) SD1_D1 (I)
GPIO49 OUTPUTXBAR4 (O) EM1A9 (O) SCIRXDA (I) SD1_C1 (I)
GPIO50 EQEP1A (I) EM1A10 (O) SPISIMOC (I/O) SD1_D2 (I)
GPIO51 EQEP1B (I) EM1A11 (O) SPISOMIC (I/O) SD1_C2 (I)
GPIO52 EQEP1S (I/O) EM1A12 (O) SPICLKC (I/O) SD1_D3 (I)
GPIO53 EQEP1I (I/O) EM1D31 (I/O) SPISTEC (I/O) SD1_C3 (I)
GPIO54 SPISIMOA (I/O) EM1D30 (I/O) EQEP2A (I) SCITXDB (O) SD1_D4 (I)
GPIO55 SPISOMIA (I/O) EM1D29 (I/O) EQEP2B (I) SCIRXDB (I) SD1_C4 (I)
GPIO56 SPICLKA (I/O) EM1D28 (I/O) EQEP2S (I/O) SCITXDC (O) SD2_D1 (I)
GPIO57 SPISTEA (I/O) EM1D27 (I/O) EQEP2I (I/O) SCIRXDC (I) SD2_C1 (I)
GPIO58 MCLKRA (I/O) EM1D26 (I/O) OUTPUTXBAR1 (O) SPICLKB (I/O) SD2_D2 (I) SPISIMOA(3) (I/O)
GPIO59 MFSRA (I/O) EM1D25 (I/O) OUTPUTXBAR2 (O) SPISTEB (I/O) SD2_C2 (I) SPISOMIA(3) (I/O)
GPIO60 MCLKRB (I/O) EM1D24 (I/O) OUTPUTXBAR3 (O) SPISIMOB (I/O) SD2_D3 (I) SPICLKA(3) (I/O)
GPIO61 MFSRB (I/O) EM1D23 (I/O) OUTPUTXBAR4 (O) SPISOMIB (I/O) SD2_C3 (I) SPISTEA (3) (I/O)
GPIO62 SCIRXDC (I) EM1D22 (I/O) EQEP3A (I) CANRXA (I) SD2_D4 (I)
GPIO63 SCITXDC (O) EM1D21 (I/O) EQEP3B (I) CANTXA (O) SD2_C4 (I) SPISIMOB(3) (I/O)
GPIO64 EM1D20 (I/O) EQEP3S (I/O) SCIRXDA (I) SPISOMIB(3) (I/O)
GPIO65 EM1D19 (I/O) EQEP3I (I/O) SCITXDA (O) SPICLKB(3) (I/O)
GPIO66 EM1D18 (I/O) SDAB (I/OD) SPISTEB (3) (I/O)
GPIO67 EM1D17 (I/O)
GPIO68 EM1D16 (I/O)
GPIO69 EM1D15 (I/O) SCLB (I/OD) SPISIMOC(3) (I/O)
GPIO70 EM1D14 (I/O) CANRXA (I) SCITXDB (O) SPISOMIC(3) (I/O)
GPIO71 EM1D13 (I/O) CANTXA (O) SCIRXDB (I) SPICLKC(3) (I/O)
GPIO72 EM1D12 (I/O) CANTXB (O) SCITXDC (O) SPISTEC (3) (I/O)
GPIO73 EM1D11 (I/O) XCLKOUT (O) CANRXB (I) SCIRXDC (I)
GPIO74 EM1D10 (I/O)
GPIO75 EM1D9 (I/O)
GPIO76 EM1D8 (I/O) SCITXDD (O)
GPIO77 EM1D7 (I/O) SCIRXDD (I)
GPIO78 EM1D6 (I/O) EQEP2A (I)
GPIO79 EM1D5 (I/O) EQEP2B (I)
GPIO80 EM1D4 (I/O) EQEP2S (I/O)
GPIO81 EM1D3 (I/O) EQEP2I (I/O)
GPIO82 EM1D2 (I/O)
GPIO83 EM1D1 (I/O)
GPIO84 SCITXDA (O) MDXB (O) MDXA (O)
GPIO85 EM1D0 (I/O) SCIRXDA (I) MDRB (I) MDRA (I)
GPIO86 EM1A13 (O) EM1CAS (O) SCITXDB (O) MCLKXB (I/O) MCLKXA (I/O)
GPIO87 EM1A14 (O) EM1RAS (O) SCIRXDB (I) MFSXB (I/O) MFSXA (I/O)
GPIO88 EM1A15 (O) EM1DQM0 (O)
GPIO89 EM1A16 (O) EM1DQM1 (O) SCITXDC (O)
GPIO90 EM1A17 (O) EM1DQM2 (O) SCIRXDC (I)
GPIO91 EM1A18 (O) EM1DQM3 (O) SDAA (I/OD)
GPIO92 EM1A19 (O) EM1BA1 (O) SCLA (I/OD)
GPIO93 EM1BA0 (O) SCITXDD (O)

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Table 6-2. GPIO Muxed Pins (continued)

GPIO Mux Selection(1) (2)
GPIO Index 0, 4, 8, 12 1 2 3 5 6 7 15
GPyGMUXn. 00b, 01b,
00b 01b 11b
GPIOz = 10b, 11b
GPyMUXn.
00b 01b 10b 11b 01b 10b 11b 11b
GPIOz =
GPIO94 SCIRXDD (I)
GPIO99 EQEP1I (I/O)
GPIO133/
SD2_C2 (I)
AUXCLKIN

(1) I = Input, O = Output, OD = Open Drain

(2) GPIO Index settings of 9, 10, 11, 13, and 14 are reserved.
(3) High-Speed SPI-enabled GPIO mux option. This pin mux option is required when using the SPI in High-Speed Mode (HS_MODE = 1
in SPICCR). This mux option is still available when not using the SPI in High-Speed Mode (HS_MODE = 0 in SPICCR).

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6.4.2 Input X-BAR

The Input X-BAR is used to route any GPIO input to the ADC, eCAP, and ePWM peripherals as well as to
external interrupts (XINT) (see Figure 6-3). Table 6-3 shows the input X-BAR destinations. For details on
configuring the Input X-BAR, see the Crossbar (X-BAR) chapter of the TMS320F2807x Microcontrollers
Technical Reference Manual .
INPUT7 eCAP1
GPIO0 INPUT8 eCAP2
Asynchronous INPUT9 eCAP3
Synchronous Input X-BAR
INPUT10 eCAP4
GPIOx Sync. + Qual.
INPUT11 eCAP5
INPUT12 eCAP6

INPUT14
INPUT13
INPUT6
INPUT5
INPUT4
INPUT3
INPUT2
INPUT1
TZ1,TRIP1
XINT5 TZ2,TRIP2
XINT4 TZ3,TRIP3
CPU PIE
XINT3
CLA XINT2 TRIP4
XINT1 TRIP5
TRIP7 ePWM
ePWM TRIP8 Modules
X-BAR TRIP9
TRIP10
TRIP11
TRIP12

TRIP6
ADC ADCEXTSOC
EXTSYNCIN1 ePWM and eCAP
EXTSYNCIN2 Sync Chain

Output X-BAR

Figure 6-3. Input X-BAR

Table 6-3. Input X-BAR Destinations

INPUT DESTINATIONS
INPUT1 EPWM[TZ1,TRIP1], EPWM X-BAR, Output X-BAR
INPUT2 EPWM[TZ2,TRIP2], EPWM X-BAR, Output X-BAR
INPUT3 EPWM[TZ3,TRIP3], EPWM X-BAR, Output X-BAR
INPUT4 XINT1, EPWM X-BAR, Output X-BAR
INPUT5 XINT2, ADCEXTSOC, EXTSYNCIN1, EPWM X-BAR, Output X-BAR
INPUT6 XINT3, EPWM[TRIP6], EXTSYNCIN2, EPWM X-BAR, Output X-BAR
INPUT7 ECAP1
INPUT8 ECAP2
INPUT9 ECAP3
INPUT10 ECAP4
INPUT11 ECAP5
INPUT12 ECAP6
INPUT13 XINT4
INPUT14 XINT5

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6.4.3 Output X-BAR and ePWM X-BAR

The Output X-BAR has eight outputs which can be selected on the GPIO mux as OUTPUTXBARx. The ePWM
X-BAR has eight outputs which are connected to the TRIPx inputs of the ePWM. The sources for both the
Output X-BAR and ePWM X-BAR are shown in Figure 6-4. For details on the Output X-BAR and ePWM X-BAR,
see the Crossbar (X-BAR) chapter of the TMS320F2807x Microcontrollers Technical Reference Manual .
CTRIPOUTH
CTRIPOUTL
(Output X-BAR only)

CMPSSx
CTRIPH
CTRIPL
(ePWM X-BAR only)

ePWM and eCAP EXTSYNCOUT

Sync
OUTPUT1
OUTPUT2
ADCSOCAO ADCSOCAO OUTPUT3
Select Ckt Output OUTPUT4 GPIO
X-BAR
OUTPUT5 Mux
ADCSOCBO OUTPUT6
ADCSOCBO OUTPUT7
Select Ckt OUTPUT8

eCAPx ECAPxOUT

EVT1
EVT2
ADCx EVT3 TRIP4
EVT4 TRIP5
TRIP7 All
INPUT1 ePWM TRIP8
ePWM
INPUT2 X-BAR TRIP9
TRIP10
Modules
INPUT3
INPUT4 TRIP11
Input X-Bar TRIP12
INPUT5
INPUT6
OTHER DESTINATIONS
(see Input X-BAR)
X-BAR Flags
FLT1.COMPH (shared)
FLT1.COMPL

SDFMx
FLT4.COMPH
FLT4.COMPL

Figure 6-4. Output X-BAR and ePWM X-BAR

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6.4.4 USB Pin Muxing

Table 6-4 shows assignment of the alternate USB function mapping. These can be configured with the
GPBAMSEL register.
Table 6-4. Alternate USB Function
GPIO GPBAMSEL SETTING USB FUNCTION
GPIO42 GPBAMSEL[10] = 1b USB0DM
GPIO43 GPBAMSEL[11] = 1b USB0DP

6.4.5 High-Speed SPI Pin Muxing

The SPI module on this device has a high-speed mode. To achieve the highest possible speed, a special GPIO
configuration is used on a single GPIO mux option for each SPI. These GPIOs may also be used by the SPI
when not in high-speed mode (HS_MODE = 0).
To select the mux options that enable the SPI high-speed mode, configure the GPyGMUX and GPyMUX
registers as shown in Table 6-5.
Table 6-5. GPIO Configuration for High-Speed SPI
GPIO SPI SIGNAL MUX CONFIGURATION
SPIA
GPIO58 SPISIMOA GPBGMUX2[21:20]=11b GPBMUX2[21:20]=11b
GPIO59 SPISOMIA GPBGMUX2[23:22]=11b GPBMUX2[23:22]=11b
GPIO60 SPICLKA GPBGMUX2[25:24]=11b GPBMUX2[25:24]=11b
GPIO61 SPISTEA GPBGMUX2[27:26]=11b GPBMUX2[27:26]=11b
SPIB
GPIO63 SPISIMOB GPBGMUX2[31:30]=11b GPBMUX2[31:30]=11b
GPIO64 SPISOMIB GPCGMUX1[1:0]=11b GPCMUX1[1:0]=11b
GPIO65 SPICLKB GPCGMUX1[3:2]=11b GPCMUX1[3:2]=11b
GPIO66 SPISTEB GPCGMUX1[5:4]=11b GPCMUX1[5:4]=11b
SPIC
GPIO69 SPISIMOC GPCGMUX1[11:10]=11b GPCMUX1[11:10]=11b
GPIO70 SPISOMIC GPCGMUX1[13:12]=11b GPCMUX1[13:12]=11b
GPIO71 SPICLKC GPCGMUX1[15:14]=11b GPCMUX1[15:14]=11b
GPIO72 SPISTEC GPCGMUX1[17:16]=11b GPCMUX1[17:16]=11b

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6.5 Connections for Unused Pins

For applications that do not need to use all functions of the device, Table 6-6 lists acceptable conditioning for any
unused pins. When multiple options are listed in Table 6-6, any are acceptable. Pins not listed in Table 6-6 must
be connected according to Section 6.2.1.
Table 6-6. Connections for Unused Pins
SIGNAL NAME ACCEPTABLE PRACTICE
Analog
VREFHIx Tie to VDDA
VREFLOx Tie to VSSA
• No Connect
ADCINx • Tie to VSSA

Digital
• No connection (input mode with internal pullup enabled)
GPIOx • No connection (output mode with internal pullup disabled)
• Pullup or pulldown resistor (any value resistor, input mode, and with internal pullup disabled)

X1 Tie to VSS
X2 No Connect
• No Connect
TCK • Pullup resistor

• No Connect
TDI • Pullup resistor

TDO No Connect
TMS No Connect
TRST Pulldown resistor (2.2 kΩ or smaller)
VREGENZ Tie to VDDIO
ERRORSTS No Connect
FLT1 No Connect
FLT2 No Connect
Power and Ground
VDD All VDD pins must be connected per Section 6.2.1.
VDDA If a dedicated analog supply is not used, tie to VDDIO.
VDDIO All VDDIO pins must be connected per Section 6.2.1.
VDD3VFL Must be tied to VDDIO
VDDOSC Must be tied to VDDIO
VSS All VSS pins must be connected to board ground.
VSSA If a dedicated analog ground is not used, tie to VSS.
VSSOSC If an external crystal is not used, this pin may be connected to the board ground.

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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
MIN MAX(1) (2) UNIT
VDDIO with respect to VSS –0.3 4.6
VDD3VFL with respect to VSS –0.3 4.6
Supply voltage V
VDDOSC with respect to VSS –0.3 4.6
VDD with respect to VSS –0.3 1.5
Analog voltage VDDA with respect to VSSA –0.3 4.6 V
Input voltage VIN (3.3 V) –0.3 4.6 V
Output voltage VO –0.3 4.6 V
Digital/analog input (per pin), IIK
–20 20
(VIN < VSS/VSSA or VIN > VDDIO/VDDA)(3)
Input clamp current mA
Total for all inputs, IIKTOTAL
–20 20
(VIN < VSS/VSSA or VIN > VDDIO/VDDA)
Output current Digital output (per pin), IOUT –20 20 mA
Free-Air temperature TA –40 125 °C
Operating junction temperature TJ –40 150 °C
Storage temperature(4) Tstg –65 150 °C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Section 7.4 is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to VSS, unless otherwise noted.
(3) Continuous clamp current per pin is ±2 mA. Do not operate in this condition continuously as VDDIO/VDDA voltage may internally rise and
impact other electrical specifications.
(4) Long-term high-temperature storage or extended use at maximum temperature conditions may result in a reduction of overall device
life. For additional information, see Semiconductor and IC Package Thermal Metrics.

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7.2 ESD Ratings – Commercial

VALUE UNIT
TMS320F28076-Q1 in 176-pin PTP package
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000
V(ESD) Electrostatic discharge (ESD) Charged-device model (CDM), per JEDEC specification JESD22- ±500 V
C101 or ANSI/ESDA/JEDEC JS-002(2)
TMS320F28076-Q1 in 100-pin PZP package
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000
V(ESD) Electrostatic discharge (ESD) Charged-device model (CDM), per JEDEC specification JESD22- ±500 V
C101 or ANSI/ESDA/JEDEC JS-002(2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 ESD Ratings – Automotive

VALUE UNIT
TMS320F28075-Q1 in 176-pin PTP package
Human body model (HBM), per All pins ±2000
AEC Q100-002(1)
V(ESD) Electrostatic discharge Charged device model (CDM), All pins ±500 V
per AEC Q100-011
Corner pins on 176-pin PTP: ±750
1, 44, 45, 88, 89, 132, 133, 176
TMS320F28075-Q1 in 100-pin PZP package
Human body model (HBM), per All pins ±2000
AEC Q100-002(1)
V(ESD) Electrostatic discharge Charged device model (CDM), All pins ±500 V
per AEC Q100-011
Corner pins on 100-pin PZP: ±750
1, 25, 26, 50, 51, 75, 76, 100

(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

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7.4 Recommended Operating Conditions

MIN NOM MAX UNIT
Device supply voltage, I/O, VDDIO (1) 3.14 3.3 3.47 V
Device supply voltage, VDD 1.14 1.2 1.26 V
Supply ground, VSS 0 V
Analog supply voltage, VDDA 3.14 3.3 3.47 V
Analog ground, VSSA 0 V
T version –40 105
Junction temperature, TJ S version(2) –40 125 °C
Q version (AEC Q100 qualification)(2) –40 150
Free-Air temperature, TA Q version (AEC Q100 qualification) –40 125 °C

(1) VDDIO, VDD3VFL, and VDDOSC should be maintained within 0.3 V of each other.
(2) Operation above TJ = 105°C for extended duration will reduce the lifetime of the device. See Calculating Useful Lifetimes of Embedded
Processors for more information.

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7.5 Power Consumption Summary

Current values listed in this section are representative for the test conditions given and not the absolute
maximum possible. The actual device currents in an application will vary with application code and pin
configurations. Section 7.5.1 shows the device current consumption at 120-MHz SYSCLK. Section 7.5.2 shows
the device current consumption at 120-MHz SYSCLK with the internal VREG enabled.
7.5.1 Device Current Consumption at 120-MHz SYSCLK
IDD IDDIO (1) IDDA IDD3VFL
MODE TEST CONDITIONS
TYP(3) MAX(2) TYP(3) MAX(2) TYP(3) MAX(2) TYP(3) MAX(2)
• RAM.(4)
Code is running out of
• All I/O pins are left unconnected.
• Peripherals not active have their
Operational clocks disabled. 140 mA 295 mA 25 mA 13 mA 20 mA 33 mA 40 mA
• FLASH is read and in active state.
• XCLKOUT is enabled at SYSCLK/4.

• CPU1 is in IDLE mode.

IDLE • Flash is powered down. 50 mA 185 mA 3 mA 10 mA 10 µA 150 µA 10 µA 150 µA
• XCLKOUT is turned off.

• CPU1 is in STANDBY mode.

STANDBY • Flash is powered down. 25 mA 170 mA 3 mA 10 mA 5 µA 150 µA 10 µA 150 µA
• XCLKOUT is turned off.

• CPU1 watchdog is running.

HALT • Flash is powered down. 1.5 mA 120 mA 750 µA 2 mA 5 µA 150 µA 10 µA 150 µA
• XCLKOUT is turned off.

• CPU1.M0 and CPU1.M1 RAMs are

HIBERNATE in low-power data retention mode. 300 µA 5 mA 750 µA 2 mA 5 µA 75 µA 1 µA 50 µA

• CPU1 is running from RAM.

• All I/O pins are left unconnected.
Flash • Peripheral clocks are disabled.
97 mA 145 mA 3 mA 10 mA 10 µA 150 µA 45 mA 55 mA
Erase/Program(5) • CPU1 is performing Flash Erase and
Programming.
• XCLKOUT is turned off.

(1) IDDIO current is dependent on the electrical loading on the I/O pins.
(2) MAX: Vmax, 125°C
(3) TYP: Vnom, 30°C
(4) The following is executed in a loop on CPU1:
• All of the communication peripherals are exercised in loop-back mode: CAN-A to CAN-B; SPI-A to SPI-C; SCI-A to SCI-D; I2C-A to
I2C-B; McBSP-A to McBSP-B; USB
• ePWM1 to ePWM12 generate 400-kHz PWM output on 24 pins
• CPU TIMERs active
• DMA does 32-bit burst transfers
• CLA1 does multiply-accumulate tasks
• All ADCs perform continuous conversion
• All DACs ramp voltage up/down at 150 kHz
• CMPSS1 to CMPSS8 active
• TMU calculates a cosine
• FPU does multiply/accumulate with parallel load
(5) Brownout events during flash programming can corrupt flash data. Programming environments using alternate power sources (such as
a USB programmer) must be capable of supplying the rated current for the device and other system components with sufficient margin
to avoid supply brownout conditions.

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7.5.2 Device Current Consumption at 120-MHz SYSCLK With the Internal VREG Enabled
IDDIO (2) IDDA IDD3VFL
MODE(1) TEST CONDITIONS
TYP(4) MAX(3) TYP(4) MAX(3) TYP(4) MAX(3)
• Code is running out of RAM.(5)
• All I/O pins are left unconnected.
Operational • Peripherals not active have their clocks
disabled. 165 mA 375 mA 13 mA 25 mA 33 mA 40 mA
(RAM)
• FLASH is read and in active state.
• XCLKOUT is enabled at SYSCLK/4.

• CPU1 is in IDLE mode.

IDLE • Flash is powered down. 53 mA 200 mA 10 µA 150 µA 10 µA 150 µA
• XCLKOUT is turned off.

• CPU1 is in STANDBY mode.

STANDBY • Flash is powered down. 28 mA 185 mA 5 µA 150 µA 10 µA 150 µA
• XCLKOUT is turned off.

• CPU1 watchdog is running.

HALT • Flash is powered down. 2.25 mA 125 mA 5 µA 150 µA 10 µA 150 µA
• XCLKOUT is turned off.

• CPU1.M0 and CPU1.M1 RAMs are in low-

HIBERNATE power data retention mode. 1.2 mA 8 mA 5 µA 75 µA 1 µA 50 µA

(1) The internal voltage regulator is described in Section 7.9.1.1.

(2) IDDIO current is dependent on the electrical loading on the I/O pins.
(3) MAX: Vmax, 125°C
(4) TYP: Vnom, 30°C
(5) The following is executed in a loop on CPU1:
• All of the communication peripherals are exercised in loop-back mode: CAN-A to CAN-B; SPI-A to SPI-C; SCI-A to SCI-D; I2C-A to
I2C-B; McBSP-A to McBSP-B; USB
• ePWM1 to ePWM12 generate 400-kHz PWM output on 24 pins
• CPU TIMERs active
• DMA does 32-bit burst transfers
• CLA1 does multiply-accumulate tasks
• All ADCs perform continuous conversion
• All DACs ramp voltage up/down at 150 kHz
• CMPSS1 to CMPSS8 active
• TMU calculates a cosine
• FPU does multiply/accumulate with parallel load

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7.5.3 Current Consumption Graphs

Figure 7-1 and Figure 7-2 are a typical representation of the relationship between frequency and current
consumption/power on the device. The operational test from Section 7.5.1 was run across frequency at Vmax and
high temperature. Actual results will vary based on the system implementation and conditions.

0.5
0.45
0.4
0.35
0.3
0.25
Current (A)

0.2
0.15
0.1
0.05
0
10 20 30 40 50 60 70 80 90 100 110 120

SYSCLK (MHz)
VDD VDDIO VDDA VDD3VFL

Figure 7-1. Operational Current Versus Frequency

Power vs. Frequency

1

0.9

0.8

0.7
Power (W)

0.6

0.5

0.4

0.3

0.2

0.1

0
10 20 30 40 50 60 70 80 90 100 110 120

SYSCLK (MHz)
Power

Figure 7-2. Power Versus Frequency

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Leakage current will increase with operating temperature in a nonlinear manner. The difference in VDD current
between TYP and MAX conditions can be seen in Figure 7-3. The current consumption in HALT mode is
primarily leakage current as there is no active switching if the internal oscillator has been powered down.
Figure 7-3 shows the typical leakage current across temperature. The device was placed into HALT mode under
nominal voltage conditions.

Figure 7-3. IDD Leakage Current Versus Temperature

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7.5.4 Reducing Current Consumption

The F2807x devices provide some methods to reduce the device current consumption:
• Any one of the four low-power modes—IDLE, STANDBY, HALT, and HIBERNATE—could be entered during
idle periods in the application.
• The flash module may be powered down if the code is run from RAM.
• Disable the pullups on pins that assume an output function.
• Each peripheral has an individual clock-enable bit (PCLKCRx). Reduced current consumption may be
achieved by turning off the clock to any peripheral that is not used in a given application. Table 7-1 indicates
the typical current reduction that may be achieved by disabling the clocks using the PCLKCRx register.
• To realize the lowest VDDA current consumption in a low-power mode, see the respective analog chapter of
the TMS320F2807x Microcontrollers Technical Reference Manual to ensure each module is powered down
as well.
Table 7-1. Current on VDD Supply by Various
Peripherals (at 120 MHz)
PERIPHERAL IDD CURRENT
MODULE(1) (2) REDUCTION (mA)
ADC(3) 2.1
CAN 2.1
CLA 0.9
CMPSS(3) 0.9
CPUTIMER 0.2
DAC(3) 0.4
DMA 1.8
eCAP 0.4
EMIF1 1.8
ePWM1 to ePWM4(4) 2.8
ePWM5 to ePWM12(4) 1.1
HRPWM(4) 1.1
I2C 0.9
McBSP 1
SCI 0.6
SDFM 1.3
SPI 0.4
USB and AUXPLL at 60 MHz 14.8

(1) At Vmax and 125°C.

(2) All peripherals are disabled upon reset. Use the PCLKCRx
register to individually enable peripherals. For peripherals with
multiple instances, the current quoted is for a single module.
(3) This number represents the current drawn by the digital portion
of the ADC, CMPSS, and DAC modules.
(4) The ePWM is at /2 of SYSCLK.

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7.6 Electrical Characteristics

over recommended operating conditions (unless otherwise noted)
TEST
PARAMETER MIN TYP MAX UNIT
CONDITIONS
IOH = IOH MIN VDDIO * 0.8
VOH High-level output voltage V
IOH = –100 μA VDDIO – 0.2
IOL = IOL MAX 0.4
VOL Low-level output voltage V
IOL = 100 µA 0.2
IOH High-level output source current for all output pins –4 mA
IOL Low-level output sink current for all output pins 4 mA
GPIO0–GPIO7,
High-level input voltage GPIO42–GPIO43, VDDIO * 0.7 VDDIO + 0.3
VIH GPIO46–GPIO47 V
(3.3 V)
All other pins 2.0 VDDIO + 0.3
VIL Low-level input voltage (3.3 V) VSS – 0.3 0.8 V
VHYSTERESIS Input hysteresis 150 mV
Digital inputs with VDDIO = 3.3 V
Ipulldown Input current 120 µA
pulldown(1) VIN = VDDIO
Digital inputs with pullup VDDIO = 3.3 V
Ipullup Input current 150 µA
enabled(1) VIN = 0 V
Pullups disabled
Digital 2
0 V ≤ VIN ≤ VDDIO
Analog (except
ILEAK Pin leakage 2 µA
ADCINB0 or DACOUTx)
0 V ≤ VIN ≤ VDDA
ADCINB0 2 11(2)
DACOUTx 66
CI Input capacitance 2 pF
VDDIO-POR VDDIO power-on reset voltage 2.3 V

(1) See Table 6-1 for a list of pins with a pullup or pulldown.
(2) The MAX input leakage shown on ADCINB0 is at high temperature.

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7.7 Thermal Resistance Characteristics

7.7.1 PTP Package
°C/W(1) AIR FLOW (lfm)(2)
RΘJC Junction-to-case thermal resistance 6.97 N/A
RΘJB Junction-to-board thermal resistance 6.05 N/A
RΘJA (High k PCB) Junction-to-free air thermal resistance 17.8 0
12.8 150
RΘJMA Junction-to-moving air thermal resistance 11.4 250
10.1 500
0.11 0
0.24 150
PsiJT Junction-to-package top
0.33 250
0.42 500
6.1 0
5.5 150
PsiJB Junction-to-board
5.4 250
5.3 500

(1) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a
JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/
JEDEC standards:
• JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
• JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
(2) lfm = linear feet per minute

7.7.2 PZP Package

°C/W(1) AIR FLOW (lfm)(2)
RΘJC Junction-to-case thermal resistance 4.3 N/A
RΘJB Junction-to-board thermal resistance 5.9 N/A
RΘJA (High k PCB) Junction-to-free air thermal resistance 19.1 0
14.3 150
RΘJMA Junction-to-moving air thermal resistance 12.8 250
11.4 500
0.03 0
0.09 150
PsiJT Junction-to-package top
0.12 250
0.20 500
6.0 0
5.5 150
PsiJB Junction-to-board
5.5 250
5.3 500

(1) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a
JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/
JEDEC standards:
• JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
• JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements

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(2) lfm = linear feet per minute

7.8 Thermal Design Considerations

Based on the end application design and operational profile, the IDD and IDDIO currents could vary. Systems that
exceed the recommended maximum power dissipation in the end product may require additional thermal
enhancements. Ambient temperature (TA) varies with the end application and product design. The critical factor
that affects reliability and functionality is TJ, the junction temperature, not the ambient temperature. Hence, care
should be taken to keep TJ within the specified limits. Tcase should be measured to estimate the operating
junction temperature TJ. Tcase is normally measured at the center of the package top-side surface. The thermal
application report Semiconductor and IC Package Thermal Metrics helps to understand the thermal metrics and
definitions.

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7.9 System
7.9.1 Power Management
7.9.1.1 Internal 1.2-V VREG
The internal VREG is supplied by VDDIO and generates the 1.2 V required to power the VDD pins. Enable this
functionality by pulling the VREGENZ pin low to VSS. Although the internal VREG eliminates the need to use an
external power supply for VDD, decoupling capacitors are required on each VDD pin for VREG stability (see the
description of VDD in Section 6.2.1). Driving an external load with the internal VREG is not supported.
7.9.1.2 Power Sequencing
7.9.1.2.1 Signal Pin Requirements
Before powering the device, no voltage larger than 0.3 V above VDDIO can be applied to any digital pin, and no
voltage larger than 0.3 V above VDDA can be applied to any analog pin (including VREFHI).
7.9.1.2.2 VDDIO, VDDA, VDD3VFL, and VDDOSC Requirements
The 3.3-V supplies should be powered up together and kept within 0.3 V of each other during functional
operation.
7.9.1.2.3 VDD Requirements
When VREGENZ is tied to VSS, the VDD sequencing requirements are handled by the device.
When using an external source for VDD (VREGENZ tied to VDDIO), VDDOSC and VDD must be powered on and off
at the same time. VDDOSC should not be powered on when VDD is off. During the ramp, VDD should be kept no
more than 0.3 V above VDDIO.
For applications not powering VDDOSC and VDD at the same time, see the "INTOSC: VDDOSC Powered Without
VDD Can Cause INTOSC Frequency Drift" advisory in the TMS320F2807x MCUs Silicon Errata.
There is an internal 12.8-mA current source from VDD3VFL to VDD when the flash is active. When the flash is
active and the device is in a low-activity state (for example, a low-power mode), this internal current source can
cause VDD to rise to approximately 1.3 V . There will be zero current load to the external system VDD regulator
while in this condition. This is not an issue for most regulators; however, if the system voltage regulator requires
a minimum load for proper operation, then an external 82Ω resistor can be added to the board to ensure a
minimal current load on VDD. See the "Low-Power Modes: Power Down Flash or Maintain Minimum Device
Activity" advisory in the TMS320F2807x MCUs Silicon Errata.
7.9.1.2.4 Supply Ramp Rate
The supplies should ramp to full rail within 10 ms. Section 7.9.1.2.4.1 shows the supply ramp rate.
7.9.1.2.4.1 Supply Ramp Rate

MIN MAX UNIT

Supply ramp rate VDDIO, VDD, VDDA, VDD3VFL, VDDOSC with respect to VSS 330 105 V/s

7.9.1.2.5 Supply Supervision

An internal power-on-reset (POR) circuit keeps the I/Os in a high-impedance state during power up. External
supply voltage supervisors (SVS) can be used to monitor the voltage on the 3.3-V and 1.2-V rails and drive XRS
low when supplies are outside operational specifications.

Note
If the supply voltage is held near the POR threshold, then the device may drive periodic resets onto
the XRS pin.

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7.9.2 Reset Timing

XRS is the device reset pin. It functions as an input and open-drain output. The device has a built-in power-on
reset (POR). During power up, the POR circuit drives the XRS pin low. A watchdog or NMI watchdog reset also
drives the pin low. An external circuit may drive the pin to assert a device reset.
A resistor with a value from 2.2 kΩ to 10 kΩ should be placed between XRS and VDDIO. A capacitor should be
placed between XRS and VSS for noise filtering; the capacitance should be 100 nF or smaller. These values will
allow the watchdog to properly drive the XRS pin to VOL within 512 OSCCLK cycles when the watchdog reset is
asserted. Figure 7-4 shows the recommended reset circuit.

VDDIO

2.2 kW – 10 kW

XRS

£100 nF

Figure 7-4. Reset Circuit

7.9.2.1 Reset Sources

The following reset sources exist on this device: XRS, WDRS, NMIWDRS, SYSRS, SCCRESET, and
HIBRESET. See the Reset Signals table in the System Control chapter of the TMS320F2807x Microcontrollers
Technical Reference Manual .
The parameter th(boot-mode) must account for a reset initiated from any of these sources.

CAUTION
Some reset sources are internally driven by the device. Some of these sources will drive XRS low.
Use this to disable any other devices driving the boot pins. The SCCRESET and debugger reset
sources do not drive XRS; therefore, the pins used for boot mode should not be actively driven by
other devices in the system. The boot configuration has a provision for changing the boot pins in
OTP; for more details, see the TMS320F2807x Microcontrollers Technical Reference Manual .

7.9.2.2 Reset Electrical Data and Timing

Section 7.9.2.2.1 shows the reset ( XRS) timing requirements. Section 7.9.2.2.2 shows the reset ( XRS)
switching characteristics. Figure 7-5 shows the power-on reset. Figure 7-6 shows the warm reset.
7.9.2.2.1 Reset ( XRS) Timing Requirements

MIN MAX UNIT

th(boot-mode) Hold time for boot-mode pins 1.5 ms
All cases 3.2
Pulse duration, XRS low on
tw(RSL2) Low-power modes used in µs
warm reset 3.2 * (SYSCLKDIV/16)
application and SYSCLKDIV > 16

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7.9.2.2.2 Reset ( XRS) Switching Characteristics

over recommended operating conditions (unless otherwise noted)
PARAMETER MIN TYP MAX UNIT
Pulse duration, XRS driven low by device after supplies are
tw(RSL1) 100 µs
stable
tw(WDRS) Pulse duration, reset pulse generated by watchdog 512tc(OSCCLK) cycles

VDDIO, VDDA
(3.3 V)

VDD (1.2 V)

tw(RSL1)
(A)
XRS

Boot ROM
CPU
Execution
Phase
User-code
th(boot-mode)(B) User-code dependent
Boot-Mode
GPIO pins as input
Pins
Peripheral/GPIO function
Boot-ROM execution starts
Based on boot code

I/O Pins GPIO pins as input (pullups are disabled)

User-code dependent
A. The XRS pin can be driven externally by a supervisor or an external pullup resistor, see Section 6.2.1.
B. After reset from any source (see Section 7.9.2.1), the boot ROM code samples Boot Mode pins. Based on the status of the Boot Mode
pin, the boot code branches to destination memory or boot code function. If boot ROM code executes after power-on conditions (in
debugger environment), the boot code execution time is based on the current SYSCLK speed. The SYSCLK will be based on user
environment and could be with or without PLL enabled.

Figure 7-5. Power-on Reset

tw(RSL2)

XRS
User Code
CPU
Execution User Code Boot ROM
Phase
Boot-ROM execution starts
(initiated by any reset source) th(boot-mode)(A)
Boot-Mode
Peripheral/GPIO Function GPIO Pins as Input Peripheral/GPIO Function
Pins
User-Code Execution Starts

I/O Pins User-Code Dependent GPIO Pins as Input (Pullups are Disabled)

User-Code Dependent
A. After reset from any source (see Section 7.9.2.1), the Boot ROM code samples BOOT Mode pins. Based on the status of the Boot Mode
pin, the boot code branches to destination memory or boot code function. If Boot ROM code executes after power-on conditions (in
debugger environment), the Boot code execution time is based on the current SYSCLK speed. The SYSCLK will be based on user
environment and could be with or without PLL enabled.

Figure 7-6. Warm Reset

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7.9.3 Clock Specifications

7.9.3.1 Clock Sources
Table 7-2 lists four possible clock sources. Figure 7-7 provides an overview of the device's clocking system.
Table 7-2. Possible Reference Clock Sources
CLOCK SOURCE MODULES CLOCKED COMMENTS
INTOSC1 Can be used to provide clock for: Internal oscillator 1.
• Watchdog block Zero-pin overhead 10-MHz internal oscillator.
• CPU-Timer 2

INTOSC2(1) Can be used to provide clock for: Internal oscillator 2.

• Main PLL Zero-pin overhead 10-MHz internal oscillator.
• Auxiliary PLL
• CPU-Timer 2

XTAL Can be used to provide clock for: External crystal or resonator connected between the X1 and X2 pins
• Main PLL or single-ended clock connected to the X1 pin.
• Auxiliary PLL
• CPU-Timer 2

AUXCLKIN Can be used to provide clock for: Single-ended 3.3-V level clock source. GPIO133/AUXCLKIN pin
• Auxiliary PLL should be used to provide the input clock.
• CPU-Timer 2

(1) On reset, internal oscillator 2 (INTOSC2) is the default clock source for both system PLL (OSCCLK) and auxiliary PLL (AUXOSCCLK).

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INTOSC1 WDCLK To watchdog timer

INTOSC2 CLKSRCCTL1 SYSPLLCTL1 SYSCLKDIVSEL

SYSCLK To GS RAMs, GPIOs,

OSCCLK PLLSYSCLK
Divider and NMIWDs
X1(XTAL) System PLL PLLRAWCLK

SYSCLK CPU CPU1.CPUCLK To local memories

To ePIEs, LS RAMs,
CPU1.SYSCLK CLA message RAMs,
and DCSMs
One per SYSCLK peripheral

PCLKCRx

PERx.SYSCLK To peripherals

One per LSPCLK peripheral

LOSPCP
PCLKCRx

To SCIs, SPIs, and

LSP PERx.LSPCLK
LSPCLK McBSPs
Divider

One per ePWM

EPWMCLKDIV PCLKCRx

PLLSYSCLK /1 EPWMCLK To ePWMs

/2

HRPWM

PCLKCRx

HRPWMCLK To HRPWMs

One per CAN module

CLKSRCCTL2

CAN Bit Clock To CANs

AUXCLKIN

CLKSRCCTL2 AUXPLLCTL1 AUXCLKDIVSEL

AUXCLK
AUXOSCCLK AUXPLLCLK To USB bit clock
Divider
Auxiliary PLL AUXPLLRAWCLK

Figure 7-7. Clocking System

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7.9.3.2 Clock Frequencies, Requirements, and Characteristics

This section provides the frequencies and timing requirements of the input clocks, PLL lock times, frequencies of
the internal clocks, and the frequency and switching characteristics of the output clock.
7.9.3.2.1 Input Clock Frequency and Timing Requirements, PLL Lock Times
Section 7.9.3.2.1.1 shows the frequency requirements for the input clocks. Table 7-3 shows the crystal
equivalent series resistance requirements. Section 7.9.3.2.1.2 shows the X1 input level characteristics when
using an external clock source. Section 7.9.3.2.1.3 and Section 7.9.3.2.1.4 show the timing requirements for the
input clocks. Section 7.9.3.2.1.5 shows the PLL lock times for the Main PLL and the USB PLL.
7.9.3.2.1.1 Input Clock Frequency

MIN MAX UNIT

f(XTAL) Frequency, X1/X2, from external crystal or resonator 10 20 MHz
f(X1) Frequency, X1, from external oscillator 2 25 MHz
f(AUXI) Frequency, AUXCLKIN, from external oscillator 2 60 MHz

7.9.3.2.1.2 X1 Input Level Characteristics When Using an External Clock Source (Not a Crystal)
over recommended operating conditions (unless otherwise noted)
PARAMETER MIN MAX UNIT
X1 VIL Valid low-level input voltage –0.3 0.3 * VDDIO V
X1 VIH Valid high-level input voltage 0.7 * VDDIO VDDIO + 0.3 V

7.9.3.2.1.3 X1 Timing Requirements

MIN MAX UNIT

tf(X1) Fall time, X1 6 ns
tr(X1) Rise time, X1 6 ns
tw(X1L) Pulse duration, X1 low as a percentage of tc(X1) 45% 55%
tw(X1H) Pulse duration, X1 high as a percentage of tc(X1) 45% 55%

7.9.3.2.1.4 AUXCLKIN Timing Requirements

MIN MAX UNIT

tf(AUXI) Fall time, AUXCLKIN 6 ns
tr(AUXI) Rise time, AUXCLKIN 6 ns
tw(AUXL) Pulse duration, AUXCLKIN low as a percentage of tc(XCI) 45% 55%
tw(AUXH) Pulse duration, AUXCLKIN high as a percentage of tc(XCI) 45% 55%

7.9.3.2.1.5 PLL Lock Times

MIN NOM MAX UNIT

t(PLL) Lock time, Main PLL (X1, from external oscillator) 50 µs + 2500 * tc(OSCCLK) (1) µs
t(USB) Lock time, USB PLL (AUXCLKIN, from external oscillator) 50 µs + 2500 * tc(OSCCLK) (1) µs

(1) The PLL lock time here defines the typical time of execution for the PLL workaround as defined in the TMS320F2807x MCUs Silicon
Errata . Cycle count includes code execution of the PLL initialization routine, which could vary depending on compiler optimizations
and flash wait states. TI recommends using the latest example software from C2000Ware for initializing the PLLs. For the system PLL,
see InitSysPll() or SysCtl_setClock(). For the auxillary PLL, see InitAuxPll() or SysCtl_setAuxClock().

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7.9.3.2.2 Internal Clock Frequencies

Section 7.9.3.2.2.1 provides the clock frequencies for the internal clocks.
7.9.3.2.2.1 Internal Clock Frequencies

MIN NOM MAX UNIT

f(SYSCLK) Frequency, device (system) clock 2 120 MHz
tc(SYSCLK) Period, device (system) clock 8.33 500 ns
Frequency, system PLL output (before SYSCLK
f(PLLRAWCLK) 120 400 MHz
divider)
Frequency, auxiliary PLL output (before AUXCLK
f(AUXPLLRAWCLK) 120 400 MHz
divider)
f(AUXPLL) Frequency, AUXPLLCLK 2 60 60 MHz
f(PLL) Frequency, PLLSYSCLK 2 120 MHz
f(LSP) Frequency, LSPCLK 2 120 MHz
tc(LSPCLK) Period, LSPCLK 8.33 500 ns
Frequency, OSCCLK (INTOSC1 or INTOSC2 or
f(OSCCLK) See respective clock MHz
XTAL or X1)
f(EPWM) Frequency, EPWMCLK(1) 100 MHz
f(HRPWM) Frequency, HRPWMCLK 60 100 MHz

(1) For SYSCLK above 100 MHz, the EPWMCLK must be half of SYSCLK.

7.9.3.2.3 Output Clock Frequency and Switching Characteristics

Section 7.9.3.2.3.1 provides the frequency of the output clock. Section 7.9.3.2.3.2 shows the switching
characteristics of the output clock, XCLKOUT.
7.9.3.2.3.1 Output Clock Frequency

MIN MAX UNIT

f(XCO) Frequency, XCLKOUT 50 MHz

7.9.3.2.3.2 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)

over recommended operating conditions (unless otherwise noted)
PARAMETER(1) (2) MIN MAX UNIT
tf(XCO) Fall time, XCLKOUT 5 ns
tr(XCO) Rise time, XCLKOUT 5 ns
tw(XCOL) Pulse duration, XCLKOUT low H–2 H+2 ns
tw(XCOH) Pulse duration, XCLKOUT high H–2 H+2 ns

(1) A load of 40 pF is assumed for these parameters.

(2) H = 0.5tc(XCO)

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7.9.3.3 Input Clocks and PLLs

In addition to the internal 0-pin oscillators, multiple external clock source options are available. Figure 7-8 shows
the recommended methods of connecting crystals, resonators, and oscillators to pins X1/X2 (also referred to as
XTAL) and AUXCLKIN.

X1 vssosc X2 X1 vssosc X2

RESONATOR
CRYSTAL

RD C L2 C L1

X1 vssosc X2 GPIO133/AUXCLKIN

NC

3.3V CLK 3.3V CLK

VDD OUT VDD OUT

GND GND

3.3V OSCILLATOR 3.3V OSCILLATOR

Figure 7-8. Connecting Input Clocks to a 2807x Device

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7.9.3.4 Crystal Oscillator

When using a quartz crystal, it may be necessary to include a damping resistor (RD) in the crystal circuit to
prevent over-driving the crystal (drive level can be found in the crystal data sheet). In higher-frequency
applications (10 MHz or greater), RD is generally not required. If a damping resistor is required, RD should be as
small as possible because the size of the resistance affects start-up time (smaller RD = faster start-up time). TI
recommends that the crystal manufacturer characterize the crystal with the application board. Section 7.9.3.4.1
shows the crystal oscillator parameters. Table 7-3 shows the crystal equivalent series resistance (ESR)
requirements. Section 7.9.3.4.2 shows the crystal oscillator electrical characteristics.
7.9.3.4.1 Crystal Oscillator Parameters

MIN MAX UNIT

CL1, CL2 Load capacitance 12 24 pF
C0 Crystal shunt capacitance 7 pF

Table 7-3. Crystal Equivalent Series Resistance (ESR) Requirements

CRYSTAL FREQUENCY (MHz) MAXIMUM ESR (Ω) MAXIMUM ESR (Ω)
(1) (2) (CL1 = CL2 = 12 pF) (CL1 = CL2 = 24 pF)
10 55 110
12 50 95
14 50 90
16 45 75
18 45 65
20 45 50

(1) Crystal shunt capacitance (C0) should be less than or equal to 7 pF.
(2) ESR = Negative Resistance/3

7.9.3.4.2 Crystal Oscillator Electrical Characteristics

over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f = 20 MHz
ESR MAX = 50 Ω
Start-up time(1) 2 ms
CL1 = CL2 = 24 pF
C0 = 7 pF
Crystal drive level (DL) 1 mW

(1) Start-up time is dependent on the crystal and tank circuit components. TI recommends that the crystal vendor characterize the
application with the chosen crystal.

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7.9.3.5 Internal Oscillators

To reduce production board costs and application development time, all F2807x devices contain two
independent internal oscillators, referred to as INTOSC1 and INTOSC2. By default, both oscillators are enabled
at power up. INTOSC2 is set as the source for the system reference clock (OSCCLK) and INTOSC1 is set as the
backup clock source. INTOSC1 can also be manually configured as the system reference clock (OSCCLK).
Section 7.9.3.5.1 provides the electrical characteristics of the internal oscillators to determine if this module
meets the clocking requirements of the application.
Section 7.9.3.5.1 provides the electrical characteristics of the two internal oscillators.
7.9.3.5.1 Internal Oscillator Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f(INTOSC) Frequency, INTOSC1 and INTOSC2 9.7 10.0 10.3 MHz
Frequency stability at room temperature 30°C, Nominal VDD ±0.1%
f(INTOSC-STABILITY) Frequency stability over VDD 30°C ±0.2%
Frequency stability –3.0% 3.0%
f(INTOSC-ST) Start-up and settling time 20 µs

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7.9.4 Flash Parameters

The on-chip flash memory is tightly integrated to the CPU, allowing code execution directly from flash through
128-bit-wide prefetch reads and a pipeline buffer. Flash performance for sequential code is equal to execution
from RAM. Factoring in discontinuities, most applications will run with an efficiency of approximately 80% relative
to code executing from RAM.
This device also has an OTP (One-Time-Programmable) sector used for the dual code security module (DCSM),
which cannot be erased after it is programmed.
Table 7-4 shows the minimum required flash wait states at different frequencies. Section 7.9.4.1 shows the flash
parameters.
Table 7-4. Flash Wait States
CPUCLK (MHz)
MINIMUM WAIT STATES (1)
EXTERNAL OSCILLATOR OR CRYSTAL INTOSC1 OR INTOSC2
100 < CPUCLK ≤ 120 97 < CPUCLK ≤ 120 2
50 < CPUCLK ≤ 100 48 < CPUCLK ≤ 97 1
CPUCLK ≤ 50 CPUCLK ≤ 48 0

(1) Minimum required FRDCNTL[RWAIT].

7.9.4.1 Flash Parameters

PARAMETER MIN TYP MAX UNIT
128 data bits + 16 ECC bits 40 300 µs
Program Time(1) 8KW sector 100 200 ms
32KW sector 400 800 ms
8KW sector 35 60
Erase Time(2) at < 25 cycles ms
32KW sector 40 65
8KW sector 110 4000
Erase Time(2) at 20k cycles ms
32KW sector 120 4000
Nwec Write/erase cycles 20000 cycles
tretention Data retention duration at TJ = 85°C 20 years

(1) Program time is at the maximum device frequency. Program time includes overhead of the flash state machine but does not include
the time to transfer the following into RAM:
• Code that uses flash API to program the flash
• Flash API itself
• Flash data to be programmed
In other words, the time indicated in this table is applicable after all the required code/data is available in the device RAM, ready for
programming. The transfer time will significantly vary depending on the speed of the JTAG debug probe used.
Program time calculation is based on programming 144 bits at a time at the specified operating frequency. Program time includes
Program verify by the CPU. The program time does not degrade with write/erase (W/E) cycling, but the erase time does.
Erase time includes Erase verify by the CPU and does not involve any data transfer.
(2) Erase time includes Erase verify by the CPU.

Note
The Main Array flash programming must be aligned to 64-bit address boundaries and each 64-bit
word may only be programmed once per write/erase cycle. For more details, see the "Flash: Minimum
Programming Word Size" advisory in the TMS320F2807x MCUs Silicon Errata .

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7.9.5 Emulation/JTAG
The JTAG port has five dedicated pins: TRST, TMS, TDI, TDO, and TCK. The TRST signal should always be
pulled down through a 2.2-kΩ pulldown resistor on the board. This MCU does not support the EMU0 and EMU1
signals that are present on 14-pin and 20-pin emulation headers. These signals should always be pulled up at
the emulation header through a pair of board pullup resistors ranging from 2.2 kΩ to 4.7 kΩ (depending on the
drive strength of the debugger ports). Typically, a 2.2-kΩ value is used.
See Figure 7-9 to see how the 14-pin JTAG header connects to the MCU’s JTAG port signals. Figure 7-10 shows
how to connect to the 20-pin header. The 20-pin JTAG header terminals EMU2, EMU3, and EMU4 are not used
and should be grounded.
The PD (Power Detect) terminal of the JTAG debug probe header should be connected to the board 3.3-V
supply. Header GND terminals should be connected to board ground. TDIS (Cable Disconnect Sense) should
also be connected to board ground. The JTAG clock should be looped from the header TCK output terminal back
to the RTCK input terminal of the header (to sense clock continuity by the JTAG debug probe). Header terminal
RESET is an open-drain output from the JTAG debug probe header that enables board components to be reset
through JTAG debug probe commands (available only through the 20-pin header).
Typically, no buffers are needed on the JTAG signals when the distance between the MCU target and the JTAG
header is smaller than 6 inches (15.24 cm), and no other devices are present on the JTAG chain. Otherwise,
each signal should be buffered. Additionally, for most JTAG debug probe operations at 10 MHz, no series
resistors are needed on the JTAG signals. However, if high emulation speeds are expected (35 MHz or so), 22-Ω
resistors should be placed in series on each JTAG signal.
For more information about hardware breakpoints and watchpoints, see Hardware Breakpoints and Watchpoints
for C28x in CCS.
For more information about JTAG emulation, see the XDS Target Connection Guide.

Distance between the header and the target

should be less than 6 inches (15.24 cm).
2.2 kW
TRST GND
1 2
TMS TMS TRST
3 4
TDI TDI TDIS GND
100 W
MCU 5 6
3.3 V PD KEY
7 8
TDO TDO GND
9 10
RTCK GND

TCK 11 12
TCK GND
4.7 kW 4.7 kW
13 14
3.3 V EMU0 EMU1 3.3 V

Figure 7-9. Connecting to the 14-Pin JTAG Header

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Distance between the header and the target

should be less than 6 inches (15.24 cm). 2.2 kW
TRST GND
1 2
TMS TMS TRST

TDI 3 4
TDI TDIS GND
100 W
MCU 5 6
3.3V PD KEY

TDO 7 8
TDO GND
9 10
RTCK GND

TCK 11 12
TCK GND
4.7 kW 4.7 kW
3.3 V 13 EMU0 EMU1 14 3.3 V
15 16
RESET GND
open
drain 17 18
EMU2 EMU3

A low pulse from the JTAG debug probe 19 EMU4 GND 20

can be tied with other reset sources
to reset the board. GND GND
Figure 7-10. Connecting to the 20-Pin JTAG Header

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7.9.5.1 JTAG Electrical Data and Timing

Section 7.9.5.1.1 lists the JTAG timing requirements. Section 7.9.5.1.2 lists the JTAG switching characteristics.
Figure 7-11 shows the JTAG timing.
7.9.5.1.1 JTAG Timing Requirements

NO. MIN MAX UNIT

1 tc(TCK) Cycle time, TCK 66.66 ns
1a tw(TCKH) Pulse duration, TCK high (40% of tc) 26.66 ns
1b tw(TCKL) Pulse duration, TCK low (40% of tc) 26.66 ns
tsu(TDI-TCKH) Input setup time, TDI valid to TCK high 13 ns
3
tsu(TMS-TCKH) Input setup time, TMS valid to TCK high 13 ns
th(TCKH-TDI) Input hold time, TDI valid from TCK high 7 ns
4
th(TCKH-TMS) Input hold time, TMS valid from TCK high 7 ns

7.9.5.1.2 JTAG Switching Characteristics

over recommended operating conditions (unless otherwise noted)
NO. PARAMETER MIN MAX UNIT
2 td(TCKL-TDO) Delay time, TCK low to TDO valid 6 25 ns

1
1a 1b

TCK

TDO

3 4

TDI/TMS

Figure 7-11. JTAG Timing

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7.9.6 GPIO Electrical Data and Timing

The peripheral signals are multiplexed with general-purpose input/output (GPIO) signals. On reset, GPIO pins
are configured as inputs. For specific inputs, the user can also select the number of input qualification cycles to
filter unwanted noise glitches.
The GPIO module contains an Output X-BAR which allows an assortment of internal signals to be routed to a
GPIO in the GPIO mux positions denoted as OUTPUTXBARx. The GPIO module also contains an Input X-BAR
which is used to route signals from any GPIO input to different IP blocks such as the ADC(s), eCAP(s),
ePWM(s), and external interrupts. For more details, see the X-BAR chapter in the TMS320F2807x
Microcontrollers Technical Reference Manual .
7.9.6.1 GPIO - Output Timing
Section 7.9.6.1.1 shows the general-purpose output switching characteristics. Figure 7-12 shows the general-
purpose output timing.
7.9.6.1.1 General-Purpose Output Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER MIN MAX UNIT
tr(GPO) Rise time, GPIO switching low to high All GPIOs 8(1) ns
tf(GPO) Fall time, GPIO switching high to low All GPIOs 8(1) ns
tfGPO Toggling frequency, GPO pins 25 MHz

(1) Rise time and fall time vary with load. These values assume a 40-pF load.

GPIO

tr(GPO)
tf(GPO)

Figure 7-12. General-Purpose Output Timing

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7.9.6.2 GPIO - Input Timing

Section 7.9.6.2.1 shows the general-purpose input timing requirements. Figure 7-13 shows the sampling mode.
7.9.6.2.1 General-Purpose Input Timing Requirements

MIN MAX UNIT

QUALPRD = 0 1tc(SYSCLK) cycles
tw(SP) Sampling period
QUALPRD ≠ 0 2tc(SYSCLK) * QUALPRD cycles
tw(IQSW) Input qualifier sampling window tw(SP) * (n(1) – 1) cycles
Synchronous mode 2tc(SYSCLK) cycles
tw(GPI) (2) Pulse duration, GPIO low/high
With input qualifier tw(IQSW) + tw(SP) + 1tc(SYSCLK) cycles

(1) "n" represents the number of qualification samples as defined by GPxQSELn register.
(2) For tw(GPI), pulse width is measured from VIL to VIL for an active low signal and VIH to VIH for an active high signal.

(A)
GPIO Signal GPxQSELn = 1,0 (6 samples)

1 1 0 0 0 0 0 0 0 1 0 0 0 1 1 1 1 1 1 1 1 1

tw(SP) Sampling Period determined

(B)
by GPxCTRL[QUALPRD]
tw(IQSW)
(C)
Sampling Window (SYSCLK cycle * 2 * QUALPRD) * 5

SYSCLK

QUALPRD = 1
(SYSCLK/2)
(D)
Output From
Qualifier
A. This glitch will be ignored by the input qualifier. The QUALPRD bit field specifies the qualification sampling period. It can vary from 00 to
0xFF. If QUALPRD = 00, then the sampling period is 1 SYSCLK cycle. For any other value "n", the qualification sampling period in 2n
SYSCLK cycles (that is, at every 2n SYSCLK cycles, the GPIO pin will be sampled).
B. The qualification period selected through the GPxCTRL register applies to groups of 8 GPIO pins.
C. The qualification block can take either three or six samples. The GPxQSELn Register selects which sample mode is used.
D. In the example shown, for the qualifier to detect the change, the input should be stable for 10 SYSCLK cycles or greater. In other words,
the inputs should be stable for (5 x QUALPRD x 2) SYSCLK cycles. This would ensure 5 sampling periods for detection to occur.
Because external signals are driven asynchronously, an 13-SYSCLK-wide pulse ensures reliable recognition.

Figure 7-13. Sampling Mode

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7.9.6.3 Sampling Window Width for Input Signals

The following section summarizes the sampling window width for input signals for various input qualifier
configurations.
Sampling frequency denotes how often a signal is sampled with respect to SYSCLK.

Sampling frequency = SYSCLK/(2 ´ QUALPRD), if QUALPRD ¹ 0 (1)

Sampling frequency = SYSCLK, if QUALPRD = 0 (2)

Sampling period = SYSCLK cycle ´ 2 ´ QUALPRD, if QUALPRD ¹ 0 (3)

In Equation 1, Equation 2, and Equation 3, SYSCLK cycle indicates the time period of SYSCLK.
Sampling period = SYSCLK cycle, if QUALPRD = 0
In a given sampling window, either 3 or 6 samples of the input signal are taken to determine the validity of the
signal. This is determined by the value written to GPxQSELn register.
Case 1:
Qualification using 3 samples
Sampling window width = (SYSCLK cycle × 2 × QUALPRD) × 2, if QUALPRD ≠ 0
Sampling window width = (SYSCLK cycle) × 2, if QUALPRD = 0
Case 2:
Qualification using 6 samples
Sampling window width = (SYSCLK cycle × 2 × QUALPRD) × 5, if QUALPRD ≠ 0
Sampling window width = (SYSCLK cycle) × 5, if QUALPRD = 0
Figure 7-14 shows the general-purpose input timing.

SYSCLK

GPIOxn

tw(GPI)

Figure 7-14. General-Purpose Input Timing

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7.9.7 Interrupts
Figure 7-15 provides a high-level view of the interrupt architecture.
As shown in Figure 7-15, the devices support five external interrupts (XINT1 to XINT5) that can be mapped onto
any of the GPIO pins.
In this device, 16 ePIE block interrupts are grouped into 1 CPU interrupt. In total, there are 12 CPU interrupt
groups, with 16 interrupts per group.
CPU1.TINT0
CPU1.TIMER0

LPM Logic CPU1.LPMINT

CPU1.W AKEINT
CPU1.WD NMI
CPU1.W DINT CPU1.NMIWD

CPU1
INPUTXBAR4 CPU1.XINT1 Control
GPIO0
GPIO1 INPUTXBAR5 CPU1.XINT2 Control INT1
...
Input CPU1.XINT3 Control
CPU1. to
INPUTXBAR6
... X-BAR CPU1.XINT4 Control
ePIE INT12
INPUTXBAR13
GPIOx
INPUTXBAR14 CPU1.XINT5 Control
CPU1.TINT1
CPU1.TIMER1 INT13
CPU1.TINT2
CPU1.TIMER2 INT14
Peripherals

Figure 7-15. External and ePIE Interrupt Sources

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7.9.7.1 External Interrupt (XINT) Electrical Data and Timing

Section 7.9.7.1.1 lists the external interrupt timing requirements. Section 7.9.7.1.2 lists the external interrupt
switching characteristics. Figure 7-16 shows the external interrupt timing.
7.9.7.1.1 External Interrupt Timing Requirements

MIN MAX UNIT(1)

Synchronous 2tc(SYSCLK) cycles
tw(INT) Pulse duration, INT input low/high
With qualifier tw(IQSW) + tw(SP) + 1tc(SYSCLK) cycles

(1) For an explanation of the input qualifier parameters, see Section 7.9.6.2.1.

7.9.7.1.2 External Interrupt Switching Characteristics

over recommended operating conditions (unless otherwise noted)(1)
PARAMETER MIN MAX UNIT
td(INT) Delay time, INT low/high to interrupt-vector fetch(2) tw(IQSW) + 14tc(SYSCLK) tw(IQSW) + tw(SP) + 14tc(SYSCLK) cycles

(1) For an explanation of the input qualifier parameters, see Section 7.9.6.2.1.
(2) This assumes that the ISR is in a single-cycle memory.

tw(INT)
XINT1, XINT2, XINT3,
XINT4, XINT5

td(INT)

Address bus
Interrupt Vector
(internal)

Figure 7-16. External Interrupt Timing

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7.9.8 Low-Power Modes

This device has three clock-gating low-power modes and a special power-gating mode.
Further details, as well as the entry and exit procedure, for all of the low-power modes can be found in the Low
Power Modes section of the TMS320F2807x Microcontrollers Technical Reference Manual .
7.9.8.1 Clock-Gating Low-Power Modes
IDLE, STANDBY, and HALT modes on this device are similar to those on other C28x devices. Table 7-5
describes the effect on the system when any of the clock-gating low-power modes are entered.
Table 7-5. Effect of Clock-Gating Low-Power Modes on the Device
MODULES/
CPU1 IDLE CPU1 STANDBY HALT
CLOCK DOMAIN
CPU1.CLKIN Active Gated Gated
CPU1.SYSCLK Active Gated Gated
CPU1.CPUCLK Gated Gated Gated
Clock to modules Connected to Active Gated Gated
PERx.SYSCLK
CPU1.WDCLK Active Active Gated if CLKSRCCTL1.WDHALTI = 0
AUXPLLCLK Active Active Gated
PLL Powered Powered Software must power down PLL before entering
HALT
INTOSC1 Powered Powered Powered down if CLKSRCCTL1.WDHALTI = 0
INTOSC2 Powered Powered Powered down if CLKSRCCTL1.WDHALTI = 0
Flash Powered Powered Software-Controlled
X1/X2 Crystal Oscillator Powered Powered Powered-Down

7.9.8.2 Power-Gating Low-Power Modes

HIBERNATE mode is the lowest power mode on this device. It is a global low-power mode that gates the supply
voltages to most of the system. HIBERNATE is essentially a controlled power-down with remote wakeup
capability, and can be used to save power during long periods of inactivity. Table 7-6 describes the effects on the
system when the HIBERNATE mode is entered.
Table 7-6. Effect of Power-Gating Low-Power Mode on the Device
MODULES/POWER DOMAINS HIBERNATE
M0 and M1 memories ● Remain on with memory retention if LPMCR.M0M1MODE = 0x00
● Are off when LPMCR.M0M1MODE = 0x01
CPU1 digital peripherals Powered down
Dx, LSx, GSx memories Power down, memory contents are lost
I/Os On with output state preserved
Oscillators, PLL, analog Enters Low-Power Mode
peripherals, Flash

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7.9.8.3 Low-Power Mode Wakeup Timing

Section 7.9.8.3.1 shows the IDLE mode timing requirements, Section 7.9.8.3.2 shows the switching
characteristics, and Figure 7-17 shows the timing diagram for IDLE mode.
7.9.8.3.1 IDLE Mode Timing Requirements

MIN MAX UNIT(1)

Without input qualifier 2tc(SYSCLK)
tw(WAKE) Pulse duration, external wake-up signal cycles
With input qualifier 2tc(SYSCLK) + tw(IQSW)

(1) For an explanation of the input qualifier parameters, see Section 7.9.6.2.1.

7.9.8.3.2 IDLE Mode Switching Characteristics

over recommended operating conditions (unless otherwise noted)(1)
PARAMETER TEST CONDITIONS MIN MAX UNIT
Delay time, external wake signal to program execution resume (2)
• Wakeup from Flash Without input qualifier 40tc(SYSCLK)
– Flash module in active state With input qualifier 40tc(SYSCLK) + tw(WAKE)
td(WAKE-IDLE) • Wakeup from Flash Without input qualifier 6700tc(SYSCLK) (3) cycles
– Flash module in sleep state With input qualifier 6700tc(SYSCLK) (3) + tw(WAKE)
Without input qualifier 25tc(SYSCLK)
• Wakeup from RAM
With input qualifier 25tc(SYSCLK) + tw(WAKE)

(1) For an explanation of the input qualifier parameters, see Section 7.9.6.2.1.
(2) This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. Execution of an ISR (triggered
by the wake-up signal) involves additional latency.
(3) This value is based on the flash power-up time, which is a function of the SYSCLK frequency, flash wait states (RWAIT), and
FPAC1[PSLEEP]. For more information, see the Flash and OTP Power-Down Modes and Wakeup section of the TMS320F2807x
Microcontrollers Technical Reference Manual . This value can be realized when SYSCLK is 120 MHz, RWAIT is 2, and
FPAC1[PSLEEP] is 0x860.

td(WAKE-IDLE)
Address/Data
(internal)

XCLKOUT

tw(WAKE)
(A)
WAKE
A. WAKE can be any enabled interrupt, WDINT or XRS. After the IDLE instruction is executed, a delay of five OSCCLK cycles (minimum) is
needed before the wake-up signal could be asserted.

Figure 7-17. IDLE Entry and Exit Timing Diagram

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Section 7.9.8.3.3 shows the STANDBY mode timing requirements, Section 7.9.8.3.4 shows the switching
characteristics, and Figure 7-18 shows the timing diagram for STANDBY mode.
7.9.8.3.3 STANDBY Mode Timing Requirements

MIN MAX UNIT

QUALSTDBY = 0 | 2tc(OSCCLK) 3tc(OSCCLK)
Pulse duration, external
tw(WAKE-INT) QUALSTDBY > 0 | cycles
wake-up signal (2 + QUALSTDBY) * tc(OSCCLK)
(2 + QUALSTDBY)tc(OSCCLK) (1)

(1) QUALSTDBY is a 6-bit field in the LPMCR register.

7.9.8.3.4 STANDBY Mode Switching Characteristics

over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN MAX UNIT
Delay time, IDLE instruction executed to
td(IDLE-XCOS) 16tc(INTOSC1) cycles
XCLKOUT stop
Delay time, external wake signal to
program execution resume(1)
• Wakeup from flash
– Flash module in active state 175tc(SYSCLK) + tw(WAKE-INT)
td(WAKE-STBY) cycles
• Wakeup from flash 6700tc(SYSCLK) (2) + tw(WAKE-
– Flash module in sleep state INT)

• Wakeup from RAM 3tc(OSC) + 15tc(SYSCLK) +

tw(WAKE-INT)

(1) This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. Execution of an ISR (triggered
by the wake-up signal) involves additional latency.
(2) This value is based on the flash power-up time, which is a function of the SYSCLK frequency, flash wait states (RWAIT), and
FPAC1[PSLEEP]. For more information, see the Flash and OTP Power-Down Modes and Wakeup section of the TMS320F2807x
Microcontrollers Technical Reference Manual . This value can be realized when SYSCLK is 120 MHz, RWAIT is 2, and
FPAC1[PSLEEP] is 0x860.

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(A) (C) (F)

(B) (D)(E) (G)

Device STANDBY STANDBY Normal Execution

Status
Flushing Pipeline

Wake-up
Signal

tw(WAKE-INT)

td(WAKE-STBY)

OSCCLK

XCLKOUT

td(IDLE-XCOS)
A. IDLE instruction is executed to put the device into STANDBY mode.
B. The LPM block responds to the STANDBY signal, SYSCLK is held for a maximum 16 INTOSC1 clock cycles before being turned off.
This delay enables the CPU pipeline and any other pending operations to flush properly.
C. Clock to the peripherals are turned off. However, the PLL and watchdog are not shut down. The device is now in STANDBY mode. After
the IDLE instruction is executed, a delay of five OSCCLK cycles (minimum) is needed before the wake-up signal could be asserted.
D. The external wake-up signal is driven active.
E. The wake-up signal fed to a GPIO pin to wake up the device must meet the minimum pulse width requirement. Furthermore, this signal
must be free of glitches. If a noisy signal is fed to a GPIO pin, the wakeup behavior of the device will not be deterministic and the device
may not exit low-power mode for subsequent wakeup pulses.
F. After a latency period, the STANDBY mode is exited.
G. Normal execution resumes. The device will respond to the interrupt (if enabled).

Figure 7-18. STANDBY Entry and Exit Timing Diagram

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Section 7.9.8.3.5 shows the HALT mode timing requirements, Section 7.9.8.3.6 shows the switching
characteristics, and Figure 7-19 shows the timing diagram for HALT mode.
7.9.8.3.5 HALT Mode Timing Requirements

MIN MAX UNIT

tw(WAKE-GPIO) Pulse duration, GPIO wake-up signal(1) toscst + 2tc(OSCCLK) cycles
tw(WAKE-XRS) Pulse duration, XRS wake-up signal(1) toscst + 8tc(OSCCLK) cycles

(1) For applications using X1/X2 for OSCCLK, the user must characterize their specific oscillator start-up time as it is dependent on circuit/
layout external to the device. See Section 7.9.3.4.2 for more information. For applications using INTOSC1 or INTOSC2 for OSCCLK,
see Section 7.9.3.5 for toscst. Oscillator start-up time does not apply to applications using a single-ended crystal on the X1 pin, as it is
powered externally to the device.

7.9.8.3.6 HALT Mode Switching Characteristics

over recommended operating conditions (unless otherwise noted)
PARAMETER MIN MAX UNIT
td(IDLE-XCOS) Delay time, IDLE instruction executed to XCLKOUT stop 16tc(INTOSC1) cycles
Delay time, external wake signal end to CPU1 program
execution resume
• Wakeup from flash
– Flash module in active state 75tc(OSCCLK)
td(WAKE-HALT) cycles
• Wakeup from flash
– Flash module in sleep state 17500tc(OSCCLK) (1)

• Wakeup from RAM 75tc(OSCCLK)

(1) This value is based on the flash power-up time, which is a function of the SYSCLK frequency, flash wait states (RWAIT), and
FPAC1[PSLEEP]. For more information, see the Flash and OTP Power-Down Modes and Wakeup section of the TMS320F2807x
Microcontrollers Technical Reference Manual . This value can be realized when SYSCLK is 120 MHz, RWAIT is 2, and
FPAC1[PSLEEP] is 0x860.

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(A) (C) (F)

(B) (D)(E) (G)

Device
HALT HALT
Status

Flushing Pipeline Normal

Execution

GPIOn

td(WAKE-HALT)
tw(WAKE-GPIO)

OSCCLK

Oscillator Start-up Time

XCLKOUT

td(IDLE-XCOS)
A. IDLE instruction is executed to put the device into HALT mode.
B. The LPM block responds to the HALT signal, SYSCLK is held for a maximum 16 INTOSC1 clock cycles before being turned off. This
delay enables the CPU pipeline and any other pending operations to flush properly.
C. Clocks to the peripherals are turned off and the PLL is shut down. If a quartz crystal or ceramic resonator is used as the clock source,
the internal oscillator is shut down as well. The device is now in HALT mode and consumes very little power. It is possible to keep the
zero-pin internal oscillators (INTOSC1 and INTOSC2) and the watchdog alive in HALT MODE. This is done by writing a 1 to
CLKSRCCTL1.WDHALTI. After the IDLE instruction is executed, a delay of five OSCCLK cycles (minimum) is needed before the wake-
up signal could be asserted.
D. When the GPIOn pin (used to bring the device out of HALT) is driven low, the oscillator is turned on and the oscillator wakeup sequence
is initiated. The GPIO pin should be driven high only after the oscillator has stabilized. This enables the provision of a clean clock signal
during the PLL lock sequence. Because the falling edge of the GPIO pin asynchronously begins the wakeup procedure, care should be
taken to maintain a low noise environment prior to entering and during HALT mode.
E. The wake-up signal fed to a GPIO pin to wake up the device must meet the minimum pulse width requirement. Furthermore, this signal
must be free of glitches. If a noisy signal is fed to a GPIO pin, the wakeup behavior of the device will not be deterministic and the device
may not exit low-power mode for subsequent wakeup pulses.
F. When CLKIN to the core is enabled, the device will respond to the interrupt (if enabled), after some latency. The HALT mode is now
exited.
G. Normal operation resumes.
H. The user must relock the PLL upon HALT wakeup to ensure a stable PLL lock.

Figure 7-19. HALT Entry and Exit Timing Diagram

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Section 7.9.8.3.7 shows the HIBERNATE mode timing requirements, Section 7.9.8.3.8 shows the switching
characteristics, and Figure 7-20 shows the timing diagram for HIBERNATE mode.
7.9.8.3.7 HIBERNATE Mode Timing Requirements

MIN MAX UNIT

tw(HIBWAKE) Pulse duration, HIBWAKE signal 40 µs
tw(WAKEXRS) Pulse duration, XRS wake-up signal 40 µs

7.9.8.3.8 HIBERNATE Mode Switching Characteristics

over recommended operating conditions (unless otherwise noted)
PARAMETER MIN MAX UNIT
td(IDLE-XCOS) Delay time, IDLE instruction executed to XCLKOUT stop 30tc(SYSCLK) cycles
td(WAKE-HIB) Delay time, external wake signal to lORestore function start 1.5 ms

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(A) (B) (C) (D) (F) (G)(H) (I)(J)

(E)

CPU1 HIB CPU1 IDLE

Device Status Device Active HIBERNATE CPU1 Boot ROM IoRestore() or Application Specific Operation
config Instruction

Td(WAKE-HIB)
GPIOHIBWAKEn,
XRSn
tw(HIBWAKEn),
tw(XRSn)

I/O Isolation

Bypassed &
PLLs Enabled Application SpecificOperation
Powered -Down

INTOSC1,INTOSC2,
On Powered Down Powering up On
X1/X2

XCLKCOUT Inactive Application Specific Operation

td(IDLE-XCOS)

A. CPU1 does necessary application-specific context save to M0/M1 memories if required. This includes GPIO state if using I/O Isolation.
Configures the LPMCR register of CPU1 for HIBERNATE mode. Powers down Flash Pump/Bank, USB-PHY, CMPSS, DAC, and ADC
using their register configurations. The application should also power down the PLL and peripheral clocks before entering HIBERNATE.
B. IDLE instruction is executed to put the device into HIBERNATE mode.
C. The device is now in HIBERNATE mode. If configured, I/O isolation is turned on, M0 and M1 memories are retained. CPU1 is powered
down. Digital peripherals are powered down. The oscillators, PLLs, analog peripherals, and Flash are in their software-controlled Low-
Power modes. Dx, LSx, and GSx memories are also powered down, and their memory contents lost.
D. A falling edge on the GPIOHIBWAKEn pin will drive the wakeup of the devices clock sources INTOSC1, INTOSC2, and X1/X2 OSC. The
wakeup source must keep the GPIOHIBWAKEn pin low long enough to ensure full power-up of these clock sources.
E. After the clock sources are powered up, the GPIOHIBWAKEn must be driven high to trigger the wakeup sequence of the remainder of
the device.
F. The BootROM will then begin to execute. The BootROM can distinguish a HIBERNATE wakeup by reading the CPU1.REC.HIBRESETn
bit. After the TI OTP trims are loaded, the BootROM code will branch to the user-defined IoRestore function if it has been configured.
G. At this point, the device is out of HIBERNATE mode, and the application may continue.
H. The IoRestore function is a user-defined function where the application may reconfigure GPIO states, disable I/O isolation, reconfigure
the PLL, restore peripheral configurations, or branch to application code. This is up to the application requirements.
I. If the application has not branched to application code, the BootROM will continue after completing IoRestore. It will disable I/O isolation
automatically if it was not taken care of inside of IoRestore.
J. BootROM will then boot as determined by the HIBBOOTMODE register. Refer to the ROM Code and Peripheral Booting chapter of the
TMS320F2807x Microcontrollers Technical Reference Manual for more information.

Figure 7-20. HIBERNATE Entry and Exit Timing Diagram

Note
1. If the IORESTOREADDR is configured as the default value, the BootROM will continue its
execution to boot as determined by the HIBBOOTMODE register. Refer to the ROM Code and
Peripheral Booting chapter of the TMS320F2807x Microcontrollers Technical Reference Manual for
more information.
2. The user may choose to disable I/O Isolation at any point in the IoRestore function. Regardless if
the user has disabled Isolation in the IoRestore function or if IoRestore is not defined, the
BootROM will automatically disable isolation before booting as determined by the HIBBOOTMODE
register.

7.9.9 External Memory Interface (EMIF)

The EMIF provides a means of connecting the CPU to various external storage devices like asynchronous
memories (SRAM, NOR flash) or synchronous memory (SDRAM).

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7.9.9.1 Asynchronous Memory Support

The EMIF supports asynchronous memories:
• SRAMs
• NOR Flash memories
There is an external wait input that allows slower asynchronous memories to extend the memory access. The
EMIF module supports up to three chip selects ( EMIF_CS[4:2]). Each chip select has the following individually
programmable attributes:
• Data bus width
• Read cycle timings: setup, hold, strobe
• Write cycle timings: setup, hold, strobe
• Bus turnaround time
• Extended wait option with programmable time-out
• Select strobe option
7.9.9.2 Synchronous DRAM Support
The EMIF memory controller is compliant with the JESD21-C SDR SDRAMs that use a 32-bit or 16-bit data bus.
The EMIF has a single SDRAM chip select ( EMIF_CS[0]).
The address space of the EMIF, for the synchronous memory (SDRAM), lies beyond the 22-bit range of the
program address bus and can only be accessed through the data bus, which places a restriction on the C
compiler being able to work effectively on data in this space. Therefore, when using SDRAM, the user is advised
to copy data (using the DMA) from external memory to RAM before working on it. See the examples in
C2000Ware (C2000Ware for C2000 MCUs ) and the TMS320F2807x Microcontrollers Technical Reference
Manual .
SDRAM configurations supported are:
• One-bank, two-bank, and four-bank SDRAM devices
• Devices with 8-, 9-, 10-, and 11-column addresses
• CAS latency of two or three clock cycles
• 16-bit/32-bit data bus width
• 3.3-V LVCMOS interface
Additionally, the EMIF supports placing the SDRAM in self-refresh and power-down modes. Self-refresh mode
allows the SDRAM to be put in a low-power state while still retaining memory contents because the SDRAM will
continue to refresh itself even without clocks from the microcontroller. Power-down mode achieves even lower
power, except the microcontroller must periodically wake up and issue refreshes if data retention is required. The
EMIF module does not support mobile SDRAM devices.
On this device, the EMIF does not support burst access for SDRAM configurations. This means every access to
an external SDRAM device will have CAS latency.

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7.9.9.3 EMIF Electrical Data and Timing

Note
This device has one EMIF interface. In this section, EMx denotes EM1.

7.9.9.3.1 Asynchronous RAM

Section 7.9.9.3.1.1 shows the EMIF asynchronous memory timing requirements. Section 7.9.9.3.1.2 shows the
EMIF asynchronous memory switching characteristics. Figure 7-21 through Figure 7-24 show the EMIF
asynchronous memory timing diagrams.
7.9.9.3.1.1 EMIF Asynchronous Memory Timing Requirements

NO.(1) MIN MAX UNIT

Reads and Writes
E EMIF clock period tc(SYSCLK) ns
Pulse duration, EMxWAIT assertion and
2 tw(EM_WAIT) 2E ns
deassertion
Reads
12 tsu(EMDV-EMOEH) Setup time, EMxD[y:0] valid before EMxOE high 15 ns
13 th(EMOEH-EMDIV) Hold time, EMxD[y:0] valid after EMxOE high 0 ns
Setup Time, EMxWAIT asserted before end of
14 tsu(EMOEL-EMWAIT) 4E+20 ns
Strobe Phase(2)
Writes
Setup Time, EMxWAIT asserted before end of
28 tsu(EMWEL-EMWAIT) 4E+20 ns
Strobe Phase(2)

(1) E = EMxCLK period in ns.

(2) Setup before end of STROBE phase (if no extended wait states are inserted) by which EMxWAIT must be asserted to add extended
wait states. Figure 7-22 and Figure 7-24 describe EMIF transactions that include extended wait states inserted during the STROBE
phase. However, cycles inserted as part of this extended wait period should not be counted; the 4E requirement is to the start of where
the HOLD phase would begin if there were no extended wait cycles.

7.9.9.3.1.2 EMIF Asynchronous Memory Switching Characteristics

NO.(1)
(2) (3) PARAMETER MIN MAX UNIT

Reads and Writes

1 td(TURNAROUND) Turn around time (TA)*E–3 (TA)*E+2 ns
Reads
EMIF read cycle time (EW = 0) (RS+RST+RH)*E–3 (RS+RST+RH)*E+2 ns
3 tc(EMRCYCLE) (RS+RST+RH+ (RS+RST+RH+
EMIF read cycle time (EW = 1) ns
(EWC*16))*E–3 (EWC*16))*E+2
Output setup time, EMxCS[y:2] low
(RS)*E–3 (RS)*E+2 ns
to EMxOE low (SS = 0)
4 tsu(EMCEL-EMOEL)
Output setup time, EMxCS[y:2] low
–3 2 ns
to EMxOE low (SS = 1)
Output hold time, EMxOE high to
(RH)*E–3 (RH)*E ns
EMxCS[y:2] high (SS = 0)
5 th(EMOEH-EMCEH)
Output hold time, EMxOE high to
–3 0 ns
EMxCS[y:2] high (SS = 1)
Output setup time, EMxBA[y:0]
6 tsu(EMBAV-EMOEL) (RS)*E–3 (RS)*E+2 ns
valid to EMxOE low
Output hold time, EMxOE high to
7 th(EMOEH-EMBAIV) (RH)*E–3 (RH)*E ns
EMxBA[y:0] invalid
Output setup time, EMxA[y:0] valid
8 tsu(EMAV-EMOEL) (RS)*E–3 (RS)*E+2 ns
to EMxOE low

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NO.(1)
(2) (3) PARAMETER MIN MAX UNIT

Output hold time, EMxOE high to

9 th(EMOEH-EMAIV) (RH)*E–3 (RH)*E ns
EMxA[y:0] invalid
EMxOE active low width (EW = 0) (RST)*E–1 (RST)*E+1 ns
10 tw(EMOEL)
EMxOE active low width (EW = 1) (RST+(EWC*16))*E–1 (RST+(EWC*16))*E+1 ns
Delay time from EMxWAIT
11 td(EMWAITH-EMOEH) 4E+10 5E+15 ns
deasserted to EMxOE high
Output setup time, EMxDQM[y:0]
29 tsu(EMDQMV-EMOEL) (RS)*E–3 (RS)*E+2 ns
valid to EMxOE low
Output hold time, EMxOE high to
30 th(EMOEH-EMDQMIV) (RH)*E–3 (RH)*E ns
EMxDQM[y:0] invalid
Writes
EMIF write cycle time (EW = 0) (WS+WST+WH)*E–3 (WS+WST+WH)*E+1 ns
15 tc(EMWCYCLE) (WS+WST+WH+ (WS+WST+WH+
EMIF write cycle time (EW = 1) ns
(EWC*16))*E–3 (EWC*16))*E+1
Output setup time, EMxCS[y:2] low
(WS)*E–3 (WS)*E+1 ns
to EMxWE low (SS = 0)
16 tsu(EMCEL-EMWEL)
Output setup time, EMxCS[y:2] low
–3 1 ns
to EMxWE low (SS = 1)
Output hold time, EMxWE high to
(WH)*E–3 (WH)*E ns
EMxCS[y:2] high (SS = 0)
17 th(EMWEH-EMCEH)
Output hold time, EMxWE high to
–3 0 ns
EMxCS[y:2] high (SS = 1)
Output setup time, EMxDQM[y:0]
18 tsu(EMDQMV-EMWEL) (WS)*E–3 (WS)*E+1 ns
valid to EMxWE low
Output hold time, EMxWE high to
19 th(EMWEH-EMDQMIV) (WH)*E–3 (WH)*E ns
EMxDQM[y:0] invalid
Output setup time, EMxBA[y:0]
20 tsu(EMBAV-EMWEL) (WS)*E–3 (WS)*E+1 ns
valid to EMxWE low
Output hold time, EMxWE high to
21 th(EMWEH-EMBAIV) (WH)*E–3 (WH)*E ns
EMxBA[y:0] invalid
Output setup time, EMxA[y:0] valid
22 tsu(EMAV-EMWEL) (WS)*E–3 (WS)*E+1 ns
to EMxWE low
Output hold time, EMxWE high to
23 th(EMWEH-EMAIV) (WH)*E–3 (WH)*E ns
EMxA[y:0] invalid
EMxWE active low width
(WST)*E–1 (WST)*E+1 ns
(EW = 0)
24 tw(EMWEL)
EMxWE active low width
(WST+(EWC*16))*E–1 (WST+(EWC*16))*E+1 ns
(EW = 1)
Delay time from EMxWAIT
25 td(EMWAITH-EMWEH) 4E+10 5E+15 ns
deasserted to EMxWE high
Output setup time, EMxD[y:0] valid
26 tsu(EMDV-EMWEL) (WS)*E–3 (WS)*E+1 ns
to EMxWE low
Output hold time, EMxWE high to
27 th(EMWEH-EMDIV) (WH)*E–3 (WH)*E ns
EMxD[y:0] invalid

(1) TA = Turn around, RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold,
MEWC = Maximum external wait cycles. These parameters are programmed through the Asynchronous Bank and Asynchronous Wait
Cycle Configuration Registers. These support the following ranges of values: TA[4–1], RS[16–1], RST[64–4], RH[8–1], WS[16–1],
WST[64–1], WH[8–1], and MEWC[1–256]. See the TMS320F2807x Microcontrollers Technical Reference Manual for more information.
(2) E = EMxCLK period in ns.
(3) EWC = external wait cycles determined by EMxWAIT input signal. EWC supports the following range of values. EWC[256–1]. The
maximum wait time before time-out is specified by bit field MEWC in the Asynchronous Wait Cycle Configuration Register. See the
TMS320F2807x Microcontrollers Technical Reference Manual for more information.

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3
1

EMxCS[y:2]

EMxBA[y:0]

EMxA[y:0]

EMxDQM[y:0]

4 5
8 9
6 7
29 30
10
EMxOE
13
12

EMxD[y:0]

EMxWE

Figure 7-21. Asynchronous Memory Read Timing

SETUP STROBE Extended Due to EMxWAIT STROBE HOLD

EMxCS[y:2]

EMxBA[y:0]

EMxA[y:0]

EMxD[y:0]

14
11
EMxOE

2
2
EMxWAIT Asserted Deasserted

Figure 7-22. EMxWAIT Read Timing Requirements

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15
1

EMxCS[y:2]

EMxBA[y:0]

EMxA[y:0]

EMxDQM[y:0]

16 17
18 19
20 21
24
22 23

EMxWE
27
26

EMxD[y:0]

EMxOE

Figure 7-23. Asynchronous Memory Write Timing

SETUP STROBE Extended Due to EMxWAIT STROBE HOLD

EMxCS[y:2]

EMxBA[y:0]

EMxA[y:0]

EMxD[y:0]

28
25
EMxWE

2
2
EMxWAIT Asserted Deasserted

Figure 7-24. EMxWAIT Write Timing Requirements

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7.9.9.3.2 Synchronous RAM

Section 7.9.9.3.2.1 shows the EMIF synchronous memory timing requirements. Section 7.9.9.3.2.2 shows the
EMIF synchronous memory switching characteristics. Figure 7-25 and Figure 7-26 show the synchronous
memory timing diagrams.
7.9.9.3.2.1 EMIF Synchronous Memory Timing Requirements

NO. MIN MAX UNIT

19 tsu(EMIFDV-EM_CLKH) Input setup time, read data valid on EMxD[y:0] before EMxCLK rising 2 ns
20 th(CLKH-DIV) Input hold time, read data valid on EMxD[y:0] after EMxCLK rising 1.5 ns

7.9.9.3.2.2 EMIF Synchronous Memory Switching Characteristics

NO. PARAMETER MIN MAX UNIT

1 tc(CLK) Cycle time, EMIF clock EMxCLK 10 ns
2 tw(CLK) Pulse width, EMIF clock EMxCLK high or low 3 ns
3 td(CLKH-CSV) Delay time, EMxCLK rising to EMxCS[y:2] valid 8 ns
4 toh(CLKH-CSIV) Output hold time, EMxCLK rising to EMxCS[y:2] invalid 1 ns
5 td(CLKH-DQMV) Delay time, EMxCLK rising to EMxDQM[y:0] valid 8 ns
6 toh(CLKH-DQMIV) Output hold time, EMxCLK rising to EMxDQM[y:0] invalid 1 ns
7 td(CLKH-AV) Delay time, EMxCLK rising to EMxA[y:0] and EMxBA[y:0] valid 8 ns
8 toh(CLKH-AIV) Output hold time, EMxCLK rising to EMxA[y:0] and EMxBA[y:0] invalid 1 ns
9 td(CLKH-DV) Delay time, EMxCLK rising to EMxD[y:0] valid 8 ns
10 toh(CLKH-DIV) Output hold time, EMxCLK rising to EMxD[y:0] invalid 1 ns
11 td(CLKH-RASV) Delay time, EMxCLK rising to EMxRAS valid 8 ns
12 toh(CLKH-RASIV) Output hold time, EMxCLK rising to EMxRAS invalid 1 ns
13 td(CLKH-CASV) Delay time, EMxCLK rising to EMxCAS valid 8 ns
14 toh(CLKH-CASIV) Output hold time, EMxCLK rising to EMxCAS invalid 1 ns
15 td(CLKH-WEV) Delay time, EMxCLK rising to EMxWE valid 8 ns
16 toh(CLKH-WEIV) Output hold time, EMxCLK rising to EMxWE invalid 1 ns
17 td(CLKH-DHZ) Delay time, EMxCLK rising to EMxD[y:0] tri-stated 8 ns
18 toh(CLKH-DLZ) Output hold time, EMxCLK rising to EMxD[y:0] driving 1 ns

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BASIC SDRAM 1
READ OPERATION 2 2
EMxCLK

3 4

EMxCS[y:2]

5 6
EMxDQM[y:0]

7 8
EMxBA[y:0]

7 8
EMxA[y:0]

19
2 EM_CLK Delay
17 20 18

EMxD[y:0]

11 12
EMxRAS
13 14

EMxCAS

EMxWE

Figure 7-25. Basic SDRAM Read Operation

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BASIC SDRAM 1
WRITE OPERATION 2 2

EMxCLK
3 4
EMxCS[y:2]

5 6
EMxDQM[y:0]

7 8
EMxBA[y:0]

7 8
EMxA[y:0]

9
10

EMxD[y:0]
11 12
EMxRAS
13

EMxCAS
15 16

EMxWE

Figure 7-26. Basic SDRAM Write Operation

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7.10 Analog Peripherals

The analog subsystem module is described in this section.
The analog modules on this device include the ADC, temperature sensor, buffered DAC, and CMPSS.
The analog subsystem has the following features:
• Flexible voltage references
– The ADCs are referenced to VREFHIx and VREFLOx pins.
• VREFHIx pin voltage must be driven in externally.
• The buffered DACs are referenced to VREFHIx and VSSA.
– Alternately, these DACs can be referenced to the VDAC pin and VSSA.
• The comparator DACs are referenced to VDDA and VSSA.
– Alternately, these DACs can be referenced to the VDAC pin and VSSA.
• Flexible pin usage
– Buffered DAC and comparator subsystem functions multiplexed with ADC inputs
• Internal connection to VREFLO on all ADCs for offset self-calibration
Figure 7-27 shows the Analog Subsystem Block Diagram for the 176-pin PTP package. Figure 7-28 shows the
Analog Subsystem Block Diagram for the 100-pin PZP package.

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VREFHIA

DACOUTA
VREFHIA VDAC Comparator Subsystem 1
DACOUTA/ADCINA0 0 REFHI CMPIN1P
DACOUTB/ADCINA1 1 DACREFSEL
Digital CTRIP1H
CMPIN1P/ADCINA2 2 VDDA or VDAC Filter CTRIPOUT1H
CMPIN1N/ADCINA3 3
CMPIN2P/ADCINA4 4 12-bit DAC12
CMPIN2N/ADCINA5 5 Buffered
6 DAC DAC12 Digital CTRIP1L
7 ADC-A CMPIN1N Filter CTRIPOUT1L
VREFLOA 8 12-bits VSSA
VREFLOA 9
10 Comparator Subsystem 2

DACOUTB
11 VREFHIA VDAC CMPIN2P
Digital CTRIP2H
12
VDDA or VDAC Filter CTRIPOUT2H
TEMP SENSOR 13 DACREFSEL
CMPIN4P/ADCIN14 14
DAC12
CMPIN4N/ADCIN15 15 REFLO 12-bit
Buffered DAC12 Digital CTRIP2L
VREFLOA DAC Filter
CMPIN2N CTRIPOUT2L
VREFHIB
VSSA
Comparator Subsystem 3
VDAC/ADCINB0 0 REFHI CMPIN3P
DACOUTC/ADCINB1 1 CTRIP3H

DACOUTC
VREFHIB VDAC Digital
CMPIN3P/ADCINB2 2 VDDA or VDAC Filter CTRIPOUT3H
CMPIN3N/ADCINB3 3
DACREFSEL
4 DAC12
5
6 12-bit DAC12 Digital CTRIP3L
7 ADC-B Buffered CMPIN3N Filter CTRIPOUT3L
VREFLOB 8 12-bits DAC
VREFLOB 9
10 VSSA Comparator Subsystem 4
11 CMPIN4P
12 Digital CTRIP4H
13 VDDA or VDAC Filter CTRIPOUT4H
14
DAC12
15 REFLO
DAC12 Digital
VREFLOB CTRIP4L
CMPIN4N Filter CTRIPOUT4L

Comparator Subsystem 5
CMPIN5P
Digital CTRIP5H
CMPIN6P VDDA or VDAC Filter CTRIPOUT5H
CMPIN6N
CMPIN5P DAC12

DAC12 Digital CTRIP5L

Filter CTRIPOUT5L

Comparator Subsystem 6
CMPIN6P
Digital CTRIP6H
VDDA or VDAC Filter CTRIPOUT6H

DAC12

DAC12 Digital CTRIP6L

CMPIN6N Filter CTRIPOUT6L
VREFHID
Comparator Subsystem 7
CMPIN7P/ADCIND0 0 REFHI CMPIN7P
CMPIN7N/ADCIND1 1 Digital CTRIP7H
CMPIN8P/ADCIND2 2 VDDA or VDAC Filter CTRIPOUT7H
CMPIN8N/ADCIND3 3
ADCIND4 4 DAC12
5
6 DAC12 Digital CTRIP7L
7 ADC-D CMPIN7N Filter CTRIPOUT7L
VREFLOD 8 12-bits
VREFLOD 9
10 Comparator Subsystem 8
11 CMPIN8P
12 Digital CTRIP8H
13 VDDA or VDAC Filter CTRIPOUT8H
14
15 DAC12
REFLO
DAC12 Digital CTRIP8L
VREFLOD
CMPIN8N Filter CTRIPOUT8L

Figure 7-27. Analog Subsystem Block Diagram (176-Pin PTP)

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VREFHIA

DACOUTA
VREFHIA VDAC Comparator Subsystem 1
DACOUTA/ADCINA0 0 REFHI CMPIN1P
DACOUTB/ADCINA1 1 DACREFSEL
Digital CTRIP1H
CMPIN1P/ADCINA2 2 VDDA or VDAC Filter CTRIPOUT1H
CMPIN1N/ADCINA3 3
CMPIN2P/ADCINA4 4 12-bit DAC12
CMPIN2N/ADCINA5 5 Buffered
6 DAC DAC12 Digital CTRIP1L
7 ADC-A CMPIN1N Filter CTRIPOUT1L
VREFLOA 8 12-bits VSSA
VREFLOA 9
10 Comparator Subsystem 2

DACOUTB
VREFHIA VDAC CMPIN2P
11
12 Digital CTRIP2H
DACREFSEL VDDA or VDAC Filter CTRIPOUT2H
TEMP SENSOR 13
CMPIN4P/ADCIN14 14
DAC12
CMPIN4N/ADCIN15 15 REFLO 12-bit
Buffered DAC12 CTRIP2L
Digital
VREFLOA DAC
CMPIN2N Filter CTRIPOUT2L
VREFHIB VSSA
Comparator Subsystem 3
VDAC/ADCINB0 0 REFHI CMPIN3P

DACOUTC
DACOUTC/ADCINB1 1 VREFHIB VDAC Digital CTRIP3H
CMPIN3P/ADCINB2 2 VDDA or VDAC Filter CTRIPOUT3H
CMPIN3N/ADCINB3 3 DACREFSEL
ADCINB4 4 DAC12
ADCINB5 5
6 12-bit DAC12 CTRIP3L
Digital
7 ADC-B Buffered
CMPIN3N Filter CTRIPOUT3L
VREFLOB 8 12-bits DAC
VREFLOB 9
10 VSSA Comparator Subsystem 4
11 CMPIN4P
12 Digital CTRIP4H
13 VDDA or VDAC Filter CTRIPOUT4H
14
DAC12
15 REFLO
DAC12 Digital
VREFLOB CTRIP4L
CMPIN4N Filter CTRIPOUT4L

Figure 7-28. Analog Subsystem Block Diagram (100-Pin PZP)

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7.10.1 Analog-to-Digital Converter (ADC)

The ADCs on this device are successive approximation (SAR) style ADCs with 12-bit resolution. There are
multiple ADC modules which allow simultaneous sampling. The ADC wrapper is start-of-conversion (SOC)
based [see the SOC Principle of Operation section of the TMS320F2807x Microcontrollers Technical Reference
Manual .
Each ADC has the following features:
• 12-bit resolution
• Ratiometric external reference set by VREFHI and VREFLO
• Single-ended signal conversions
• Input multiplexer with up to 16 channels
• 16 configurable SOCs
• 16 individually addressable result registers
• Multiple trigger sources
– Software immediate start
– All ePWMs
– GPIO XINT2
– CPU timers
– ADCINT1 or 2
• Four flexible PIE interrupts
• Burst mode
• Four post-processing blocks, each with:
– Saturating offset calibration
– Error from setpoint calculation
– High, low, and zero-crossing compare, with interrupt and ePWM trip capability
– Trigger-to-sample delay capture

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Figure 7-29 shows the ADC module block diagram.

Analog to Digital Core Analog to Digital Wrapper Logic

SIGNALMODE
SIGNALMODE

Input Circuit RESOLUTION RESOLUTION

TRIGSEL
SOCx (0-15)

Triggers
CHSEL [15:0]
SOC
[15:0]
ADCSOC Arbitration ACQPS
ADCIN0 0
ADCIN1 1 & Control [15:0]
CHSEL
ADCIN2 2
ADCIN3 3

SOCxSTART[15:0]

...
...
ADCIN4 4
ADCIN5

EOCx[15:0]
5
ADCIN6 6
xV1IN+
ADCCOUNTER TRIGGER[15:0]
ADCIN7 7
u
DOUT1
ADCIN8 8
xV
ADCIN9 9
2 IN-

ADCIN10 10
ADCIN11 11 SOC Delay Trigger
ADCIN12 12
S/H Circuit Converter Timestamp Timestamp
ADCIN13 13
ADCIN14 14
ADCIN15 15 RESULT + -
S ADCPPBxOFFCAL

ADCRESULT
0–15 Regs
saturate

ADCPPBxOFFREF
+ -
S ADCPPBxRESULT

VREFHI Event
ADCEVT
CONFIG ADCEVTINT
Logic
VREFLO
Reference Voltage Levels Post Processing Block (1-4)

Interrupt Block (1-4)

ADCINT1-4

Figure 7-29. ADC Module Block Diagram

7.10.1.1 ADC Configurability

Some ADC configurations are individually controlled by the SOCs, while others are controlled by each ADC
module. Table 7-7 summarizes the basic ADC options and their level of configurability.
Table 7-7. ADC Options and Configuration Levels
OPTIONS CONFIGURABILITY
Clock By the module(1)
Resolution Not configurable (12-bit resolution only)
Signal mode Not configurable (single-ended signal mode only)
Reference voltage source Not configurable (external reference only)
Trigger source By the SOC(1)
Converted channel By the SOC
Acquisition window duration By the SOC(1)
EOC location By the module
Burst mode By the module(1)

(1) Writing these values differently to different ADC modules could cause the ADCs to operate
asynchronously. For guidance on when the ADCs are operating synchronously or asynchronously,
see the Ensuring Synchronous Operation section of the Analog-to-Digital Converter (ADC) chapter
in the TMS320F2807x Microcontrollers Technical Reference Manual.

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7.10.1.1.1 Signal Mode

The ADC supports single-ended signaling. In single-ended mode, the input voltage to the converter is sampled
through a single pin (ADCINx), referenced to VREFLO. Figure 7-30 shows the single-ended signaling mode.

Pin Voltage
VREFHI
VREFHI

ADCINx ADCINx

VREFHI/2 ADC

VREFLO
VREFLO
(VSSA)

Digital Output
2n - 1

ADC Vin

Figure 7-30. Single-ended Signaling Mode

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7.10.1.2 ADC Electrical Data and Timing

Section 7.10.1.2.1 shows the ADC operating conditions. Section 7.10.1.2.2 shows the ADC characteristics.
Section 7.10.1.2.3 shows the ADCEXTSOC timing requirements.

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7.10.1.2.1 ADC Operating Conditions

over recommended operating conditions (unless otherwise noted)
MIN TYP MAX UNIT
ADCCLK (derived from PERx.SYSCLK) 5 50 MHz
Sample window duration (set by ACQPS and PERx.SYSCLK)(1) 100 ns
VREFHI 2.4 2.5 or 3.0 VDDA V
VREFLO VSSA 0 VSSA V
VREFHI – VREFLO 2.4 VDDA V
ADC input conversion range VREFLO VREFHI V

(1) The sample window must also be at least as long as 1 ADCCLK cycle for correct ADC operation.

Note
The ADC inputs should be kept below VDDA + 0.3 V during operation. If an ADC input exceeds this
level, the VREF internal to the device may be disturbed, which can impact results for other ADC or
DAC inputs using the same VREF.

Note
The VREFHI pin must be kept below VDDA + 0.3 V to ensure proper functional operation. If the VREFHI
pin exceeds this level, a blocking circuit may activate, and the internal value of VREFHI may float to 0 V
internally, giving improper ADC conversion or DAC output.

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7.10.1.2.2 ADC Characteristics

over recommended operating conditions (unless otherwise noted)(5)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ADC conversion cycles(1) 10.1 11 ADCCLKs
Power-up time 500 µs
Gain error –5 ±3 5 LSBs
Offset error –4 ±2 4 LSBs
Channel-to-channel gain error ±4 LSBs
Channel-to-channel offset error ±2 LSBs
ADC-to-ADC gain error Identical VREFHI and VREFLO for all ADCs ±4 LSBs
ADC-to-ADC offset error Identical VREFHI and VREFLO for all ADCs ±2 LSBs
DNL(2) > –1 ±0.5 1 LSBs
INL –2 ±1.0 2 LSBs
SNR(3) (10) VREFHI = 2.5 V, fin = 100 kHz 68.8 dB
THD(3) (10) VREFHI = 2.5 V, fin = 100 kHz –78.4 dB
SFDR(3) (10) VREFHI = 2.5 V, fin = 100 kHz 79.2 dB
SINAD(3) (10) VREFHI = 2.5 V, fin = 100 kHz 68.4 dB
VREFHI = 2.5 V, fin = 100 kHz,
11.1
single ADC(6), all packages
VREFHI = 2.5 V, fin = 100 kHz,
11.1
synchronous ADCs(7), all packages

ENOB(3) (10) VREFHI = 2.5 V, fin = 100 kHz, bits

Not
asynchronous ADCs(8),
supported
100-pin PZP package
VREFHI = 2.5 V, fin = 100 kHz,
asynchronous ADCs(8), 9.7
176-pin PTP package
VDDA = 3.3-V DC + 200 mV
PSRR 60 dB
DC up to Sine at 1 kHz
VDDA = 3.3-V DC + 200 mV
PSRR 57 dB
Sine at 800 kHz
VREFHI = 2.5 V, synchronous ADCs(7), all
–1 1
packages
VREFHI = 2.5 V, asynchronous ADCs(8), Not
ADC-to-ADC isolation(10) (4) (9) LSBs
100-pin PZP package supported
VREFHI = 2.5 V, asynchronous ADCs(8),
–9 9
176-pin PTP package
VREFHI input current 130 µA

(1) See Section 7.10.1.2.5.

(2) No missing codes.
(3) AC parameters will be impacted by clock source accuracy and jitter, this should be taken into account when selecting the clock source
for the system. The clock source used for these parameters was a high-accuracy external clock fed through the PLL. The on-chip
Internal Oscillator has higher jitter than an external crystal and these parameters will degrade if it is used as a clock source.
(4) Maximum DC code deviation due to operation of multiple ADCs simultaneously.
(5) Typical values are measured with VREFHI = 2.5 V and VREFLO = 0 V. Minimum and Maximum values are tested or characterized with
VREFHI = 2.5 V and VREFLO = 0 V.
(6) One ADC operating while all other ADCs are idle.
(7) All ADCs operating with identical ADCCLK, S+H durations, triggers, and resolution.
(8) Any ADCs operating with heterogeneous ADCCLK, S+H durations, triggers, or resolution.
(9) Value based on characterization.
(10) I/O activity is minimized on pins adjacent to ADC input and VREFHI pins as part of best practices to reduce capacitive coupling and
crosstalk.

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7.10.1.2.3 ADCEXTSOC Timing Requirements

MIN(1) MAX UNIT

Synchronous 2tc(SYSCLK) cycles
tw(INT) Pulse duration, INT input low/high
With qualifier tw(IQSW) + tw(SP) + 1tc(SYSCLK) cycles

(1) For an explanation of the input qualifier parameters, see Section 7.9.6.2.1.

7.10.1.2.4 ADC Input Model

Note
ADC channels ADCINA0, ADCINA1, and ADCINB1 have a 50-kΩ pulldown resistor to VSSA.

7.10.1.2.4.1 Single-Ended Input Model Parameters

DESCRIPTION VALUE
Cp Parasitic input capacitance See Table 7-8
Ron Sampling switch resistance 600 Ω
Ch Sampling capacitor 16.5 pF
Rs Nominal source impedance 50 Ω

ADC
ADCINx
Rs
Switch Ron
AC Cp Ch

VREFLO

Figure 7-31. Single-Ended Input Model

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Table 7-8 shows the parasitic capacitance on each channel. Also, enabling a comparator adds approximately
1.4 pF of capacitance on positive comparator inputs and 2.5 pF of capacitance on negative comparator inputs.
Table 7-8. Per-Channel Parasitic Capacitance
Cp (pF)
ADC CHANNEL
COMPARATOR DISABLED COMPARATOR ENABLED
ADCINA0 12.9 N/A
ADCINA1 10.3 N/A
ADCINA2 5.9 7.3
ADCINA3 6.3 8.8
ADCINA4 5.9 7.3
ADCINA5 6.3 8.8
ADCINB0(1) 117.0 N/A
ADCINB1 10.6 N/A
ADCINB2 5.9 7.3
ADCINB3 6.2 8.7
ADCINB4 5.2 N/A
ADCINB5 5.1 N/A
ADCIND0 5.3 6.7
ADCIND1 5.7 8.2
ADCIND2 5.3 6.7
ADCIND3 5.6 8.1
ADCIND4 4.3 N/A
ADCIN14 8.6 10.0
ADCIN15 9.0 11.5

(1) The increased capacitance is due to VDAC functionality.

This input model should be used along with actual signal source impedance to determine the acquisition window
duration. See the Choosing an Acquisition Window Duration section of the TMS320F2807x Microcontrollers
Technical Reference Manual for more information.
The user should analyze the ADC input setting assuming worst-case initial conditions on Ch. This will require
assuming that Ch could start the S+H window completely charged to VREFHI or completely discharged to VREFLO.
When the ADC transitions from an odd-numbered channel to an even-numbered channel, or vice-versa, the
actual initial voltage on Ch will be close to being completely discharged to VREFLO. For even-to-even or odd-to-
odd channel transitions, the initial voltage on Ch will be close to the voltage of the previously converted channel.

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7.10.1.2.5 ADC Timing Diagrams

Section 7.10.1.2.5.1 lists the ADC timings in 12-bit mode (SYSCLK cycles). Figure 7-32 shows the ADC
conversion timings for two SOCs given the following assumptions:
• SOC0 and SOC1 are configured to use the same trigger.
• No other SOCs are converting or pending when the trigger occurs.
• The round robin pointer is in a state that causes SOC0 to convert first.
• ADCINTSEL is configured to set an ADCINT flag upon end of conversion for SOC0 (whether this flag
propagates through to the CPU to cause an interrupt is determined by the configurations in the PIE module).
Table 7-9 lists the descriptions of the ADC timing parameters that are in Figure 7-32 .
Table 7-9. ADC Timing Parameters
PARAMETER DESCRIPTION
The duration of the S+H window.

At the end of this window, the value on the S+H capacitor becomes the voltage to be converted into a digital
value. The duration is given by (ACQPS + 1) SYSCLK cycles. ACQPS can be configured individually for each
tSH
SOC, so tSH will not necessarily be the same for different SOCs.

Note: The value on the S+H capacitor will be captured approximately 5 ns before the end of the S+H window
regardless of device clock settings.
The time from the end of the S+H window until the ADC conversion results latch in the ADCRESULTx register.
tLAT
If the ADCRESULTx register is read before this time, the previous conversion results will be returned.
The time from the end of the S+H window until the next ADC conversion S+H window can begin. The
tEOC
subsequent sample can start before the conversion results are latched.
The time from the end of the S+H window until an ADCINT flag is set (if configured).

If the INTPULSEPOS bit in the ADCCTL1 register is set, tINT will coincide with the conversion results being
latched into the result register.
tINT
If the INTPULSEPOS bit is 0, tINT will coincide with the end of the S+H window. If tINT triggers a read of the
ADC result register (directly through DMA or indirectly by triggering an ISR that reads the result), care must be
taken to ensure the read occurs after the results latch (otherwise, the previous results will be read).

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7.10.1.2.5.1 ADC Timings in 12-Bit Mode (SYSCLK Cycles)

ADCCLK
ADCCLK PRESCALE SYSCLK CYCLES
CYCLES
ADCCTL2 RATIO
tEOC tLAT (1) tINT(EARLY) tINT(LATE) tEOC
[PRESCALE] ADCCLK:SYSCLK
0 1 11 13 1 11 11.0
1 1.5 Invalid
2 2 21 23 1 21 10.5
3 2.5 26 28 1 26 10.4
4 3 31 34 1 31 10.3
5 3.5 36 39 1 36 10.3
6 4 41 44 1 41 10.3
7 4.5 46 49 1 46 10.2
8 5 51 55 1 51 10.2
9 5.5 56 60 1 56 10.2
10 6 61 65 1 61 10.2
11 6.5 66 70 1 66 10.2
12 7 71 76 1 71 10.1
13 7.5 76 81 1 76 10.1
14 8 81 86 1 81 10.1
15 8.5 86 91 1 86 10.1

(1) Refer to the "ADC: DMA Read of Stale Result" advisory in the TMS320F2807x MCUs Silicon Errata .

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Sample n

Input on SOC0.CHSEL

Input on SOC1.CHSEL
Sample n+1

ADC S+H SOC0 SOC1

SYSCLK

ADCCLK

ADCTRIG

ADCSOCFLG.SOC0

ADCSOCFLG.SOC1

ADCRESULT0 (old data) Sample n

ADCRESULT1 (old data) Sample n+1

ADCINTFLG.ADCINTx

tSH tLAT

tEOC

tINT

Figure 7-32. ADC Timings for 12-Bit Mode

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7.10.1.3 Temperature Sensor Electrical Data and Timing

The temperature sensor can be used to measure the device junction temperature. The temperature sensor is
sampled through an internal connection to the ADC and translated into a temperature through TI-provided
software. When sampling the temperature sensor, the ADC must meet the acquisition time in Section 7.10.1.3.1.
7.10.1.3.1 Temperature Sensor Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER MIN TYP MAX UNIT
Temperature accuracy ±15 °C
Start-up time (TSNSCTL[ENABLE] to sampling temperature sensor) 500 µs
ADC acquisition time 700 ns

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7.10.2 Comparator Subsystem (CMPSS)

Each CMPSS module includes two comparators, two internal voltage reference DACs (CMPSS DACs), two
digital glitch filters, and one ramp generator. There are two inputs, CMPINxP and CMPINxN. Each of these
inputs will be internally connected to an ADCIN pin. The CMPINxP pin is always connected to the positive input
of the CMPSS comparators. CMPINxN can be used instead of the DAC output to drive the negative comparator
inputs. There are two comparators, and therefore two outputs from the CMPSS module, which are connected to
the input of a digital filter module before being passed on to the Comparator TRIP crossbar and either PWM
modules or directly to a GPIO pin. Figure 7-33 shows CMPSS connectivity on the 176-pin PTP package. Figure
7-34 shows CMPSS connectivity on the 100-pin PZP package.
Comparator Subsystem 1
CMPIN1P Pin CTRIP1H
Digital
VDDA or VDAC Filter CTRIPOUT1H

DAC12
CTRIP1H
CTRIP1L
DAC12 CTRIP1L CTRIP2H
Digital
CTRIPOUT1L CTRIP2L ePWMs
CMPIN1N Pin Filter ePWM X-BAR

Comparator Subsystem 2 CTRIP8H

CMPIN2P Pin CTRIP2H CTRIP8L
Digital
VDDA or VDAC Filter CTRIPOUT2H

DAC12

DAC12 CTRIP2L
Digital
Filter CTRIPOUT2L
CMPIN2N Pin

CTRIPOUT1H
CTRIPOUT1L
Comparator Subsystem 8 CTRIPOUT2H
CMPIN8P Pin CTRIP8H CTRIPOUT2L
Digital Output X-BAR GPIO Mux
VDDA or VDAC Filter CTRIPOUT8H
CTRIPOUT8H
DAC12 CTRIPOUT8L
DAC12 CTRIP8L
Digital
Filter CTRIPOUT8L
CMPIN8N Pin

Figure 7-33. CMPSS Connectivity (176-Pin PTP)

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Comparator Subsystem 1
CMPIN1P Pin CTRIP1H
Digital
VDDA or VDAC Filter CTRIPOUT1H
CTRIP1H
DAC12
CTRIP1L
DAC12 CTRIP1L CTRIP2H
Digital CTRIP2L
Filter CTRIPOUT1L ePWM X-BAR ePWMs
CMPIN1N Pin CTRIP3H
CTRIP3L
CTRIP4H
Comparator Subsystem 2
CMPIN2P Pin CTRIP4L
CTRIP2H
Digital
VDDA or VDAC Filter CTRIPOUT2H

DAC12

DAC12 CTRIP2L
Digital
Filter CTRIPOUT2L
CMPIN2N Pin

Comparator Subsystem 3
CMPIN3P Pin CTRIP3H
Digital
VDDA or VDAC Filter CTRIPOUT3H CTRIPOUT1H
CTRIPOUT1L
DAC12 CTRIPOUT2H
CTRIPOUT2L Output X-BAR
CTRIP3L GPIO Mux
DAC12 Digital CTRIPOUT3H
Filter CTRIPOUT3L CTRIPOUT3L
CMPIN3N Pin
CTRIPOUT4H
CTRIPOUT4L
Comparator Subsystem 4
CMPIN4P Pin CTRIP4H
Digital
VDDA or VDAC Filter CTRIPOUT4H

DAC12

DAC12 CTRIP4L
Digital
Filter CTRIPOUT4L
CMPIN4N Pin

Figure 7-34. CMPSS Connectivity (100-Pin PZP)

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7.10.2.1 CMPSS Electrical Data and Timing

Section 7.10.2.1.1 shows the comparator electrical characteristics. Figure 7-35 shows the CMPSS comparator
input referred offset. Figure 7-36 shows the CMPSS comparator hysteresis.
7.10.2.1.1 Comparator Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Power-up time 500(2) µs
Comparator input (CMPINxx) range 0 VDDA V
Low common mode, inverting input set
Input referred offset error –20 20 mV
to 50 mV
1x 12
2x 24 CMPSS
Hysteresis(1)
3x 36 DAC LSB

4x 48
Step response 21 60
Response time (delay from CMPINx input change
Ramp response (1.65 V/µs) 26 ns
to output on ePWM X-BAR or Output X-BAR)
Ramp response (8.25 mV/µs) 30
Common Mode Rejection Ratio (CMRR) 40 dB

(1) The CMPSS DAC is used as the reference to determine how much hysteresis to apply. Therefore, hysteresis will scale with the
CMPSS DAC reference voltage. Hysteresis is available for all comparator input source configurations.
(2) See the "Analog Bandgap References" advisory of the TMS320F2807x MCUs Silicon Errata .

Note
The CMPSS inputs must be kept below VDDA + 0.3 V to ensure proper functional operation. If a
CMPSS input exceeds this level, an internal blocking circuit will isolate the internal comparator from
the external pin until the external pin voltage returns below VDDA + 0.3 V. During this time, the internal
comparator input will be floating and can decay below VDDA within approximately 0.5 µs. After this
time, the comparator could begin to output an incorrect result depending on the value of the other
comparator input.

Input Referred Offset

CTRIPx
Logic Level CTRIPx = 1

CTRIPx = 0

COMPINxP
Voltage
0 CMPINxN or
DACxVAL

Figure 7-35. CMPSS Comparator Input Referred Offset

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Hysteresis

CTRIPx
Logic Level CTRIPx = 1

CTRIPx = 0

COMPINxP
Voltage
0 CMPINxN or
DACxVAL

Figure 7-36. CMPSS Comparator Hysteresis

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Section 7.10.2.1.2 shows the CMPSS DAC static electrical characteristics. Figure 7-37 shows the CMPSS DAC
static offset. Figure 7-38 shows the CMPSS DAC static gain. Figure 7-39 shows the CMPSS DAC static linearity.
7.10.2.1.2 CMPSS DAC Static Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Internal reference 0 VDDA (1)
CMPSS DAC output range V
External reference 0 VDAC
Static offset error(2) –25 25 mV
Static gain error(2) –2 2 % of FSR
Static DNL Endpoint corrected >–1 4 LSB
Static INL Endpoint corrected –16 16 LSB
Settling to 1 LSB after full-scale output
Settling time 1 µs
change
Resolution 12 bits
Error induced by comparator trip or
CMPSS DAC output disturbance(3) CMPSS DAC code change within the –100 100 LSB
same CMPSS module
CMPSS DAC disturbance time(3) 200 ns
VDAC reference voltage When VDAC is reference 2.4 2.5 or 3.0 VDDA V
VDAC load(4) When VDAC is reference 6 kΩ

(1) The maximum output voltage is VDDA when VDAC > VDDA.
(2) Includes comparator input referred errors.
(3) Disturbance error may be present on the CMPSS DAC output for a certain amount of time after a comparator trip.
(4) Per active CMPSS module.

Offset Error

Figure 7-37. CMPSS DAC Static Offset

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Ideal Gain

Actual Gain

Actual Linear Range

Figure 7-38. CMPSS DAC Static Gain

Linearity Error

Figure 7-39. CMPSS DAC Static Linearity

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7.10.3 Buffered Digital-to-Analog Converter (DAC)

The buffered DAC module consists of an internal 12-bit DAC and an analog output buffer that is capable of
driving an external load. An integrated pulldown resistor on the DAC output helps to provide a known pin voltage
when the output buffer is disabled. This pulldown resistor cannot be disabled and remains as a passive
component on the pin, even for other shared pin mux functions. Software writes to the DAC value register can
take effect immediately or can be synchronized with EPWMSYNCPER events.
Each buffered DAC has the following features:
• 12-bit programmable internal DAC
• Selectable reference voltage
• Pulldown resistor on output
• Ability to synchronize with EPWMSYNCPER
The block diagram for the buffered DAC is shown in Figure 7-40.
DACCTL[DACREFSEL]

VDAC
0
DACREF
VREFHI 1

VDDA
SYSCLK > DACCTL[LOADMODE]

DACVALS D Q 0
12-bit DACOUT
DACVALA DAC Buffer
D Q 1
RPD
EPWM1SYNCPER 0
EPWM2SYNCPER 1 EN
EPWM3SYNCPER 2 VSSA VSSA
... Y
EPWMnSYNCPER n-1

DACCTL[SYNCSEL]
Figure 7-40. DAC Module Block Diagram

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7.10.3.1 Buffered DAC Electrical Data and Timing

Section 7.10.3.1.1 shows the buffered DAC electrical characteristics. Figure 7-41 shows the buffered DAC offset.
Figure 7-42 shows the buffered DAC gain. Figure 7-43 shows the buffered DAC linearity.
7.10.3.1.1 Buffered DAC Electrical Characteristics
over recommended operating conditions (unless otherwise noted)(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Power-up time 500(8) µs
Offset error Midpoint –10 10 mV
Gain error(2) –2.5 2.5 % of FSR
DNL(3) Endpoint corrected > –1 ±0.4 1 LSB
INL Endpoint corrected –5 ±2 5 LSB
Settling to 2 LSBs after 0.3V-to-3V
DACOUTx settling time 2 µs
transition
Resolution 12 bits
Voltage output range(4) 0.3 VDDA – 0.3 V
Capacitive load Output drive capability 100 pF
Resistive load Output drive capability 5 kΩ
RPD pulldown resistor 50 kΩ
Reference voltage(5) VDAC or VREFHI 2.4 2.5 or 3.0 VDDA V
Reference input resistance(6) VDAC or VREFHI 170 kΩ
Integrated noise from 100 Hz to 100 kHz 500 µVrms
Output noise
Noise density at 10 kHz 711 nVrms/√Hz
Glitch energy 1.5 V-ns
DC up to 1 kHz 70
PSRR(7) dB
100 kHz 30
SNR 1020 Hz 67 dB
THD 1020 Hz –63 dB
1020 Hz, including harmonics and spurs 66
SFDR dBc
1020 Hz, including only spurs 104

(1) Typical values are measured with VREFHI = 3.3 V unless otherwise noted. Minimum and Maximum values are tested or characterized
with VREFHI = 2.5 V.
(2) Gain error is calculated for linear output range.
(3) The DAC output is monotonic.
(4) This is the linear output range of the DAC. The DAC can generate voltages outside this range, but the output voltage will not be linear
due to the buffer.
(5) For best PSRR performance, VDAC or VREFHI should be less than VDDA.
(6) Per active Buffered DAC module.
(7) VREFHI = 3.2 V, VDDA = 3.3 V DC + 100 mV Sine.
(8) See the "Analog Bandgap References" advisory of the TMS320F2807x MCUs Silicon Errata .

Note
The VDAC pin must be kept below VDDA + 0.3 V to ensure proper functional operation. If the VDAC
pin exceeds this level, a blocking circuit may activate, and the internal value of VDAC may float to 0 V
internally, giving improper DAC output.

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Note
The VREFHI pin must be kept below VDDA + 0.3 V to ensure proper functional operation. If the VREFHI
pin exceeds this level, a blocking circuit may activate, and the internal value of VREFHI may float to 0 V
internally, giving improper ADC conversion or DAC output.

Offset Error

Code 2048

Figure 7-41. Buffered DAC Offset

Actual Gain

Ideal Gain

Code 373 Code 3722

Linear Range
(3.3-V Reference)

Figure 7-42. Buffered DAC Gain

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Linearity Error

Code 373 Code 3722

Linear Range
(3.3-V Reference)

Figure 7-43. Buffered DAC Linearity

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7.11 Control Peripherals

Note
For the actual number of each peripheral on a specific device, see Table 5-1.

7.11.1 Enhanced Capture (eCAP)

The eCAP module can be used in systems where accurate timing of external events is important.
Applications for eCAP include:
• Speed measurements of rotating machinery (for example, toothed sprockets sensed through Hall sensors)
• Elapsed time measurements between position sensor pulses
• Period and duty cycle measurements of pulse train signals
• Decoding current or voltage amplitude derived from duty cycle encoded current/voltage sensors
The eCAP module includes the following features:
• 4-event time-stamp registers (each 32 bits)
• Edge-polarity selection for up to four sequenced time-stamp capture events
• Interrupt on either of the four events
• Single shot capture of up to four event timestamps
• Continuous mode capture of timestamps in a four-deep circular buffer
• Absolute time-stamp capture
• Difference (Delta) mode time-stamp capture
• All of the above resources dedicated to a single input pin
• When not used in capture mode, the eCAP module can be configured as a single-channel PWM output
(APWM).
The eCAP inputs connect to any GPIO input through the Input X-BAR. The APWM outputs connect to GPIO pins
through the Output X-BAR to OUTPUTx positions in the GPIO mux. See Section 6.4.2 and Section 6.4.3.
Figure 7-44 shows the block diagram of an eCAP module.

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CTRPHS
(phase register−32 bit) APWM mode

SYNC
SYNCIn
OVF CTR_OVF
TSCTR CTR [0−31]
SYNCOut PWM
(counter−32 bit) Delta−mode PRD [0−31] compare
RST
logic
CMP [0−31]
32

CTR [0−31] CTR=PRD

CTR=CMP
32
PRD [0−31]

eCAPx

MODE SELECT
32 CAP1 LD1 Polarity
LD
(APRD active) select

APRD 32
shadow CMP [0−31]
32

32 CAP2 LD2 Polarity

LD
(ACMP active) select

Event Event
32 ACMP
qualifier
shadow Prescale

32 Polarity
CAP3 LD3 select
LD
(APRD shadow)

32 CAP4 LD4
LD Polarity
(ACMP shadow) select

4
Capture events 4

CEVT[1:4]

Interrupt Continuous /
to PIE Trigger Oneshot
and CTR_OVF Capture Control
Flag
CTR=PRD
control
CTR=CMP

Figure 7-44. eCAP Block Diagram

The eCAP module is clocked by PERx.SYSCLK.

The clock enable bits (ECAP1–ECAP6) in the PCLKCR3 register turn off the eCAP module individually (for low-
power operation). Upon reset, ECAP1ENCLK is set to low, indicating that the peripheral clock is off.

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7.11.1.1 eCAP Electrical Data and Timing

Section 7.11.1.1.1 shows the eCAP timing requirement and Section 7.11.1.1.2 shows the eCAP switching
characteristics.
7.11.1.1.1 eCAP Timing Requirement

MIN(1) MAX UNIT

Asynchronous 2tc(SYSCLK) cycles
tw(CAP) Capture input pulse width Synchronous 2tc(SYSCLK) cycles
With input qualifier 1tc(SYSCLK) + tw(IQSW) cycles

(1) For an explanation of the input qualifier parameters, see Section 7.9.6.2.1.

7.11.1.1.2 eCAP Switching Characteristics

over recommended operating conditions (unless otherwise noted)
PARAMETER MIN MAX UNIT
tw(APWM) Pulse duration, APWMx output high/low 20 ns

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7.11.2 Enhanced Pulse Width Modulator (ePWM)

The ePWM peripheral is a key element in controlling many of the power electronic systems found in both
commercial and industrial equipment. The ePWM type-4 module is able to generate complex pulse width
waveforms with minimal CPU overhead by building the peripheral up from smaller modules with separate
resources that can operate together to form a system. Some of the highlights of the ePWM type-4 module
include complex waveform generation, dead-band generation, a flexible synchronization scheme, advanced trip-
zone functionality, and global register reload capabilities.
Figure 7-45 shows the signal interconnections with the ePWM. Figure 7-46 shows the ePWM trip input
connectivity.

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TBCTL2[SYNCOSELX]
Time-Base (TB)
Disable 00
CTR=CMPC 01
TBPRD Shadow (24) CTR=CMPD 10
TBPRDHR (8) Rsvd 11 CTR=ZERO Sync EPWMxSYNCO
TBPRD Active (24) Out
TBCTL[SWFSYNC] CTR=CMPB
8 Select
CTR=PRD EPWMxSYNCI

TBCTL[PHSEN] TBCTL[SYNCOSEL]
Counter DCAEVT1.sync
(A)

Up/Down (A)
DCBEVT1.sync
(16 Bit)
CTR=ZERO
TBCTR
Active (16) CTR_Dir
CTR=PRD
EPWMx_INT
TBPHSHR (8) CTR=ZERO
16 8 CTR=PRD or ZERO
Phase EPWMxSOCA On-chip
TBPHS Active (24) CTR=CMPA Event
Control ADC
CTR=CMPB Trigger EPWMxSOCB
CTR=CMPC and
Interrupt
CTR=CMPD (ET) ADCSOCOUTSELECT
Counter Compare (CC)
Action CTR_Dir
Qualifier (A) Select and pulse stretch
CTR=CMPA (AQ) DCAEVT1.soc
(A) for external ADC
DCBEVT1.soc
CMPAHR (8)
ADCSOCAO
16 ADCSOCBO
HiRes PWM (HRPWM)
CMPA Active (24) CMPAHR (8)

CMPA Shadow (24) EPWMA ePWMxA

Dead PWM Trip

CTR=CMPB Chopper Zone
Band
CMPBHR (8) (DB) (PC) (TZ)
16
EPWMB ePWMxB
CMPB Active (24)

CMPB Shadow (24)

CMPBHR (8)
EPWMx_TZ_INT
TBCNT(16) TZ1 to TZ3
CTR=CMPC
CTR=ZERO EMUSTOP
CMPC[15-0] 16 DCAEVT1.inter CLOCKFAIL
DCBEVT1.inter
EQEPxERR
CMPC Active (16) DCAEVT2.inter (A)
DCBEVT2.inter DCAEVT1.force
(A)
CMPC Shadow (16) DCAEVT2.force
(A)
DCBEVT1.force
(A)
TBCNT(16) DCBEVT2.force
CTR=CMPD

CMPD[15-0] 16

CMPD Active (16)

CMPD Shadow (16)

Copyright © 2017, Texas Instruments Incorporated

A. These events are generated by the ePWM digital compare (DC) submodule based on the levels of the TRIPIN inputs.

Figure 7-45. ePWM Submodules and Critical Internal Signal Interconnects

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GPIO0 Async/
INPUT14 XINT5 PIE(s),
Sync/ Input X-Bar CLA(s)
INPUT13 XINT4
Sync+Filter
GPIOx

INPUT10

INPUT12
INPUT11
INPUT1
INPUT2
INPUT3
INPUT4
INPUT5
INPUT6

INPUT7
INPUT8
INPUT9
eCAP6
eCAP5
XINT1 eCAP4
PIE(s),
XINT2 eCAP3
CLA(s)
XINT3 eCAP2
eCAP1
ADC EXTSYNCIN1 ePWM and eCAP
Wrapper(s) Sync Chain
EXTSYNCIN2

TZ1
TZ2 EPWMINT PIE(s),
TZ3 TZINT CLA(s)
TRIP1
EPWMx.EPWMCLK
TRIP2 EPWMENCLK
TRIP3 TBCLKSYNC
TRIP6
TRIP4
ADCSOCAO Select Ckt
TRIP5
TRIP7
ePWM TRIP8 ADCSOCBO Select Ckt
X-Bar TRIP9 All
TRIP10 ePWM SOCA ADC
TRIP11 Modules Wrapper(s)
TRIP12 SOCB
Reserved TRIP13
ECCERR TRIP14
CPU1.PIEVECTERROR TRIP15 SD1
EQEPERR TZ4 Filter-Reset FLT1
PWM11.CMPC FLT1
CLKFAIL TZ5 Filter-Reset FLT1
CPU1.EMUSTOP TZ6 PWM11.CMPD FLT1
EPWMn.EMUSTOP
Filter-Reset FLT1
PWM12.CMPC FLT1
PWM12.CMPD Filter-Reset FLT1
FLT1
SD2

EPWMSYNCPER CMPSS
DAC

Figure 7-46. ePWM Trip Input Connectivity

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7.11.2.1 Control Peripherals Synchronization

The ePWM and eCAP synchronization chain allows synchronization between multiple modules for the system.
Figure 7-47 shows the synchronization chain architecture.
EXTSYNCIN1 EXTSYNCIN2

EPWM1
EPWM1SYNCOUT

EPWM2

EPWM3 EPWM4
EPWM4SYNCOUT

EPWM5

SYNCSEL.EPWM4SYNCIN
EPWM6
EPWM7 EXTSYNCOUT
EPWM7SYNCOUT
Pulse-Stretched
(8 PLLSYSCLK
Cycles)
EPWM8

SYNCSEL.EPWM7SYNCIN

EPWM9
EPWM10 EPWM10SYNCOUT

EPWM11
SYNCSEL.EPWM10SYNCIN

EPWM12 ECAP1
ECAP1SYNCOUT

ECAP2
SYNCSEL.ECAP1SYNCIN

ECAP3 ECAP4

SYNCSEL.ECAP4SYNCIN SYNCSEL.SYNCOUT
ECAP5

ECAP6

Figure 7-47. Synchronization Chain Architecture

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7.11.2.2 ePWM Electrical Data and Timing

Section 7.11.2.2.1 shows the PWM timing requirements and Section 7.11.2.2.2 shows the PWM switching
characteristics.
7.11.2.2.1 ePWM Timing Requirements

MIN(1) MAX UNIT

f(EPWM) Frequency, EPWMCLK(2) 100 MHz
Asynchronous 2tc(EPWMCLK) cycles
tw(SYNCIN) Sync input pulse width Synchronous 2tc(EPWMCLK) cycles
With input qualifier 1tc(EPWMCLK) + tw(IQSW) cycles

(1) For an explanation of the input qualifier parameters, see Section 7.9.6.2.1.
(2) For SYSCLK above 100 MHz, the EPWMCLK must be half of SYSCLK.

7.11.2.2.2 ePWM Switching Characteristics

over recommended operating conditions (unless otherwise noted)
PARAMETER MIN MAX UNIT
tw(PWM) Pulse duration, PWMx output high/low 20 ns
tw(SYNCOUT) Sync output pulse width 8tc(SYSCLK) cycles
Delay time, trip input active to PWM forced high
td(TZ-PWM) Delay time, trip input active to PWM forced low 25 ns
Delay time, trip input active to PWM Hi-Z

7.11.2.2.3 Trip-Zone Input Timing

Section 7.11.2.2.3.1 shows the trip-zone input timing requirements. Figure 7-48 shows the PWM Hi-Z
characteristics.
7.11.2.2.3.1 Trip-Zone Input Timing Requirements

MIN(1) MAX UNIT

Asynchronous 1tc(EPWMCLK) cycles
tw(TZ) Pulse duration, TZx input low Synchronous 2tc(EPWMCLK) cycles
With input qualifier 1tc(EPWMCLK) + tw(IQSW) cycles

(1) For an explanation of the input qualifier parameters, see Section 7.9.6.2.1.

EPWMCLK

tw(TZ)
(A)
TZ

td(TZ-PWM)

(B)
PWM

A. TZ: TZ1, TZ2, TZ3, TRIP1–TRIP12

B. PWM refers to all the PWM pins in the device. The state of the PWM pins after TZ is taken high depends on the PWM recovery software.

Figure 7-48. PWM Hi-Z Characteristics

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7.11.2.3 External ADC Start-of-Conversion Electrical Data and Timing

Section 7.11.2.3.1 shows the external ADC start-of-conversion switching characteristics. Figure 7-49 shows the
ADCSOCAO or ADCSOCBO timing.
7.11.2.3.1 External ADC Start-of-Conversion Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER MIN MAX UNIT
tw(ADCSOCL) Pulse duration, ADCSOCxO low 32tc(SYSCLK) cycles

tw(ADCSOCL)
ADCSOCAO
or
ADCSOCBO

Figure 7-49. ADCSOCAO or ADCSOCBO Timing

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7.11.3 Enhanced Quadrature Encoder Pulse (eQEP)

The eQEP module interfaces directly with linear or rotary incremental encoders to obtain position, direction, and
speed information from rotating machines used in high-performance motion and position-control systems.
Each eQEP peripheral comprises five major functional blocks:
• Quadrature Capture Unit (QCAP)
• Position Counter/Control Unit (PCCU)
• Quadrature Decoder Unit (QDU)
• Unit Time Base for speed and frequency measurement (UTIME)
• Watchdog timer for detecting stalls (QWDOG)
The eQEP peripherals are clocked by PERx.SYSCLK. Figure 7-50 shows the eQEP block diagram.

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System Control
Registers
To CPU
EQEPxENCLK
SYSCLK

Data Bus
QCPRD
QCAPCTL QCTMR

16 16

16
Quadrature
Capture
QCTMRLAT Unit
(QCAP)
QCPRDLAT

Registers QUTMR QWDTMR

Used by QUPRD QWDPRD
Multiple Units
32 16
QEPCTL
QEPSTS UTOUT
UTIME QWDOG QDECCTL
QFLG
16
WDTOUT
EQEPxAIN
EQEPxINT QCLK EQEPxA/XCLK
PIE EQEPxBIN
QDIR
EQEPxIIN
16 Position Counter/ QI EQEPxB/XDIR
EQEPxIOUT
Control Unit QS Quadrature GPIO
(PCCU) Decoder EQEPxIOE
QPOSLAT PHE (QDU) MUX EQEPxI
EQEPxSIN
QPOSSLAT PCSOUT
EQEPxSOUT
QPOSILAT EQEPxS
EQEPxSOE
32 32 16

QPOSCNT QPOSCMP QEINT

QPOSINIT QFRC
QPOSMAX QCLR
QPOSCTL

eQEP Peripheral

Figure 7-50. eQEP Block Diagram

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7.11.3.1 eQEP Electrical Data and Timing

Section 7.11.3.1.1 lists the eQEP timing requirement and Section 7.11.3.1.2 lists the eQEP switching
characteristics.
7.11.3.1.1 eQEP Timing Requirements

MIN(1) MAX UNIT

Asynchronous(2)/Synchronous 2tc(SYSCLK) cycles
tw(QEPP) QEP input period
With input qualifier 2[1tc(SYSCLK) + tw(IQSW)] cycles
Asynchronous(2)/Synchronous 2tc(SYSCLK) cycles
tw(INDEXH) QEP Index Input High time
With input qualifier 2tc(SYSCLK) + tw(IQSW) cycles
Asynchronous(2)/Synchronous 2tc(SYSCLK) cycles
tw(INDEXL) QEP Index Input Low time
With input qualifier 2tc(SYSCLK) + tw(IQSW) cycles
Asynchronous(2)/Synchronous 2tc(SYSCLK) cycles
tw(STROBH) QEP Strobe High time
With input qualifier 2tc(SYSCLK) + tw(IQSW) cycles
Asynchronous(2)/Synchronous 2tc(SYSCLK) cycles
tw(STROBL) QEP Strobe Input Low time
With input qualifier 2tc(SYSCLK) + tw(IQSW) cycles

(1) For an explanation of the input qualifier parameters, see Section 7.9.6.2.1.
(2) See the TMS320F2807x MCUs Silicon Errata for limitations in the asynchronous mode.

7.11.3.1.2 eQEP Switching Characteristics

over recommended operating conditions (unless otherwise noted)
PARAMETER MIN MAX UNIT
td(CNTR)xin Delay time, external clock to counter increment 4tc(SYSCLK) cycles
td(PCS-OUT)QEP Delay time, QEP input edge to position compare sync output 6tc(SYSCLK) cycles

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7.11.4 High-Resolution Pulse Width Modulator (HRPWM)

The HRPWM combines multiple delay lines in a single module and a simplified calibration system by using a
dedicated calibration delay line. For each ePWM module, there are two HR outputs:
• HR Duty and Deadband control on Channel A
• HR Duty and Deadband control on Channel B
The HRPWM module offers PWM resolution (time granularity) that is significantly better than what can be
achieved using conventionally derived digital PWM methods. The key points for the HRPWM module are:
• Significantly extends the time resolution capabilities of conventionally derived digital PWM
• This capability can be used in both single edge (duty cycle and phase-shift control) as well as dual edge
control for frequency/period modulation.
• Finer time granularity control or edge positioning is controlled through extensions to the Compare A, B,
phase, period and deadband registers of the ePWM module.

Note
The minimum HRPWMCLK frequency allowed for HRPWM is 60 MHz.

7.11.4.1 HRPWM Electrical Data and Timing

Section 7.11.4.1.1 lists the high-resolution PWM timing requirements. Section 7.11.4.1.2 lists the high-resolution
PWM switching characteristics.
7.11.4.1.1 High-Resolution PWM Timing Requirements

MIN MAX UNIT

f(EPWM) Frequency, EPWMCLK(1) 100 MHz
f(HRPWM) Frequency, HRPWMCLK 60 100 MHz

(1) For SYSCLK above 100 MHz, the EPWMCLK must be half of SYSCLK.

7.11.4.1.2 High-Resolution PWM Characteristics

PARAMETER MIN TYP MAX UNIT

Micro Edge Positioning (MEP) step size(1) 150 310 ps

(1) The MEP step size will be largest at high temperature and minimum voltage on VDD. MEP step size will increase with higher
temperature and lower voltage and decrease with lower temperature and higher voltage.
Applications that use the HRPWM feature should use MEP Scale Factor Optimizer (SFO) estimation software functions. See the TI
software libraries for details of using SFO functions in end applications. SFO functions help to estimate the number of MEP steps per
SYSCLK period dynamically while the HRPWM is in operation.

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7.11.5 Sigma-Delta Filter Module (SDFM)

The SDFM is a four-channel digital filter designed specifically for current measurement and resolver position
decoding in motor control applications. Each channel can receive an independent sigma-delta (ΣΔ) modulated
bit stream. The bit streams are processed by four individually programmable digital decimation filters. The filter
set includes a fast comparator for immediate digital threshold comparisons for overcurrent and undercurrent
monitoring. Figure 7-51 shows a block diagram of the SDFMs.
SDFM features include:
• Eight external pins per SDFM module:
– Four sigma-delta data input pins per SDFM module (SDx_Dy, where x = 1 to 2 and y = 1 to 4)
– Four sigma-delta clock input pins per SDFM module (SDx_Cy, where x = 1 to 2 and y = 1 to 4)
• Four different configurable modulator clock modes:
– Modulator clock rate equals modulator data rate
– Modulator clock rate running at half the modulator data rate
– Modulator data is Manchester encoded. Modulator clock not required.
– Modulator clock rate is double that of modulator data rate
• Four independent configurable comparator units:
– Four different filter type selection (Sinc1/Sinc2/Sincfast/Sinc3) options available
– Ability to detect over-value and under-value conditions
– Comparator Over-Sampling Ratio (COSR) value for comparator programmable from 1 to 32
• Four independent configurable data filter units:
– Four different filter type selection (Sinc1/Sinc2/Sincfast/Sinc3) options available
– Data filter Over-Sampling Ratio (DOSR) value for data filter unit programmable from 1 to 256
– Ability to enable or disable individual filter module
– Ability to synchronize all four independent filters of a SDFM module using the Master Filter Enable (MFE)
bit or the PWM signals.
• Filter data can be 16-bit or 32-bit representation
• PWMs can be used to generate modulator clock for sigma-delta modulators

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SDFM- Sigma Delta Filter Module

G4 Filter Channel 1
Streams
IEL SD1INT
R
Comparator filter IEH Interrupt
SD1_D1 SD2INT
Unit
Input PIE
SD1_C1 Ctrl Data filter R
FILRES

PWM11.CMPC

SD1_D2 Filter Channel 2

SD1_C2
FILRES

Register Data bus

SD1_D3 Filter Channel 3 Map
SD1_C3
FILRES
PWM11.CMPD

SD1_D4 Filter Channel 4

SD1_C4 SD1FLT1.IEH
FILRES
SD1FLT1.IEL
SD1FLT2.IEH
SD1FLT2.IEL
SD1FLT3.IEH
GPIO SD1FLT3.IEL
MUX SD1FLT4.IEH
SDFM- Sigma Delta Filter Module SD1FLT4.IEL

Output
G4 Filter Channel 1 XBar
Streams
IEL SD2FLT1.IEH
R
Comparator filter IEH Interrupt SD2FLT1.IEL
SD2_D1 Unit
Input SD2FLT2.IEH
SD2_C1 Ctrl Data filter R
Data filter SD2FLT2.IEL
FILRES
SD2FLT3.IEH
PWM12.CMPC SD2FLT3.IEL
SD2_D2 Filter Channel 2 SD2FLT4.IEH
SD2_C2 SD2FLT4.IEL
FILRES

Register Data bus

SD2_D3 Filter Channel 3 Map
SD2_C3
PWM12.CMPD FILRES

SD2_D4 Filter Channel 4

SD2_C4
FILRES

Figure 7-51. SDFM Block Diagram

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7.11.5.1 SDFM Electrical Data and Timing (Using ASYNC)

SDFM operation with asynchronous GPIO is defined by setting GPyQSELn = 0b11. Section 7.11.5.1.1 lists the
SDFM timing requirements when using the asynchronous GPIO (ASYNC) option. Figure 7-52 through Figure
7-55 show the SDFM timing diagrams.
7.11.5.1.1 SDFM Timing Requirements When Using Asynchronous GPIO (ASYNC) Option

MIN MAX UNIT

Mode 0
tc(SDC)M0 Cycle time, SDx_Cy 40 256 * SYSCLK period ns
tw(SDCH)M0 Pulse duration, SDx_Cy high 10 tc(SDC)M0 – 10 ns
Setup time, SDx_Dy valid before SDx_Cy goes
tsu(SDDV-SDCH)M0 5 ns
high
th(SDCH-SDD)M0 Hold time, SDx_Dy wait after SDx_Cy goes high 5 ns
Mode 1
tc(SDC)M1 Cycle time, SDx_Cy 80 256 * SYSCLK period ns
tw(SDCH)M1 Pulse duration, SDx_Cy high 10 tc(SDC)M1 – 10 ns
Setup time, SDx_Dy valid before SDx_Cy goes
tsu(SDDV-SDCL)M1 5 ns
low
Setup time, SDx_Dy valid before SDx_Cy goes
tsu(SDDV-SDCH)M1 5 ns
high
th(SDCL-SDD)M1 Hold time, SDx_Dy wait after SDx_Cy goes low 5 ns
th(SDCH-SDD)M1 Hold time, SDx_Dy wait after SDx_Cy goes high 5 ns
Mode 2
tc(SDD)M2 Cycle time, SDx_Dy 8 * tc(SYSCLK) 20 * tc(SYSCLK) ns
tw(SDDH)M2 Pulse duration, SDx_Dy high 10 ns
SDx_Dy long pulse duration keepout, where the
long pulse must not fall within the MIN or MAX
values listed.
Long pulse is defined as the high or low pulse
tw(SDD_LONG_KEEPOUT)M2 (N * tc(SYSCLK)) – 0.5 (N * tc(SYSCLK)) + 0.5 ns
which is the full width of the Manchester bit-clock
period.
This requirement must be satisfied for any integer
between 8 and 20.
SDx_Dy Short pulse duration for a high or low
pulse (SDD_SHORT_H or SDD_SHORT_L).
tw(SDD_LONG) / 2 – tw(SDD_LONG) / 2 +
tw(SDD_SHORT)M2 Short pulse is defined as the high or low pulse ns
tc(SYSCLK) tc(SYSCLK)
which is half the width of the Manchester bit-clock
period.
SDx_Dy Long pulse variation (SDD_LONG_H –
tw(SDD_LONG_DUTY)M2 – tc(SYSCLK) tc(SYSCLK) ns
SDD_LONG_L)
SDx_Dy Short pulse variation (SDD_SHORT_H –
tw(SDD_SHORT_DUTY)M2 – tc(SYSCLK) tc(SYSCLK) ns
SDD_SHORT_L)
Mode 3
tc(SDC)M3 Cycle time, SDx_Cy 40 256 * SYSCLK period ns
tw(SDCH)M3 Pulse duration, SDx_Cy high 10 tc(SDC)M3 – 5 ns
Setup time, SDx_Dy valid before SDx_Cy goes
tsu(SDDV-SDCH)M3 5 ns
high
th(SDCH-SDD)M3 Hold time, SDx_Dy wait after SDx_Cy goes high 5 ns

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WARNING
The SDFM clock inputs (SDx_Cy pins) directly clock the SDFM module when there is no GPIO input
synchronization. Any glitches or ringing noise on these inputs can corrupt the SDFM module
operation. Special precautions should be taken on these signals to ensure a clean and noise-free
signal that meets SDFM timing requirements. Precautions such as series termination for ringing due
to any impedance mismatch of the clock driver and spacing of traces from other noisy signals are
recommended.

WARNING
Mode 2 (Manchester Mode) is not recommended for new applications. See the "SDFM: Manchester
Mode (Mode 2) Does Not Produce Correct Filter Results Under Several Conditions" advisory in the
TMS320F2807x MCUs Silicon Errata .

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Mode 0 tw(SDCH)M0 tc(SDC)M0

SDx_Cy

tsu(SDDV-SDCH)M0 th(SDCH-SDD)M0

SDx_Dy

Figure 7-52. SDFM Timing Diagram – Mode 0

Mode 1
tw(SDCH)M1 tc(SDC)M1

SDx_Cy

tsu(SDDV-SDCL)M1 tsu(SDDV-SDCH)M1

SDx_Dy

th(SDCL-SDD)M1 th(SDCH-SDD)M1

Figure 7-53. SDFM Timing Diagram – Mode 1

Mode 2
(Manchester-encoded-bit stream)

tc(SDD)M2

Modulator
Internal clock

tw(SDDH)M2

Modulator
Internal data 1 1 0 1 1 0 0 1 1

tw(SDD_LONG_KEEPOUT)

SDx-Dy tw(SDD_LONG_L) tw(SDD_LONG_H)

tw(SDD_SHORT_H) tw(SDD_SHORT_L)
N x tc(SYSCLK) + 0.5
N x SYSCLK
N x tc(SYSCLK) ±0.5
±

SYSCLK

Figure 7-54. SDFM Timing Diagram – Mode 2

Mode 3 (CLKx is driven externally)
tc(SDC)M3
tw(SDCH)M3

SDx_Cy

tsu(SDDV-SDCH)M3 th(SDCH-SDD)M3

SDx_Dy

Figure 7-55. SDFM Timing Diagram – Mode 3

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7.11.5.2 SDFM Electrical Data and Timing (Using 3-Sample GPIO Input Qualification)
SDFM operation with qualified GPIO (3-sample window) is defined by setting GPyQSELn = 0b01. When using
this qualified GPIO (3-sample window) mode, the timing requirement for the tw(GPI) pulse duration of 2tc(SYSCLK)
must be met. It is important for both SD-Cx and SD-Dx pairs to be configured with the same GPIO qualification
option. Section 7.11.5.2.1 lists the SDFM timing requirements when using the GPIO input qualification (3-sample
window) option. Figure 7-52 through Figure 7-55 show the SDFM timing diagrams.
7.11.5.2.1 SDFM Timing Requirements When Using GPIO Input Qualification (3-Sample Window) Option

MIN(1) MAX UNIT

Mode 0
tc(SDC)M0 Cycle time, SDx_Cy 10 * SYSCLK period 256 * SYSCLK period ns
tw(SDCHL)M0 Pulse duration, SDx_Cy high/low 4 * SYSCLK period 6 * SYSCLK period ns
tw(SDDHL)M0 Pulse duration, SDx_Dy high/low 4 * SYSCLK period ns
Setup time, SDx_Dy valid before SDx_Cy goes
tsu(SDDV-SDCH)M0 2 * SYSCLK period ns
high
th(SDCH-SDD)M0 Hold time, SDx_Dy wait after SDx_Cy goes high 2 * SYSCLK period ns
Mode 1
tc(SDC)M1 Cycle time, SDx_Cy 20 * SYSCLK period 256 * SYSCLK period ns
tw(SDCH)M1 Pulse duration, SDx_Cy high 4 * SYSCLK period 6 * SYSCLK period ns
tw(SDDHL)M1 Pulse duration, SDx_Dy high/low 4 * SYSCLK period ns
Setup time, SDx_Dy valid before SDx_Cy goes
tsu(SDDV-SDCL)M1 2 * SYSCLK period ns
low
Setup time, SDx_Dy valid before SDx_Cy goes
tsu(SDDV-SDCH)M1 2 * SYSCLK period ns
high
th(SDCL-SDD)M1 Hold time, SDx_Dy wait after SDx_Cy goes low 2 * SYSCLK period ns
th(SDCH-SDD)M1 Hold time, SDx_Dy wait after SDx_Cy goes high 2 * SYSCLK period ns
Mode 2
tc(SDD)M2 Cycle time, SDx_Dy
Option unavailable
tw(SDDH)M2 Pulse duration, SDx_Dy high
Mode 3
tc(SDC)M3 Cycle time, SDx_Cy 10 * SYSCLK period 256 * SYSCLK period ns
tw(SDCHL)M3 Pulse duration, SDx_Cy high 4 * SYSCLK period 6 * SYSCLK period ns
tw(SDDHL)M3 Pulse duration, SDx_Dy high/low 4 * SYSCLK period ns
Setup time, SDx_Dy valid before SDx_Cy goes
tsu(SDDV-SDCH)M3 2 * SYSCLK period ns
high
th(SDCH-SDD)M3 Hold time, SDx_Dy wait after SDx_Cy goes high 2 * SYSCLK period ns

(1) SDFM timing requirements apply only when the GPIO input qualification type is the 3-sample window (GPyQSELx = 1; QUALPRD = 0)
option. It is important that both the SD-Cx and SD-Dx pairs be configured with the 3-sample window option.

Note
The SDFM Qualified GPIO (3-sample) mode provides protection against SDFM module corruption due
to occasional random noise glitches on the SDx_Cy pin that may result in a false comparator trip and
filter output. For more details, refer to the "SDFM: Use Caution While Using SDFM Under Noisy
Conditions" usage note in the TMS320F2807x MCUs Silicon Errata .
The SDFM Qualified GPIO (3-sample) mode does not provide protection against persistent violations
of the above timing requirements. Timing violations will result in data corruption proportional to the
number of bits which violate the requirements.

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7.12 Communications Peripherals

Note
For the actual number of each peripheral on a specific device, see Table 5-1.

7.12.1 Controller Area Network (CAN)

The CAN module performs CAN protocol communication according to ISO 11898-1 (identical to Bosch® CAN
protocol specification 2.0 A, B). The bit rate can be programmed to values up to 1 Mbps. A CAN transceiver chip
is required for the connection to the physical layer (CAN bus).
For communication on a CAN network, individual message objects can be configured. The message objects and
identifier masks are stored in the Message RAM.
All functions concerning the handling of messages are implemented in the message handler. These functions
are: acceptance filtering; the transfer of messages between the CAN Core and the Message RAM; and the
handling of transmission requests.
The register set of the CAN may be accessed directly by the CPU through the module interface. These registers
are used to control and configure the CAN core and the message handler, and to access the message RAM.
The CAN module implements the following features:
• Complies with ISO11898-1 (Bosch® CAN protocol specification 2.0 A and B)
• Bit rates up to 1 Mbps
• Multiple clock sources
• 32 message objects (“message objects” are also referred to as “mailboxes” in this document; the two terms
are used interchangeably), each with the following properties:
– Configurable as receive or transmit
– Configurable with standard (11-bit) or extended (29-bit) identifier
– Supports programmable identifier receive mask
– Supports data and remote frames
– Holds 0 to 8 bytes of data
– Parity-checked configuration and data RAM
• Individual identifier mask for each message object
• Programmable FIFO mode for message objects
• Programmable loop-back modes for self-test operation
• Suspend mode for debug support
• Software module reset
• Automatic bus-on, after bus-off state by a programmable 32-bit timer
• Message-RAM parity-check mechanism
• Two interrupt lines

Note
For a CAN bit clock of 200 MHz, the smallest bit rate possible is 7.8125 kbps.

Note
Depending on the timing settings used, the accuracy of the on-chip zero-pin oscillator (specified in the
data manual) may not meet the requirements of the CAN protocol. In this situation, an external clock
source must be used.

Figure 7-56 shows the CAN block diagram.

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CAN_H
CAN Bus
CAN_L

External connections 3.3V CAN Transceiver

Device CANx RX pin CANx TX pin

CAN

CAN Core

Message RAM

Message Handler
Message
RAM
Interface
32 Register and Message
Message Object Access (IFx)
Objects Test Modes
(Mailboxes) Only

Module Interface

CANINT0 CANINT1
CPU Bus
(to ePIE)
Figure 7-56. CAN Block Diagram

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7.12.2 Inter-Integrated Circuit (I2C)

The I2C module has the following features:
• Compliance with the Philips Semiconductors I2C-bus specification (version 2.1):
– Support for 1-bit to 8-bit format transfers
– 7-bit and 10-bit addressing modes
– General call
– START byte mode
– Support for multiple master-transmitters and slave-receivers
– Support for multiple slave-transmitters and master-receivers
– Combined master transmit/receive and receive/transmit mode
– Data transfer rate of from 10 kbps up to 400 kbps (I2C Fast-mode rate)
• One 16-byte receive FIFO and one 16-byte transmit FIFO
• One interrupt that can be used by the CPU. This interrupt can be generated as a result of one of the following
conditions:
– Transmit-data ready
– Receive-data ready
– Register-access ready
– No-acknowledgment received
– Arbitration lost
– Stop condition detected
– Addressed as slave
• An additional interrupt that can be used by the CPU when in FIFO mode
• Module enable/disable capability
• Free data format mode

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Figure 7-57 shows how the I2C peripheral module interfaces within the device.
2
I C Module

I2CXSR I2CDXR

TX FIFO
SDA FIFO Interrupt to
CPU/PIE
RX FIFO

Peripheral Bus
I2CRSR I2CDRR

Control/Status
Registers CPU
Clock
SCL Synchronizer

Prescaler

Noise Filters
Interrupt to
I2C INT
CPU/PIE
Arbitrator

Figure 7-57. I2C Peripheral Module Interfaces

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7.12.2.1 I2C Electrical Data and Timing

Section 7.12.2.1.1 lists the I2C timing requirements. Section 7.12.2.1.2 lists the I2C switching characteristics.
Figure 7-58 shows the I2C timing diagram.
7.12.2.1.1 I2C Timing Requirements

NO. MIN MAX UNIT

Standard mode
T0 fmod I2C module frequency 7 12 MHz
Hold time, START condition, SCL fall delay after
T1 th(SDA-SCL)START 4.0 µs
SDA fall
Setup time, Repeated START, SCL rise before SDA
T2 tsu(SCL-SDA)START 4.7 µs
fall delay
T3 th(SCL-DAT) Hold time, data after SCL fall 0 µs
T4 tsu(DAT-SCL) Setup time, data before SCL rise 250 ns
T5 tr(SDA) Rise time, SDA 1000 ns
T6 tr(SCL) Rise time, SCL 1000 ns
T7 tf(SDA) Fall time, SDA 300 ns
T8 tf(SCL) Fall time, SCL 300 ns
Setup time, STOP condition, SCL rise before SDA
T9 tsu(SCL-SDA)STOP 4.0 µs
rise delay
Pulse duration of spikes that will be suppressed by
T10 tw(SP) 0 50 ns
filter
T11 Cb capacitance load on each bus line 400 pF
Fast mode
T0 fmod I2C module frequency 7 12 MHz
Hold time, START condition, SCL fall delay after
T1 th(SDA-SCL)START 0.6 µs
SDA fall
Setup time, Repeated START, SCL rise before SDA
T2 tsu(SCL-SDA)START 0.6 µs
fall delay
T3 th(SCL-DAT) Hold time, data after SCL fall 0 µs
T4 tsu(DAT-SCL) Setup time, data before SCL rise 100 ns
T5 tr(SDA) Rise time, SDA 20 300 ns
T6 tr(SCL) Rise time, SCL 20 300 ns
T7 tf(SDA) Fall time, SDA 11.4 300 ns
T8 tf(SCL) Fall time, SCL 11.4 300 ns
Setup time, STOP condition, SCL rise before SDA
T9 tsu(SCL-SDA)STOP 0.6 µs
rise delay
Pulse duration of spikes that will be suppressed by
T10 tw(SP) 0 50 ns
filter
T11 Cb capacitance load on each bus line 400 pF

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7.12.2.1.2 I2C Switching Characteristics

over recommended operating conditions (unless otherwise noted)
NO. PARAMETER TEST CONDITIONS MIN MAX UNIT
Standard mode
S1 fSCL SCL clock frequency 0 100 kHz
S2 TSCL SCL clock period 10 µs
S3 tw(SCLL) Pulse duration, SCL clock low 4.7 µs
S4 tw(SCLH) Pulse duration, SCL clock high 4.0 µs
Bus free time between STOP and START
S5 tBUF 4.7 µs
conditions
S6 tv(SCL-DAT) Valid time, data after SCL fall 3.45 µs
S7 tv(SCL-ACK) Valid time, Acknowledge after SCL fall 3.45 µs
S8 II Input current on pins 0.1 Vbus < Vi < 0.9 Vbus –10 10 µA
Fast mode
S1 fSCL SCL clock frequency 0 400 kHz
S2 TSCL SCL clock period 2.5 µs
S3 tw(SCLL) Pulse duration, SCL clock low 1.3 µs
S4 tw(SCLH) Pulse duration, SCL clock high 0.6 µs
Bus free time between STOP and START
S5 tBUF 1.3 µs
conditions
S6 tv(SCL-DAT) Valid time, data after SCL fall 0.9 µs
S7 tv(SCL-ACK) Valid time, Acknowledge after SCL fall 0.9 µs
S8 II Input current on pins 0.1 Vbus < Vi < 0.9 Vbus –10 10 µA

7.12.2.1.3

Note
To meet all of the I2C protocol timing specifications, the I2C module clock (Fmod) must be configured
from 7 MHz to 12 MHz.

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STOP START

SDA
ACK Contd...

S6 T10 S7
T5 T7 S3

SCL S4 Contd...

9th
T6 T8 clock
S2
Repeated
START STOP
S5

SDA
ACK
T2
T9
T1

SCL

9th
clock

Figure 7-58. I2C Timing Diagram

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7.12.3 Multichannel Buffered Serial Port (McBSP)

The McBSP module has the following features:
• Compatible with McBSP in TMS320C28x and TMS320F28x DSP devices
• Full-duplex communication
• Double-buffered data registers that allow a continuous data stream
• Independent framing and clocking for receive and transmit
• External shift clock generation or an internal programmable frequency shift clock
• 8-bit data transfer mode can be configured to transmit with LSB or MSB first
• Programmable polarity for both frame synchronization and data clocks
• Highly programmable internal clock and frame generation
• Direct interface to industry-standard CODECs, Analog Interface Chips (AICs), and other serially connected
A/D and D/A devices
• Supports AC97, I2S, and SPI protocols
• McBSP clock rate,
CLKSRG
CLKG =
(1 + CLKGDV )

where CLKSRG source could be LSPCLK, CLKX, or CLKR.

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Figure 7-59 shows the block diagram of the McBSP module.

TX
MXINT Interrupt
Peripheral Write Bus CPU
To CPU TX Interrupt Logic

McBSP Transmit 16 16
Interrupt Select Logic

PERx.LSPCLK DXR2 Transmit Buffer DXR1 Transmit Buffer

16 MFSXx
16
Compand Logic MCLKXx

XSR2 XSR1 MDXx

Peripheral Bus
Bridge

RSR1 MDRx
CPU DMA Bus RSR2
16
MCLKRx
16 Expand Logic
MFSRx
RBR2 Register RBR1 Register

16 16

DRR2 Receive Buffer DRR1 Receive Buffer

McBSP Receive
Interrupt Select Logic 16 16

RX
MRINT RX Interrupt Logic Interrupt
Peripheral Read Bus CPU
To CPU

Figure 7-59. McBSP Block Diagram

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7.12.3.1 McBSP Electrical Data and Timing

7.12.3.1.1 McBSP Transmit and Receive Timing
Section 7.12.3.1.1.1 shows the McBSP timing requirements. Section 7.12.3.1.1.2 shows the McBSP switching
characteristics. Figure 7-60 and Figure 7-61 show the McBSP timing diagrams.
7.12.3.1.1.1 McBSP Timing Requirements

NO.(1)
(2) MIN MAX UNIT

1 kHz
McBSP module clock (CLKG, CLKX, CLKR) range
25 MHz
40 ns
McBSP module cycle time (CLKG, CLKX, CLKR) range
1 ms
M11 tc(CKRX) Cycle time, CLKR/X CLKR/X ext 2P ns
M12 tw(CKRX) Pulse duration, CLKR/X high or CLKR/X low CLKR/X ext P–7 ns
M13 tr(CKRX) Rise time, CLKR/X CLKR/X ext 7 ns
M14 tf(CKRX) Fall time, CLKR/X CLKR/X ext 7 ns
CLKR int 18
M15 tsu(FRH-CKRL) Setup time, external FSR high before CLKR low ns
CLKR ext 2
CLKR int 0
M16 th(CKRL-FRH) Hold time, external FSR high after CLKR low ns
CLKR ext 6
CLKR int 18
M17 tsu(DRV-CKRL) Setup time, DR valid before CLKR low ns
CLKR ext 5
CLKR int 0
M18 th(CKRL-DRV) Hold time, DR valid after CLKR low ns
CLKR ext 3
CLKX int 18
M19 tsu(FXH-CKXL) Setup time, external FSX high before CLKX low ns
CLKX ext 2
CLKX int 0
M20 th(CKXL-FXH) Hold time, external FSX high after CLKX low ns
CLKX ext 6

(1) Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that
signal are also inverted.
(2) 2P = 1/CLKG in ns. CLKG is the output of sample rate generator mux. CLKG = CLKSRG / (1 + CLKGDV). CLKSRG can be LSPCLK,
CLKX, CLKR as source. CLKSRG ≤ (SYSCLK/2).

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7.12.3.1.1.2 McBSP Switching Characteristics

over recommended operating conditions (unless otherwise noted)
NO.(1)
(2) PARAMETER MIN MAX UNIT

M1 tc(CKRX) Cycle time, CLKR/X CLKR/X int 2P ns

M2 tw(CKRXH) Pulse duration, CLKR/X high CLKR/X int D–5 (3) D+5 (3) ns
M3 tw(CKRXL) Pulse duration, CLKR/X low CLKR/X int C – 5 (3) C + 5 (3) ns
CLKR int -7 7.5
M4 td(CKRH-FRV) Delay time, CLKR high to internal FSR valid ns
CLKR ext 3 27
CLKX int -5 6
M5 td(CKXH-FXV) Delay time, CLKX high to internal FSX valid ns
CLKX ext 3 27

Disable time, CLKX high to DX high impedance CLKX int –8 8

M6 tdis(CKXH-DXHZ) ns
following last data bit CLKX ext 3 15
Delay time, CLKX high to DX valid. CLKX int –3 9
This applies to all bits except the first bit
CLKX ext 5 25
transmitted.

Delay time, CLKX high to DX CLKX int –3 8

M7 td(CKXH-DXV) DXENA = 0 ns
valid CLKX ext 5 20
Only applies to first bit CLKX int P–3 P+8
transmitted when in Data
DXENA = 1
Delay 1 or 2 (XDATDLY=01b CLKX ext P+5 P + 20
or 10b) modes

Enable time, CLKX high to CLKX int -6

DXENA = 0
DX driven CLKX ext 4
M8 ten(CKXH-DX) Only applies to first bit CLKX int P-6 ns
transmitted when in Data
DXENA = 1
Delay 1 or 2 (XDATDLY=01b CLKX ext P+4
or 10b) modes

Delay time, FSX high to DX FSX int 8

DXENA = 0
valid FSX ext 17
M9 td(FXH-DXV) Only applies to first bit FSX int P+8 ns
transmitted when in Data
DXENA = 1
Delay 0 (XDATDLY=00b) FSX ext P + 17
mode.

Enable time, FSX high to DX FSX int -3

DXENA = 0
driven FSX ext 6
M10 ten(FXH-DX) Only applies to first bit FSX int P-3 ns
transmitted when in Data
DXENA = 1
Delay 0 (XDATDLY=00b) FSX ext P+6
mode

(1) Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that
signal are also inverted.
(2) 2P = 1/CLKG in ns.
(3) C = CLKRX low pulse width = P
D = CLKRX high pulse width = P

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M1, M11
M2, M12
M13
M3, M12

CLKR

M4 M4 M14
FSR (int)
M15
M16
FSR (ext)

M18
M17

DR Bit (n−1) (n−2) (n−3) (n−4)

(RDATDLY=00b)
M17
M18
DR Bit (n−1) (n−2) (n−3)
(RDATDLY=01b)
M17 M18
DR Bit (n−1) (n−2)
(RDATDLY=10b)

Figure 7-60. McBSP Receive Timing

M1, M11
M2, M12 M13
M3, M12

CLKX
M5 M5
FSX (int)
M19
M20
FSX (ext)
M9
M10 M7
DX
(XDATDLY=00b) Bit 0 Bit (n−1) (n−2) (n−3)

M7
M8
DX
(XDATDLY=01b) Bit 0 Bit (n−1) (n−2)

M6 M7
M8
DX
(XDATDLY=10b) Bit 0 Bit (n−1)

Figure 7-61. McBSP Transmit Timing

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7.12.3.1.2 McBSP as SPI Master or Slave Timing

Section 7.12.3.1.2.1 lists the McBSP as SPI master timing requirements. Section 7.12.3.1.2.2 lists the McBSP as
SPI master switching characteristics. Section 7.12.3.1.2.3 lists the McBSP as SPI slave timing requirements.
Section 7.12.3.1.2.4 lists the McBSP as SPI slave switching characteristics.
Figure 7-62 through Figure 7-65 show the McBSP as SPI master or slave timing diagrams.
7.12.3.1.2.1 McBSP as SPI Master Timing Requirements

NO. MIN MAX UNIT

CLOCK
tc(CLKG) Cycle time, CLKG(1) 2 * tc(LSPCLK) ns
P Cycle time, LSPCLK(1) tc(LSPCLK) ns
M33,
M42,
tc(CKX) Cycle time, CLKX 2P ns
M52,
M61
CLKSTP = 10b, CLKXP = 0
M30 tsu(DRV-CKXL) Setup time, DR valid before CLKX low 30 ns
M31 th(CKXL-DRV) Hold time, DR valid after CLKX low 1 ns
CLKSTP = 11b, CLKXP = 0
M39 tsu(DRV-CKXH) Setup time, DR valid before CLKX high 30 ns
M40 th(CKXH-DRV) Hold time, DR valid after CLKX high 1 ns
CLKSTP = 10b, CLKXP = 1
M49 tsu(DRV-CKXH) Setup time, DR valid before CLKX high 30 ns
M50 th(CKXH-DRV) Hold time, DR valid after CLKX high 1 ns
CLKSTP = 11b, CLKXP = 1
M58 tsu(DRV-CKXL) Setup time, DR valid before CLKX low 30 ns
M59 th(CKXL-DRV) Hold time, DR valid after CLKX low 1 ns

(1) CLKG should be configured to LSPCLK/2 by setting CLKSM = 1 and CLKGDV = 1

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7.12.3.1.2.2 McBSP as SPI Master Switching Characteristics

over operating free-air temperature range (unless otherwise noted)
NO. PARAMETER MIN TYP MAX UNIT
CLOCK
M33 tc(CLKG) Cycle time, CLKG(1) (n * tc(LSPCLK)) 40 ns
P Half CLKG cycle; 0.5 * tc(CLKG) 20 ns
n LSPCLK to CLKG divider 2 ns
CLKSTP = 10b, CLKXP = 0
M24 th(CKXL-FXL) Hold time, FSX high after CLKX low 2P – 6 ns
M25 td(FXL-CKXH) Delay time, FSX low to CLKX high P–6 ns
M26 td(CLKXH-DXV) Delay time, CLKX high to DX valid –4 6 ns
Disable time, DX high impedance following last data bit from
M28 tdis(FXH-DXHZ) P–8 ns
CLKX low
M29 td(FXL-DXV) Delay time, FSX low to DX valid P–3 P+6 ns
CLKSTP = 11b, CLKXP = 0
M34 th(CKXL-FXH) Hold time, FSX high after CLKX low P–6 ns
M35 td(FXL-CKXH) Delay time, FSX low to CLKX high P–6 ns
M36 td(CLKXL-DXV) Delay time, CLKX low to DX valid –4 6 ns
Disable time, DX high impedance following last data bit from
M37 tdis(CKXL-DXHZ) P–6 ns
CLKX low
M38 td(FXL-DXV) Delay time, FSX low to DX valid –2 1 ns
CLKSTP = 10b, CLKXP = 1
M43 th(CKXH-FXH) Hold time, FSX high after CLKX high 2P – 6 ns
M44 td(FXL-CKXL) Delay time, FSX low to CLKX low P–6 ns
M45 td(CLKXL-DXV) Delay time, CLKX low to DX valid –4 6 ns
Disable time, DX high impedance following last data bit from
M47 tdis(FXH-DXHZ) P–6 ns
CLKX low
M48 td(FXL-DXV) Delay time, FSX low to DX valid –2 1 ns
CLKSTP = 11b, CLKXP = 1
M53 th(CKXH-FXH) Hold time, FSX high after CLKX high P–6 ns
M54 td(FXL-CKXL) Delay time, FSX low to CLKX low 2P – 6 ns
M55 td(CLKXH-DXV) Delay time, CLKX high to DX valid –4 6 ns
Disable time, DX high impedance following last data bit from
M56 tdis(CKXH-DXHZ) P–8 ns
CLKX high
M57 td(FXL-DXV) Delay time, FSX low to DX valid –2 1 ns

(1) CLKG should be configured to LSPCLK/2 by setting CLKSM = 1 and CLKGDV = 1.

7.12.3.1.2.3 McBSP as SPI Slave Timing Requirements

NO. MIN MAX UNIT

CLOCK
tc(CLKG) Cycle time, CLKG(1) 2 * tc(LSPCLK) ns
P Cycle time, LSPCLK(1) tc(LSPCLK) ns
M33,
M42,
tc(CKX) Cycle time, CLKX(2) 16P ns
M52,
M61
CLKSTP = 10b, CLKXP = 0
M30 tsu(DRV-CKXL) Setup time, DR valid before CLKX low 8P – 10 ns
M31 th(CKXL-DRV) Hold time, DR valid after CLKX low 8P – 10 ns

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NO. MIN MAX UNIT

M32 tsu(BFXL-CKXH) Setup time, FSX low before CLKX high 8P+10 ns
CLKSTP = 11b, CLKXP = 0
M39 tsu(DRV-CKXH) Setup time, DR valid before CLKX high 8P – 10 ns
M40 th(CKXH-DRV) Hold time, DR valid after CLKX high 8P – 10 ns
M41 tsu(FXL-CKXH) Setup time, FSX low before CLKX high 16P+10 ns
CLKSTP = 10b, CLKXP = 1
M49 tsu(DRV-CKXH) Setup time, DR valid before CLKX high 8P – 10 ns
M50 th(CKXH-DRV) Hold time, DR valid after CLKX high 8P – 10 ns
M51 tsu(FXL-CKXL) Setup time, FSX low before CLKX low 8P+10 ns
CLKSTP = 11b, CLKXP = 1
M58 tsu(DRV-CKXL) Setup time, DR valid before CLKX low 8P – 10 ns
M59 th(CKXL-DRV) Hold time, DR valid after CLKX low 8P – 10 ns
M60 tsu(FXL-CKXL) Setup time, FSX low before CLKX low 16P+10 ns

(1) CLKG should be configured to LSPCLK/2 by setting CLKSM = 1 and CLKGDV = 1

(2) For SPI slave modes CLKX must be a minimum of 8 CLKG cycles

7.12.3.1.2.4 McBSP as SPI Slave Switching Characteristics

over operating free-air temperature range (unless otherwise noted)
NO. PARAMETER MIN TYP MAX UNIT
CLOCK
2P Cycle time, CLKG ns
CLKSTP = 10b, CLKXP = 0
M26 td(CLKXH-DXV) Delay time, CLKX high to DX valid 3P + 6 5P + 20 ns
Disable time, DX high impedance following last data bit from
M28 tdis(FXH-DXHZ) 6P + 6 ns
FSX high
M29 td(FXL-DXV) Delay time, FSX low to DX valid 4P + 6 ns
CLKSTP = 11b, CLKXP = 0
M36 td(CLKXL-DXV) Delay time, CLKX low to DX valid 3P + 6 5P + 20 ns
Disable time, DX high impedance following last data bit from
M37 tdis(CKXL-DXHZ) 7P + 6 ns
CLKX low
M38 td(FXL-DXV) Delay time, FSX low to DX valid 4P + 6 ns
CLKSTP = 10b, CLKXP = 1
M45 td(CLKXL-DXV) Delay time, CLKX low to DX valid 3P + 6 5P + 20 ns
Disable time, DX high impedance following last data bit from
M47 tdis(FXH-DXHZ) 6P + 6 ns
FSX high
M48 td(FXL-DXV) Delay time, FSX low to DX valid 4P + 6 ns
CLKSTP = 11b, CLKXP = 1
M55 td(CLKXH-DXV) Delay time, CLKX high to DX valid 3P + 6 5P + 20 ns
Disable time, DX high impedance following last data bit from
M56 tdis(CKXH-DXHZ) 7P + 6 ns
CLKX high
M57 td(FXL-DXV) Delay time, FSX low to DX valid 4P + 6 ns

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LSB M32 MSB M33

CLKX

M24 M25
FSX

M28 M29 M26

DX Bit 0 Bit(n-1) (n-2) (n-3) (n-4)

M30
M31

DR Bit 0 Bit(n-1) (n-2) (n-3) (n-4)

Figure 7-62. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0

MSB M42
LSB M41
CLKX

M34 M35
FSX

M37 M38 M36

DX Bit 0 Bit(n-1) (n-2) (n-3) (n-4)

M39
M40

DR Bit 0 Bit(n-1) (n-2) (n-3) (n-4)

Figure 7-63. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0

LSB M51 MSB M52

CLKX

M43 M44
FSX

M47 M48
M45

DX Bit 0 Bit(n-1) (n-2) (n-3) (n-4)

M49
M50
DR Bit 0 Bit(n-1) (n-2) (n-3) (n-4)

Figure 7-64. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1

M60 MSB M61

LSB
CLKX

M53 M54
FSX

M56 M57 M55

DX Bit 0 Bit(n-1) (n-2) (n-3) (n-4)

M58
M59
DR Bit 0 Bit(n-1) (n-2) (n-3) (n-4)

Figure 7-65. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1

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7.12.4 Serial Communications Interface (SCI)

The SCI is a 2-wire asynchronous serial port, commonly known as a UART. The SCI module supports digital
communications between the CPU and other asynchronous peripherals that use the standard non-return-to-zero
(NRZ) format
The SCI receiver and transmitter each have a 16-level-deep FIFO for reducing servicing overhead, and each has
its own separate enable and interrupt bits. Both can be operated independently for half-duplex communication,
or simultaneously for full-duplex communication. To specify data integrity, the SCI checks received data for break
detection, parity, overrun, and framing errors. The bit rate is programmable to different speeds through a 16-bit
baud-select register. Figure 7-66 shows the SCI block diagram.
Features of the SCI module include:
• Two external pins:
– SCITXD: SCI transmit-output pin
– SCIRXD: SCI receive-input pin

Note
NOTE: Both pins can be used as GPIO if not used for SCI.
– Baud rate programmable to 64K different rates
• Data-word format
– One start bit
– Data-word length programmable from 1 to 8 bits
– Optional even/odd/no parity bit
– 1 or 2 stop bits
• Four error-detection flags: parity, overrun, framing, and break detection
• Two wakeup multiprocessor modes: idle-line and address bit
• Half- or full-duplex operation
• Double-buffered receive and transmit functions
• Transmitter and receiver operations can be accomplished through interrupt-driven or polled algorithms with
status flags.
– Transmitter: TXRDY flag (transmitter-buffer register is ready to receive another character) and TX EMPTY
flag (transmitter-shift register is empty)
– Receiver: RXRDY flag (receiver-buffer register is ready to receive another character), BRKDT flag (break
condition occurred), and RX ERROR flag (monitoring four interrupt conditions)
• Separate enable bits for transmitter and receiver interrupts (except BRKDT)
• NRZ format
• Auto baud-detect hardware logic
• 16-level transmit and receive FIFO

Note
All registers in this module are 8-bit registers. When a register is accessed, the register data is in the
lower byte (bits 7–0), and the upper byte (bits 15–8) is read as zeros. Writing to the upper byte has no
effect.

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TXENA
SCICTL1.1

TXSHF
SCITXD
Register

Frame 8
Format and Mode

Parity
Even/Odd TXEMPTY
0 1
SCICCR.6 8 SCICTL2.6

Enable
TX FIFO_0
TXINT
SCICCR.5 To CPU
TX FIFO_1 TX FIFO Interrupts TX Interrupt
88
Logic

TX FIFO_N
TXINTENA

TXRDY SCICTL2.0
8
TXWAKE 0 1 SCICTL2.7
SCICTL1.3

SCI TX Interrupt Select Logic

WUT 8

Transmit Data
Buffer Register
SCITXBUF.7-0 Auto Baud Detect Logic
RXENA
Baud Rate
MSB/LSB SCICTL1.0
LSPCLK Registers
RXSHF
SCIRXD
Register
SCIHBAUD.15-8
RXWAKE
SCILBAUD.7-0 8
SCIRXST.1

0 1
8

SCIFFENA
SCIFFTX.14 RX FIFO_0 RXINT
8 RX FIFO_1 To CPU
RX FIFO Interrupts RX Interrupt
Logic

RX FIFO_N
RXFFOVF
8 SCIFFRX.15
0 1
RXBKINTENA
SCICTL2.1
RXRDY
SCIRXST.6

RXENA BRKDT
RXERRINTENA
SCICTL1.0
SCIRXST.5 SCICTL1.6

SCI RX Interrupt Select Logic

8

SCIRXST.5-2
Receive Data BRKDT FE OE PE
Buffer Register
RXERROR
SCIRXBUF.7-0
SCIRXST.7

Figure 7-66. SCI Block Diagram

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The major elements used in full-duplex operation include:

• A transmitter (TX) and its major registers:
– SCITXBUF register – Transmitter Data Buffer register. Contains data (loaded by the CPU) to be
transmitted
– TXSHF register – Transmitter Shift register. Accepts data from the SCITXBUF register and shifts data onto
the SCITXD pin, 1 bit at a time
• A receiver (RX) and its major registers:
– RXSHF register – Receiver Shift register. Shifts data in from the SCIRXD pin, 1 bit at a time
– SCIRXBUF register – Receiver Data Buffer register. Contains data to be read by the CPU. Data from a
remote processor is loaded into the RXSHF register and then into the SCIRXBUF and SCIRXEMU
registers
• A programmable baud generator
• Data-memory-mapped control and status registers enable the CPU to access the I2C module registers and
FIFOs.
The SCI receiver and transmitter operate independently.

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7.12.5 Serial Peripheral Interface (SPI)

The SPI is a high-speed synchronous serial input/output (I/O) port that allows a serial bit stream of programmed
length (1 to 16 bits) to be shifted into and out of the device at a programmed bit-transfer rate. The SPI is
normally used for communications between the microcontroller and external peripherals or another controller.
Typical applications include external I/O or peripheral expansion through devices such as shift registers, display
drivers, and ADCs. Multidevice communications are supported by the master/slave operation of the SPI. The
port supports 16-level receive and transmit FIFOs for reducing CPU servicing overhead.
The SPI module features include:
• SPISOMI: SPI slave-output/master-input pin
• SPISIMO: SPI slave-input/master-output pin
• SPISTE: SPI slave transmit-enable pin
• SPICLK: SPI serial-clock pin
• Two operational modes: master and slave
• Baud rate: 125 different programmable rates
• Data word length: 1 to 16 data bits
• Four clocking schemes (controlled by clock polarity and clock phase bits) include:
– Falling edge without phase delay: SPICLK active-high. SPI transmits data on the falling edge of the
SPICLK signal and receives data on the rising edge of the SPICLK signal.
– Falling edge with phase delay: SPICLK active-high. SPI transmits data one half-cycle ahead of the falling
edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal.
– Rising edge without phase delay: SPICLK inactive-low. SPI transmits data on the rising edge of the
SPICLK signal and receives data on the falling edge of the SPICLK signal.
– Rising edge with phase delay: SPICLK inactive-low. SPI transmits data one half-cycle ahead of the rising
edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal.
• Simultaneous receive-and-transmit operation (transmit function can be disabled in software)
• Transmitter and receiver operations are accomplished through either interrupt-driven or polled algorithms.
• 16-level transmit and receive FIFO
• Delayed transmit control
• 3-wire SPI mode
• SPISTE inversion for digital audio interface receive mode on devices with two SPI modules
• DMA support
• High-speed mode for up to 30-MHz full-duplex communication

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The SPI operates in master or slave mode. The master initiates data transfer by sending the SPICLK signal. For
both the slave and the master, data is shifted out of the shift registers on one edge of the SPICLK and latched
into the shift register on the opposite SPICLK clock edge. If the CLOCK PHASE bit (SPICTL.3) is high, data is
transmitted and received a half-cycle before the SPICLK transition. As a result, both controllers send and receive
data simultaneously. The application software determines whether the data is meaningful or dummy data. There
are three possible methods for data transmission:
• Master sends data; slave sends dummy data
• Master sends data; slave sends data
• Master sends dummy data; slave sends data
The master can initiate a data transfer at any time because it controls the SPICLK signal. The software,
however, determines how the master detects when the slave is ready to broadcast data.
Figure 7-67 shows the SPI CPU Interface.

PCLKCR8
Low-Speed
LSPCLK
Prescaler
SYSCLK CPU

Bit

Peripheral Bus
Clock
SYSRS

SPISIMO
GPIO SPISOMI
MUX SPICLK
SPI SPIINT
SPITXINT PIE
SPISTE

SPIRXDMA
SPITXDMA DMA

Figure 7-67. SPI CPU Interface

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7.12.5.1 SPI Electrical Data and Timing

Note
All timing parameters for SPI High-Speed Mode assume a load capacitance of 5 pF on SPICLK,
SPISIMO, and SPISOMI.

For more information about the SPI in High-Speed mode, see the Serial Peripheral Interface (SPI) chapter of the
TMS320F2807x Microcontrollers Technical Reference Manual .
To use the SPI in High-Speed mode, the application must use the high-speed enabled GPIOs (see Section
6.4.5).
7.12.5.1.1 SPI Master Mode Timings
Section 7.12.5.1.1.1 lists the SPI master mode timing requirements. Section 7.12.5.1.1.2 lists the SPI master
mode switching characteristics (clock phase = 0). Section 7.12.5.1.1.3 lists the SPI master mode switching
characteristics (clock phase = 1). Figure 7-68 shows the SPI master mode external timing where the clock phase
= 0. Figure 7-69 shows the SPI master mode external timing where the clock phase = 1.
7.12.5.1.1.1 SPI Master Mode Timing Requirements

(BRR + 1)
NO. MIN MAX UNIT
CONDITION(1)
High Speed Mode
Setup time, SPISOMI valid before
8 tsu(SOMI)M Even, Odd 1 ns
SPICLK
Hold time, SPISOMI valid after
9 th(SOMI)M Even, Odd 5 ns
SPICLK
Normal Mode
Setup time, SPISOMI valid before
8 tsu(SOMI)M Even, Odd 20 ns
SPICLK
Hold time, SPISOMI valid after
9 th(SOMI)M Even, Odd 0 ns
SPICLK

(1) The (BRR + 1) condition is Even when (SPIBRR + 1) is even or SPIBRR is 0 or 2. It is Odd when (SPIBRR + 1) is odd and SPIBRR is
greater than 3.

7.12.5.1.1.2 SPI Master Mode Switching Characteristics (Clock Phase = 0)

over recommended operating conditions (unless otherwise noted)
(BRR + 1)
NO. PARAMETER MIN MAX UNIT
CONDITION(1)
General
Even 4tc(LSPCLK) 128tc(LSPCLK)
1 tc(SPC)M Cycle time, SPICLK ns
Odd 5tc(LSPCLK) 127tc(LSPCLK)
Even 0.5tc(SPC)M – 1 0.5tc(SPC)M + 1
2 tw(SPC1)M Pulse duration, SPICLK, first pulse 0.5tc(SPC)M +0.5tc(LSPCLK) 0.5tc(SPC)M +0.5tc(LSPCLK) ns
Odd
–1 +1
Even 0.5tc(SPC)M – 1 0.5tc(SPC)M + 1
Pulse duration, SPICLK, second
3 tw(SPC2)M 0.5tc(SPC)M –0.5tc(LSPCLK) – 0.5tc(SPC)M –0.5tc(LSPCLK) ns
pulse Odd
1 +1
1.5tc(SPC)M - 3tc(SYSCLK) – 1.5tc(SPC)M - 3tc(SYSCLK) +
Even
7 5
23 td(SPC)M Delay time, SPISTE active to SPICLK ns
1.5tc(SPC)M - 4tc(SYSCLK) – 1.5tc(SPC)M - 4tc(SYSCLK) +
Odd
7 5
Even 0.5tc(SPC)M – 7 0.5tc(SPC)M + 5
Valid time, SPICLK to SPISTE
24 tv(STE)M 0.5tc(SPC)M –0.5tc(LSPCLK) – 0.5tc(SPC)M –0.5tc(LSPCLK) ns
inactive Odd
7 +5

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over recommended operating conditions (unless otherwise noted)

(BRR + 1)
NO. PARAMETER MIN MAX UNIT
CONDITION(1)
High Speed Mode
4 td(SIMO)M Delay time, SPICLK to SPISIMO valid Even, Odd 1 ns
Even 0.5tc(SPC)M – 2
Valid time, SPISIMO valid after
5 tv(SIMO)M 0.5tc(SPC)M –0.5tc(LSPCLK) – ns
SPICLK Odd
2
Normal Mode
4 td(SIMO)M Delay time, SPICLK to SPISIMO valid Even, Odd 6 ns
Even 0.5tc(SPC)M – 5
Valid time, SPISIMO valid after
5 tv(SIMO)M 0.5tc(SPC)M –0.5tc(LSPCLK) – ns
SPICLK Odd
5

(1) The (BRR + 1) condition is Even when (SPIBRR + 1) is even or SPIBRR is 0 or 2. It is Odd when (SPIBRR + 1) is odd and SPIBRR is
greater than 3.

7.12.5.1.1.3 SPI Master Mode Switching Characteristics (Clock Phase = 1)

over recommended operating conditions (unless otherwise noted)
(BRR + 1)
NO. PARAMETER MIN MAX UNIT
CONDITION(1)
General
Even 4tc(LSPCLK) 128tc(LSPCLK)
1 tc(SPC)M Cycle time, SPICLK ns
Odd 5tc(LSPCLK) 127tc(LSPCLK)
Even 0.5tc(SPC)M – 1 0.5tc(SPC)M + 1
Pulse duration, SPICLK, first
2 tw(SPCH)M 0.5tc(SPC)M – ns
pulse Odd 0.5tc(SPC)M – 0.5tc(LSPCLK) – 1
0.5tc(LSPCLK) + 1
Even 0.5tc(SPC)M – 1 0.5tc(SPC)M + 1
Pulse duration, SPICLK,
3 tw(SPC2)M 0.5tc(SPC)M + ns
second pulse Odd 0.5tc(SPC)M + 0.5tc(LSPCLK) – 1
0.5tc(LSPCLK) + 1
Delay time, SPISTE valid to 2tc(SPC)M –
23 td(SPC)M Even, Odd 2tc(SPC)M – 3tc(SYSCLK) – 7 ns
SPICLK 3tc(SYSCLK) + 5

Valid time, SPICLK to SPISTE Even –7 +5

24 tv(STE)M ns
invalid Odd –7 +5
High Speed Mode

Delay time, SPISIMO valid to Even 0.5tc(SPC)M – 1

4 td(SIMO)M ns
SPICLK Odd 0.5tc(SPC)M + 0.5tc(LSPCLK) – 1

Valid time, SPISIMO valid after Even 0.5tc(SPC)M – 2

5 tv(SIMO)M ns
SPICLK Odd 0.5tc(SPC)M – 0.5tc(LSPCLK) – 2
Normal Mode

Delay time, SPISIMO valid to Even 0.5tc(SPC)M – 5

4 td(SIMO)M ns
SPICLK Odd 0.5tc(SPC)M + 0.5tc(LSPCLK) – 5

Valid time, SPISIMO valid after Even 0.5tc(SPC)M – 5

5 tv(SIMO)M ns
SPICLK Odd 0.5tc(SPC)M – 0.5tc(LSPCLK) – 5

(1) The (BRR + 1) condition is Even when (SPIBRR + 1) is even or SPIBRR is 0 or 2. It is Odd when (SPIBRR + 1) is odd and SPIBRR is
greater than 3.

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SPICLK
(clock polarity = 0)

SPICLK
(clock polarity = 1)

4
5

SPISIMO Master Out Data Is Valid

Master In Data
SPISOMI
Must Be Valid

23 24

(A)
SPISTE

A. On the trailing end of the word, SPISTE will go inactive except between back-to-back transmit words in both FIFO and non-FIFO modes.

Figure 7-68. SPI Master Mode External Timing (Clock Phase = 0)

1
SPICLK
(clock polarity = 0)
2

SPICLK
(clock polarity = 1)
4
5

SPISIMO Master Out Data Is Valid

SPISOMI Master In Data Must

Be Valid
24
(A) 23
SPISTE

A. On the trailing end of the word, SPISTE will go inactive except between back-to-back transmit words in both FIFO and non-FIFO modes.

Figure 7-69. SPI Master Mode External Timing (Clock Phase = 1)

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7.12.5.1.2 SPI Slave Mode Timings

Section 7.12.5.1.2.1 lists the SPI slave mode timing requirements. Section 7.12.5.1.2.2 lists the SPI slave mode
switching characteristics. Figure 7-70 shows the SPI slave mode external timing where the clock phase = 0.
Figure 7-71 shows the SPI slave mode external timing where the clock phase = 1.
7.12.5.1.2.1 SPI Slave Mode Timing Requirements

NO. MIN MAX UNIT

12 tc(SPC)S Cycle time, SPICLK 4tc(SYSCLK) ns
13 tw(SPC1)S Pulse duration, SPICLK, first pulse 2tc(SYSCLK) – 1 ns
14 tw(SPC2)S Pulse duration, SPICLK, second pulse 2tc(SYSCLK) – 1 ns
19 tsu(SIMO)S Setup time, SPISIMO valid before SPICLK 1.5tc(SYSCLK) ns
20 th(SIMO)S Hold time, SPISIMO valid after SPICLK 1.5tc(SYSCLK) ns
Setup time, SPISTE valid before
2tc(SYSCLK) + 4 ns
SPICLK (Clock Phase = 0)
25 tsu(STE)S
Setup time, SPISTE valid before
2tc(SYSCLK) + 14 ns
SPICLK (Clock Phase = 1)
26 th(STE)S Hold time, SPISTE invalid after SPICLK 1.5tc(SYSCLK) ns

7.12.5.1.2.2 SPI Slave Mode Switching Characteristics

over recommended operating conditions (unless otherwise noted)
NO. PARAMETER MIN MAX UNIT
High Speed Mode
15 td(SOMI)S Delay time, SPICLK to SPISOMI valid 9 ns
16 tv(SOMI)S Valid time, SPISOMI valid after SPICLK 0 ns
Normal Mode
15 td(SOMI)S Delay time, SPICLK to SPISOMI valid 20 ns
16 tv(SOMI)S Valid time, SPISOMI valid after SPICLK 0 ns

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12

SPICLK
(clock polarity = 0)

13

14

SPICLK
(clock polarity = 1)

15
16

SPISOMI SPISOMI Data Is Valid

19

20

SPISIMO Data
SPISIMO
Must Be Valid

25 26

SPISTE

Figure 7-70. SPI Slave Mode External Timing (Clock Phase = 0)

12

SPICLK
(clock polarity = 0)

13 14

SPICLK
(clock polarity = 1)

15

SPISOMI SPISOMI Data Is Valid Data Valid Data Valid

19 16

20

SPISIMO SPISIMO Data

Must Be Valid

25 26

SPISTE

Figure 7-71. SPI Slave Mode External Timing (Clock Phase = 1)

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7.12.6 Universal Serial Bus (USB) Controller

The USB controller operates as a full-speed or low-speed function controller during point-to-point
communications with USB host or device functions.
The USB module has the following features:
• USB 2.0 full-speed and low-speed operation
• Integrated PHY
• Three transfer types: control, interrupt, and bulk
• 32 endpoints
– One dedicated control IN endpoint and one dedicated control OUT endpoint
– 15 configurable IN endpoints and 15 configurable OUT endpoints
• 4KB of dedicated endpoint memory
Figure 7-72 shows the USB block diagram.

Endpoint Control

Transmit
EP0 –31
Control
Receive
CPU Interface
Interrupt Interrupts
Host
Combine Control
Transaction
Endpoints
Scheduler
EP Reg.
Decoder

Common CPU Bus

UTM Packet FIFO RAM
Synchronization Encode/Decode Controller Regs
Rx Rx
Data Sync Packet Encode
Buff Buff Cycle
Control
HNP/SRP Packet Decode Tx Tx
Buff Buff
USB FS/LS
PHY FIFO
Timers CRC Gen/Check Cycle Control
Decoder
USB DataLines
D+ andD-

Figure 7-72. USB Block Diagram

Note
The accuracy of the on-chip zero-pin oscillator (Section 7.9.3.5.1, Internal Oscillator Electrical
Characteristics) will not meet the accuracy requirements of the USB protocol. An external clock source
must be used for applications using USB. For applications using the USB boot mode, see Section 8.9
(Boot ROM and Peripheral Booting) for clock frequency requirements.

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7.12.6.1 USB Electrical Data and Timing

Section 7.12.6.1.1 shows the USB input ports DP and DM timing requirements. Section 7.12.6.1.2 shows the
USB output ports DP and DM switching characteristics.
7.12.6.1.1 USB Input Ports DP and DM Timing Requirements

MIN MAX UNIT

V(CM) Differential input common mode range 0.8 2.5 V
Z(IN) Input impedance 300 kΩ
VCRS Crossover voltage 1.3 2.0 V
VIL Static SE input logic-low level 0.8 V
VIH Static SE input logic-high level 2.0 V
VDI Differential input voltage 0.2 V

7.12.6.1.2 USB Output Ports DP and DM Switching Characteristics

over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN MAX UNIT
VOH D+, D– single-ended USB 2.0 load conditions 2.8 3.6 V
VOL D+, D– single-ended USB 2.0 load conditions 0 0.3 V
Z(DRV) D+, D– impedance 28 44 Ω
Full speed, differential, CL = 50 pF, 10%/90%,
tr Rise time 4 20 ns
Rpu on D+
Full speed, differential, CL = 50 pF, 10%/90%,
tf Fall time 4 20 ns
Rpu on D+

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8 Detailed Description
8.1 Overview
The TMS320F2807x microcontroller family is suited for advanced closed-loop control applications such as
industrial motor drives; solar inverters and digital power; electrical vehicles and transportation; and sensing and
signal processing. Complete development packages for digital power and industrial drives are available as part
of the powerSUITE and DesignDRIVE initiatives.
The F2807x is a 32-bit floating-point microcontroller based on TI’s industry-leading C28x core. This core is
boosted by the trigonometric hardware accelerator which improves performance of trigonometric-based
algorithms with CPU instructions such as sine, cosine, and arctangent functions, which are common in torque-
loop and position calculations.
The F2807x microcontroller family features a CLA real-time control coprocessor. The CLA is an independent 32-
bit floating-point processor that runs at the same speed as the main CPU. The CLA responds to peripheral
triggers and executes code concurrently with the main C28x CPU. This parallel processing capability can
effectively double the computational performance of a real-time control system. By using the CLA to service
time-critical functions, the main C28x CPU is free to perform other tasks, such as communications and
diagnostics.
The F2807x device supports up to 512KB (256KW) of ECC-protected onboard flash memory and up to 100KB
(50KW) of SRAM with parity. Two independent security zones are also available for 128-bit code protection of
the main C28x.
The analog subsystem boasts up to three 12-bit ADCs, which enable simultaneous management of three
independent power phases, and up to eight windowed comparator subsystems (CMPSSs), allowing very fast,
direct trip of the PWMs in overvoltage or overcurrent conditions. In addition, the device has three 12-bit DACs,
and precision control peripherals such as enhanced pulse width modulators (ePWMs) with fault protection,
eQEP peripherals, and eCAP units.
Connectivity peripherals such as dual Controller Area Network (CAN) modules (ISO 11898-1/CAN 2.0B-
compliant) and a USB 2.0 port with MAC and full-speed PHY let users add universal serial bus (USB)
connectivity to their application.
8.2 Functional Block Diagram
Figure 8-1 shows the CPU system and associated peripherals.

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MEMCPU1 Low-Power
Mode Control GPIO MUX
CPU1.CLA1 to CPU1 C28 CPU-1 User
CPU1.CLA1 128x16 MSG RAM
FPU Configurable
CPU1 to CPU1.CLA1 Dual PSWD DCSM
128x16 MSG RAM TMU Code OTP
Security 1K x 16 Watchdog INTOSC1
Module
+
Emulation
FLASH
CPU1 Local Shared 256K x 16
Code
Secure Memories 6x 2Kx16 Security Secure
LS0-LS5 RAMs Logic
shown in Red (ECSL) PUMP
CPU1.D0 RAM 2Kx16 OTP/Flash Main PLL INTOSC2
Wrapper
CPU1.D1 RAM 2Kx16 WD Timer
NMI-WDT External Crystal or
Oscillator
CPU Timer 0
CPU1.M0 RAM 1Kx16
CPU Timer 1
12-bit ADC CPU Timer 2 Aux PLL
A5:0 CPU1.M1 RAM 1Kx16
A x3 AUXCLKIN

B ePIE Global Shared

B3:0 (up to 192 8x 4Kx16
D ADC TRST
Analog Result
Secure-ROM 32Kx16 interrupts) GS0-GS7 RAMs
Secure TCK
D4:0 MUX Config Regs
Boot-ROM 32Kx16
CPU1.CLA1 Bus

Nonsecure JTAG TDI

ADCIN14 TMS
ADCIN15
Data Bus TDO
Bridge CPU1.CLA1 Data ROM CPU1.DMA
(4Kx16)

Comparator
DAC CPU1 Buses
Subsystem
(CMPSS) x3

Data Bus Data Bus Data Bus Data Bus

Peripheral Frame 1 Data Bus Bridge Bridge Bridge Peripheral Frame 2 Bridge Bridge

ePWM-1/../12 SCI- USB CAN- SPI-

eCAP- I2C-A/B
1/../6
eQEP-1/2/3 SDFM-1/2 A/B/C/D Ctrl / A/B A/B/C McBSP-A/B EMIF1 GPIO
(16L FIFO)
HRPWM-1/../8 (16L FIFO) PHY (32-MBOX) (16L FIFO)
EXTSYNCOUT
EPWMxB
EPWMxA

SCITXDx

CANTXx

SPISIMOx
SPISOMIx

EM1CTLx
SPICLKx

MCLKRx
SPISTEx

MCLKXx
EQEPxS
EXTSYNCIN

USBDM
SDx_Dy

SDx_Cy
EQEPxI

MDXx
USBDP

MFSRx
SCIRXDx

MFSXx

EM1Dx
EM1Ax

GPIOn
CANRXx
EQEPxB
ECAPx

EQEPxA
TZ1-TZ6

MDRx
SDAx

SCLx

GPIO MUX, Input X-BAR, Output X-BAR

Figure 8-1. Functional Block Diagram

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8.3 Memory
8.3.1 C28x Memory Map
The C28x memory map is described in Table 8-1. Memories accessible by the CLA or DMA (direct memory
access) are noted as well.
Table 8-1. C28x Memory Map
MEMORY SIZE START ADDRESS END ADDRESS CLA ACCESS DMA ACCESS
M0 RAM 1K × 16 0x0000 0000 0x0000 03FF
M1 RAM 1K × 16 0x0000 0400 0x0000 07FF
PieVectTable 512 × 16 0x0000 0D00 0x0000 0EFF
CLA to CPU MSGRAM 128 × 16 0x0000 1480 0x0000 14FF Yes
CPU to CLA MSGRAM 128 × 16 0x0000 1500 0x0000 157F Yes
LS0 RAM 2K × 16 0x0000 8000 0x0000 87FF Yes
LS1 RAM 2K × 16 0x0000 8800 0x0000 8FFF Yes
LS2 RAM 2K × 16 0x0000 9000 0x0000 97FF Yes
LS3 RAM 2K × 16 0x0000 9800 0x0000 9FFF Yes
LS4 RAM 2K × 16 0x0000 A000 0x0000 A7FF Yes
LS5 RAM 2K × 16 0x0000 A800 0x0000 AFFF Yes
D0 RAM 2K × 16 0x0000 B000 0x0000 B7FF
D1 RAM 2K × 16 0x0000 B800 0x0000 BFFF
GS0 RAM 4K × 16 0x0000 C000 0x0000 CFFF Yes
GS1 RAM 4K × 16 0x0000 D000 0x0000 DFFF Yes
GS2 RAM 4K × 16 0x0000 E000 0x0000 EFFF Yes
GS3 RAM 4K × 16 0x0000 F000 0x0000 FFFF Yes
GS4 RAM 4K × 16 0x0001 0000 0x0001 0FFF Yes
GS5 RAM 4K × 16 0x0001 1000 0x0001 1FFF Yes
GS6 RAM 4K × 16 0x0001 2000 0x0001 2FFF Yes
GS7 RAM 4K × 16 0x0001 3000 0x0001 3FFF Yes
CAN A Message RAM 2K × 16 0x0004 9000 0x0004 97FF
CAN B Message RAM 2K × 16 0x0004 B000 0x0004 B7FF
Flash Bank 0 256K × 16 0x0008 0000 0x000B FFFF
Secure ROM 32K × 16 0x003F 0000 0x003F 7FFF
Boot ROM 32K × 16 0x003F 8000 0x003F FFBF
Vectors 64 × 16 0x003F FFC0 0x003F FFFF

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8.3.2 Flash Memory Map

The F28076 and F28075 devices have one flash bank of 512KB (256KW). See Section 7.9.4 for details on flash
wait-states. Table 1-1 shows the addresses of flash sectors on F28076 and F28075.
Table 8-2. Addresses of Flash Sectors on F28076 and F28075
SECTOR SIZE START ADDRESS END ADDRESS
OTP Sectors
TI OTP Bank 0 1K x 16 0x0007 0000 0x0007 03FF
User configurable DCSM OTP
1K x 16 0x0007 8000 0x0007 83FF
Bank 0
Sectors
Sector 0 8K x 16 0x0008 0000 0x0008 1FFF
Sector 1 8K x 16 0x0008 2000 0x0008 3FFF
Sector 2 8K x 16 0x0008 4000 0x0008 5FFF
Sector 3 8K x 16 0x0008 6000 0x0008 7FFF
Sector 4 32K x 16 0x0008 8000 0x0008 FFFF
Sector 5 32K x 16 0x0009 0000 0x0009 7FFF
Sector 6 32K x 16 0x0009 8000 0x0009 FFFF
Sector 7 32K x 16 0x000A 0000 0x000A 7FFF
Sector 8 32K x 16 0x000A 8000 0x000A FFFF
Sector 9 32K x 16 0x000B 0000 0x000B 7FFF
Sector 10 8K x 16 0x000B 8000 0x000B 9FFF
Sector 11 8K x 16 0x000B A000 0x000B BFFF
Sector 12 8K x 16 0x000B C000 0x000B DFFF
Sector 13 8K x 16 0x000B E000 0x000B FFFF
Flash ECC Locations
TI OTP ECC Bank 0 128 x 16 0x0107 0000 0x0107 007F
User-configurable DCSM OTP
128 x 16 0x0107 1000 0x0107 107F
ECC Bank 0
Flash ECC (Sector 0) 1K x 16 0x0108 0000 0x0108 03FF
Flash ECC (Sector 1) 1K x 16 0x0108 0400 0x0108 07FF
Flash ECC (Sector 2) 1K x 16 0x0108 0800 0x0108 0BFF
Flash ECC (Sector 3) 1K x 16 0x0108 0C00 0x0108 0FFF
Flash ECC (Sector 4) 4K x 16 0x0108 1000 0x0108 1FFF
Flash ECC (Sector 5) 4K x 16 0x0108 2000 0x0108 2FFF
Flash ECC (Sector 6) 4K x 16 0x0108 3000 0x0108 3FFF
Flash ECC (Sector 7) 4K x 16 0x0108 4000 0x0108 4FFF
Flash ECC (Sector 8) 4K x 16 0x0108 5000 0x0108 5FFF
Flash ECC (Sector 9) 4K x 16 0x0108 6000 0x0108 6FFF
Flash ECC (Sector 10) 1K x 16 0x0108 7000 0x0108 73FF
Flash ECC (Sector 11) 1K x 16 0x0108 7400 0x0108 77FF
Flash ECC (Sector 12) 1K x 16 0x0108 7800 0x0108 7BFF
Flash ECC (Sector 13) 1K x 16 0x0108 7C00 0x0108 7FFF

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8.3.3 EMIF Chip Select Memory Map

The EMIF memory map is shown in Table 8-3.
Table 8-3. EMIF Chip Select Memory Map
EMIF CHIP SELECT SIZE(1) START ADDRESS END ADDRESS CLA ACCESS DMA ACCESS
EMIF1_CS0n - Data 256M × 16 0x8000 0000 0x8FFF FFFF Yes
EMIF1_CS2n - Program + Data(2) 2M × 16 0x0010 0000 0x002F FFFF Yes
EMIF1_CS3n - Program + Data 512K × 16 0x0030 0000 0x0037 FFFF Yes
EMIF1_CS4n - Program + Data 393K × 16 0x0038 0000 0x003D FFFF Yes

(1) Available memory size listed in this table is the maximum possible size assuming 32-bit memory. This may not apply to other memory
sizes because of pin mux setting. See Section 6.4.1 to find the available address lines for your use case.
(2) The 2M × 16 size is for a 32-bit interface with the assumption that 16-bit accesses are not performed; hence, byte enables are not
used (tied to active value on board). If byte enables are used, then the maximum size is smaller because byte enables are muxed with
address pins (see Section 6.4.1) . If 16-bit memory is used, then the maximum size is 1M × 16.

8.3.4 Peripheral Registers Memory Map

The peripheral registers memory map can be found in Table 8-4. Registers in the peripheral frames share a
secondary master (CLA or DMA) selection with all other registers within the same peripheral frame. See the
TMS320F2807x Microcontrollers Technical Reference Manual for details on the CPU subsystem and secondary
master selection.
Table 8-4. Peripheral Registers Memory Map
START END (1) CLA DMA
REGISTERS STRUCTURE NAME PROTECTED
ADDRESS ADDRESS ACCESS ACCESS
AdcaResultRegs ADC_RESULT_REGS 0x0000 0B00 0x0000 0B1F Yes Yes
AdcbResultRegs ADC_RESULT_REGS 0x0000 0B20 0x0000 0B3F Yes Yes
AdcdResultRegs ADC_RESULT_REGS 0x0000 0B60 0x0000 0B7F Yes Yes
CpuTimer0Regs CPUTIMER_REGS 0x0000 0C00 0x0000 0C07
CpuTimer1Regs CPUTIMER_REGS 0x0000 0C08 0x0000 0C0F
CpuTimer2Regs CPUTIMER_REGS 0x0000 0C10 0x0000 0C17
(2)
PieCtrlRegs PIE_CTRL_REGS 0x0000 0CE0 0x0000 0CFF
Yes – CLA
(2) only, no
Cla1SoftIntRegs CLA_SOFTINT_REGS 0x0000 0CE0 0x0000 0CFF
CPU
access
DmaRegs DMA_REGS 0x0000 1000 0x0000 11FF
Cla1Regs CLA_REGS 0x0000 1400 0x0000 147F
Peripheral Frame 1
EPwm1Regs EPWM_REGS 0x0000 4000 0x0000 40FF Yes Yes Yes
EPwm2Regs EPWM_REGS 0x0000 4100 0x0000 41FF Yes Yes Yes
EPwm3Regs EPWM_REGS 0x0000 4200 0x0000 42FF Yes Yes Yes
EPwm4Regs EPWM_REGS 0x0000 4300 0x0000 43FF Yes Yes Yes
EPwm5Regs EPWM_REGS 0x0000 4400 0x0000 44FF Yes Yes Yes
EPwm6Regs EPWM_REGS 0x0000 4500 0x0000 45FF Yes Yes Yes
EPwm7Regs EPWM_REGS 0x0000 4600 0x0000 46FF Yes Yes Yes
EPwm8Regs EPWM_REGS 0x0000 4700 0x0000 47FF Yes Yes Yes
EPwm9Regs EPWM_REGS 0x0000 4800 0x0000 48FF Yes Yes Yes
EPwm10Regs EPWM_REGS 0x0000 4900 0x0000 49FF Yes Yes Yes
EPwm11Regs EPWM_REGS 0x0000 4A00 0x0000 4AFF Yes Yes Yes
EPwm12Regs EPWM_REGS 0x0000 4B00 0x0000 4BFF Yes Yes Yes
ECap1Regs ECAP_REGS 0x0000 5000 0x0000 501F Yes Yes Yes
ECap2Regs ECAP_REGS 0x0000 5020 0x0000 503F Yes Yes Yes
ECap3Regs ECAP_REGS 0x0000 5040 0x0000 505F Yes Yes Yes
ECap4Regs ECAP_REGS 0x0000 5060 0x0000 507F Yes Yes Yes

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Table 8-4. Peripheral Registers Memory Map (continued)

START END (1) CLA DMA
REGISTERS STRUCTURE NAME PROTECTED
ADDRESS ADDRESS ACCESS ACCESS
ECap5Regs ECAP_REGS 0x0000 5080 0x0000 509F Yes Yes Yes
ECap6Regs ECAP_REGS 0x0000 50A0 0x0000 50BF Yes Yes Yes
EQep1Regs EQEP_REGS 0x0000 5100 0x0000 513F Yes Yes Yes
EQep2Regs EQEP_REGS 0x0000 5140 0x0000 517F Yes Yes Yes
EQep3Regs EQEP_REGS 0x0000 5180 0x0000 51BF Yes Yes Yes
DacaRegs DAC_REGS 0x0000 5C00 0x0000 5C0F Yes Yes Yes
DacbRegs DAC_REGS 0x0000 5C10 0x0000 5C1F Yes Yes Yes
DaccRegs DAC_REGS 0x0000 5C20 0x0000 5C2F Yes Yes Yes
Cmpss1Regs CMPSS_REGS 0x0000 5C80 0x0000 5C9F Yes Yes Yes
Cmpss2Regs CMPSS_REGS 0x0000 5CA0 0x0000 5CBF Yes Yes Yes
Cmpss3Regs CMPSS_REGS 0x0000 5CC0 0x0000 5CDF Yes Yes Yes
Cmpss4Regs CMPSS_REGS 0x0000 5CE0 0x0000 5CFF Yes Yes Yes
Cmpss5Regs CMPSS_REGS 0x0000 5D00 0x0000 5D1F Yes Yes Yes
Cmpss6Regs CMPSS_REGS 0x0000 5D20 0x0000 5D3F Yes Yes Yes
Cmpss7Regs CMPSS_REGS 0x0000 5D40 0x0000 5D5F Yes Yes Yes
Cmpss8Regs CMPSS_REGS 0x0000 5D60 0x0000 5D7F Yes Yes Yes
Sdfm1Regs SDFM_REGS 0x0000 5E00 0x0000 5E7F Yes Yes Yes
Sdfm2Regs SDFM_REGS 0x0000 5E80 0x0000 5EFF Yes Yes Yes
Peripheral Frame 2
McbspaRegs MCBSP_REGS 0x0000 6000 0x0000 603F Yes Yes Yes
McbspbRegs MCBSP_REGS 0x0000 6040 0x0000 607F Yes Yes Yes
SpiaRegs SPI_REGS 0x0000 6100 0x0000 610F Yes Yes Yes
SpibRegs SPI_REGS 0x0000 6110 0x0000 611F Yes Yes Yes
SpicRegs SPI_REGS 0x0000 6120 0x0000 612F Yes Yes Yes

WdRegs WD_REGS 0x0000 7000 0x0000 703F Yes

NmiIntruptRegs NMI_INTRUPT_REGS 0x0000 7060 0x0000 706F Yes
XintRegs XINT_REGS 0x0000 7070 0x0000 707F Yes
SciaRegs SCI_REGS 0x0000 7200 0x0000 720F Yes
ScibRegs SCI_REGS 0x0000 7210 0x0000 721F Yes
ScicRegs SCI_REGS 0x0000 7220 0x0000 722F Yes
ScidRegs SCI_REGS 0x0000 7230 0x0000 723F Yes
I2caRegs I2C_REGS 0x0000 7300 0x0000 733F Yes
I2cbRegs I2C_REGS 0x0000 7340 0x0000 737F Yes
AdcaRegs ADC_REGS 0x0000 7400 0x0000 747F Yes Yes
AdcbRegs ADC_REGS 0x0000 7480 0x0000 74FF Yes Yes
AdcdRegs ADC_REGS 0x0000 7580 0x0000 75FF Yes Yes
InputXbarRegs INPUT_XBAR_REGS 0x0000 7900 0x0000 791F Yes
XbarRegs XBAR_REGS 0x0000 7920 0x0000 793F Yes
TrigRegs TRIG_REGS 0x0000 7940 0x0000 794F Yes
DmaClaSrcSelRegs DMA_CLA_SRC_SEL_REGS 0x0000 7980 0x0000 798F Yes
EPwmXbarRegs EPWM_XBAR_REGS 0x0000 7A00 0x0000 7A3F Yes
OutputXbarRegs OUTPUT_XBAR_REGS 0x0000 7A80 0x0000 7ABF Yes
GpioCtrlRegs GPIO_CTRL_REGS 0x0000 7C00 0x0000 7D7F Yes
GpioDataRegs GPIO_DATA_REGS 0x0000 7F00 0x0000 7F2F Yes Yes
UsbaRegs USB_REGS 0x0004 0000 0x0004 0FFF Yes
Emif1Regs EMIF_REGS 0x0004 7000 0x0004 77FF Yes
CanaRegs CAN_REGS 0x0004 8000 0x0004 87FF Yes
CanbRegs CAN_REGS 0x0004 A000 0x0004 A7FF Yes

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Table 8-4. Peripheral Registers Memory Map (continued)

START END (1) CLA DMA
REGISTERS STRUCTURE NAME PROTECTED
ADDRESS ADDRESS ACCESS ACCESS
FlashPumpSemaphoreRegs FLASH_PUMP_SEMAPHORE_REGS 0x0005 0024 0x0005 0025 Yes
DevCfgRegs DEV_CFG_REGS 0x0005 D000 0x0005 D17F Yes
AnalogSubsysRegs ANALOG_SUBSYS_REGS 0x0005 D180 0x0005 D1FF Yes
ClkCfgRegs CLK_CFG_REGS 0x0005 D200 0x0005 D2FF Yes
CpuSysRegs CPU_SYS_REGS 0x0005 D300 0x0005 D3FF Yes
RomPrefetchRegs ROM_PREFETCH_REGS 0x0005 E608 0x0005 E60B Yes
DcsmZ1Regs DCSM_Z1_REGS 0x0005 F000 0x0005 F02F Yes
DcsmZ2Regs DCSM_Z2_REGS 0x0005 F040 0x0005 F05F Yes
DcsmCommonRegs DCSM_COMMON_REGS 0x0005 F070 0x0005 F07F Yes
MemCfgRegs MEM_CFG_REGS 0x0005 F400 0x0005 F47F Yes
Emif1ConfigRegs EMIF1_CONFIG_REGS 0x0005 F480 0x0005 F49F Yes
AccessProtectionRegs ACCESS_PROTECTION_REGS 0x0005 F4C0 0x0005 F4FF Yes
MemoryErrorRegs MEMORY_ERROR_REGS 0x0005 F500 0x0005 F53F Yes
RomWaitStateRegs ROM_WAIT_STATE_REGS 0x0005 F540 0x0005 F541 Yes
Flash0CtrlRegs FLASH_CTRL_REGS 0x0005 F800 0x0005 FAFF Yes
Flash0EccRegs FLASH_ECC_REGS 0x0005 FB00 0x0005 FB3F Yes

(1) The CPU (not applicable for CLA or DMA) contains a write followed by read protection mode to ensure that any read operation that
follows a write operation within a protected address range is executed as written by delaying the read operation until the write is
initiated.
(2) The address overlap of PieCtrlRegs and Cla1SoftIntRegs is correct. Each CPU, C28x and CLA, only has access to one of the register
sets.

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8.3.5 Memory Types

Table 8-5 provides more information about each memory type.
Table 8-5. Memory Types
HIBERNATE ACCESS
MEMORY TYPE ECC-CAPABLE PARITY SECURITY
RETENTION PROTECTION
M0, M1 Yes – – Yes –
D0, D1 Yes – Yes – Yes
LSx – Yes Yes – Yes
GSx – Yes – – Yes
CPU/CLA MSGRAM – Yes Yes – Yes
Boot ROM – – – N/A –
Secure ROM – – Yes N/A –
Flash Yes – Yes N/A N/A
User-configurable DCSM OTP Yes – Yes N/A N/A

8.3.5.1 Dedicated RAM (Mx and Dx RAM)

The CPU subsystem has four dedicated ECC-capable RAM blocks: M0, M1, D0, and D1. M0/M1 memories are
small nonsecure blocks that are tightly coupled with the CPU (that is, only the CPU has access to them). D0/D1
memories are secure blocks and also have the access-protection feature (CPU write/CPU fetch protection).
8.3.5.2 Local Shared RAM (LSx RAM)
RAM blocks which are dedicated to each subsystem and are accessible to its CPU and CLA only, are called
local shared RAMs (LSx RAMs).
All LSx RAM blocks have parity. These memories are secure and have the access protection (CPU write/CPU
fetch) feature.
By default, these memories are dedicated to the CPU only, and the user could choose to share these memories
with the CLA by configuring the MSEL_LSx bit field in the LSxMSEL registers appropriately.
Table 8-6 shows the master access for the LSx RAM.
Table 8-6. Master Access for LSx RAM
(With Assumption That all Other Access Protections are Disabled)
MSEL_LSx CLAPGM_LSx CPU ALLOWED ACCESS CLA ALLOWED ACCESS COMMENT
LSx memory is configured
00 X All –
as CPU dedicated RAM.
Data Read LSx memory is shared
01 0 All
Data Write between CPU and CLA1.
Emulation Read LSx memory is CLA1
01 1 Fetch Only
Emulation Write program memory.

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8.3.5.3 Global Shared RAM (GSx RAM)

RAM blocks which are accessible from both the CPU and DMA are called global shared RAMs (GSx RAMs).
Both the CPU and DMA have full read and write access to these memories.
All GSx RAM blocks have parity.
The GSx RAMs have access protection (CPU write/CPU fetch/DMA write).
8.3.5.4 CLA Message RAM (CLA MSGRAM)
These RAM blocks can be used to share data between the CPU and CLA. The CLA has read and write access
to the "CLA to CPU MSGRAM." The CPU has read and write access to the "CPU to CLA MSGRAM." The CPU
and CLA both have read access to both MSGRAMs.
This RAM has parity.

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8.4 Identification
Table 8-7 shows the Device Identification Registers.
Table 8-7. Device Identification Registers
NAME ADDRESS SIZE (x16) DESCRIPTION
Device part identification number(1)
PARTIDH 0x0005 D00A 2 TMS320F28076 0x**FC 0500
TMS320F28075 0x**FF 0500
Silicon revision number
REVID 0x0005 D00C 2 Revision B 0x0000 0002
Revision C 0x0000 0003
Unique identification number. This number is different on each
individual device with the same PARTIDH. This can be used as
UID_UNIQUE 0x0007 03CC 2
a serial number in the application. This number is present only
on TMS Revision C devices.
JTAG ID N/A N/A JTAG Device ID 0x0B99 C02F

(1) PARTIDH may have one of two values for each part number, with the eight most significant bits identified with '**' above being 0x00 or
0x02.

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8.5 Bus Architecture – Peripheral Connectivity

Table 8-8 shows a broad view of the peripheral and configuration register accessibility from each bus master.
Peripherals within peripheral frames 1 or 2 will all be mapped to the respective secondary master as a group (if
SPI is assigned to CPU1.DMA, then McBSP is also assigned to CPU1.DMA).
Table 8-8. Bus Master Peripheral Access
PERIPHERALS
CPU1.DMA CPU1.CLA1 CPU1
(BY BUS ACCESS TYPE)
Peripheral Frame 1:
• ePWM/HRPWM
• SDFM
• eCAP(1) Y Y Y
• eQEP(1)
• CMPSS(1)
• DAC(1)

Peripheral Frame 2:
• SPI Y Y Y
• McBSP

SCI Y
I2C Y
CAN Y
ADC Configuration Y Y
EMIF1 Y Y
USB Y
Device Capability, Peripheral Reset, Peripheral CPU Select Y
GPIO Pin Mapping and Configuration Y
Analog System Control Y
Reset Configuration Y
Clock and PLL Configuration Y
System Configuration
Y
(WD, NMIWD, LPM, Peripheral Clock Gating)
Flash Configuration Y
CPU Timers Y
DMA and CLA Trigger Source Select Y
GPIO Data(2) Y Y
ADC Results Y Y Y

(1) These modules are on a Peripheral Frame with DMA access; however, they cannot trigger a DMA transfer.
(2) The GPIO Data Registers are unique for each CPU1 and CPU1.CLAx. When the GPIO Pin Mapping Register is configured to assign a
GPIO to a particular master, the respective GPIO Data Register will control the GPIO. See the General-Purpose Input/Output (GPIO)
chapter of the TMS320F2807x Microcontrollers Technical Reference Manual for more details.

8.6 C28x Processor

The CPU is a 32-bit fixed-point processor. This device draws from the best features of digital signal processing;
reduced instruction set computing (RISC); and microcontroller architectures, firmware, and tool sets.
The CPU features include a modified Harvard architecture and circular addressing. The RISC features are
single-cycle instruction execution, register-to-register operations, and modified Harvard architecture. The
microcontroller features include ease of use through an intuitive instruction set, byte packing and unpacking, and
bit manipulation. The modified Harvard architecture of the CPU enables instruction and data fetches to be
performed in parallel. The CPU can read instructions and data while it writes data simultaneously to maintain the
single-cycle instruction operation across the pipeline. The CPU does this over six separate address/data buses.

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For more information on CPU architecture and instruction set, see the TMS320C28x CPU and Instruction Set
Reference Guide.
8.6.1 Floating-Point Unit
The C28x plus floating-point (C28x+FPU) processor extends the capabilities of the C28x fixed-point CPU by
adding registers and instructions to support IEEE single-precision floating-point operations.
Devices with the C28x+FPU include the standard C28x register set plus an additional set of floating-point unit
registers. The additional floating-point unit registers are the following:
• Eight floating-point result registers, RnH (where n = 0–7)
• Floating-point Status Register (STF)
• Repeat Block Register (RB)
All of the floating-point registers, except the repeat block register, are shadowed. This shadowing can be used in
high-priority interrupts for fast context save and restore of the floating-point registers.
For more information, see the TMS320C28x Extended Instruction Sets Technical Reference Manual.
8.6.2 Trigonometric Math Unit
The TMU extends the capabilities of a C28x+FPU by adding instructions and leveraging existing FPU
instructions to speed up the execution of common trigonometric and arithmetic operations listed in Table 8-9.
Table 8-9. TMU Supported Instructions
INSTRUCTIONS C EQUIVALENT OPERATION PIPELINE CYCLES
MPY2PIF32 RaH,RbH a = b * 2pi 2/3
DIV2PIF32 RaH,RbH a = b / 2pi 2/3
DIVF32 RaH,RbH,RcH a = b/c 5
SQRTF32 RaH,RbH a = sqrt(b) 5
SINPUF32 RaH,RbH a = sin(b*2pi) 4
COSPUF32 RaH,RbH a = cos(b*2pi) 4
ATANPUF32 RaH,RbH a = atan(b)/2pi 4
QUADF32 RaH,RbH,RcH,RdH Operation to assist in calculating ATANPU2 5

No changes have been made to existing instructions, pipeline or memory bus architecture. All TMU instructions
use the existing FPU register set (R0H to R7H) to carry out their operations. A detailed explanation of the
workings of the FPU can be found in the TMS320C28x Extended Instruction Sets Technical Reference Manual.

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8.7 Control Law Accelerator

The CLA is an independent single-precision (32-bit) FPU processor with its own bus structure, fetch mechanism,
and pipeline. Eight individual CLA tasks can be specified. Each task is started by software or a peripheral such
as the ADC, ePWM, eCAP, eQEP, or CPU Timer 0. The CLA executes one task at a time to completion. When a
task completes, the main CPU is notified by an interrupt to the PIE and the CLA automatically begins the next
highest-priority pending task. The CLA can directly access the ADC Result registers, ePWM, eCAP, eQEP,
Comparator and DAC registers. Dedicated message RAMs provide a method to pass additional data between
the main CPU and the CLA.
Figure 8-2 shows the CLA block diagram.

CLA Control
Register Set
MIFR(16) CLA_INT1
From MPERINT1 to
MIOVF(16)
Shared to MICLR(16) CLA_INT8
Peripherals MPERINT8 MICLROVF(16) INT11 C28x
PIE
MIFRC(16) INT12 CPU
MIER(16)
MIRUN(16)
LVF
LUF
MVECT1(16)
MVECT2(16)
MVECT3(16)
SYSCLK MVECT4(16)
CLA Clock Enable MVECT5(16)
SYSRSn CPU Read/Write Data Bus
MVECT6(16)
MVECT7(16)
MVECT8(16) CLA Program
CLA Program Bus Memory (LSx)
MCTL(16)

LSxMSEL[MSEL_LSx]
LSxCLAPGM[CLAPGM_LSx]

CPU Data Bus

CLA Data
CLA Execution Memory (LSx)
CLA Data Bus

Register Set
MPC(16) CLA Message
MSTF(32) RAMs
MR0(32)
MR1(32)
MR2(32) Shared
MR3(32) Peripherals
MAR0(16) MEALLOW
MAR1(16)

CPU Read Data Bus

Figure 8-2. CLA Block Diagram

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8.8 Direct Memory Access

The CPU has its own 6-channel DMA module. The DMA module provides a hardware method of transferring
data between peripherals and/or memory without intervention from the CPU, thereby freeing up bandwidth for
other system functions. Additionally, the DMA has the capability to orthogonally rearrange the data as it is
transferred as well as “ping-pong” data between buffers. These features are useful for structuring data into
blocks for optimal CPU processing.
The DMA module is an event-based machine, meaning it requires a peripheral or software trigger to start a DMA
transfer. Although it can be made into a periodic time-driven machine by configuring a timer as the interrupt
trigger source, there is no mechanism within the module itself to start memory transfers periodically. The
interrupt trigger source for each of the six DMA channels can be configured separately and each channel
contains its own independent PIE interrupt to let the CPU know when a DMA transfer has either started or
completed. Five of the six channels are exactly the same, while Channel 1 has the ability to be configured at a
higher priority than the others.
DMA features include:
• Six channels with independent PIE interrupts
• Peripheral interrupt trigger sources
– ADC interrupts and EVT signals
– Multichannel buffered serial port transmit and receive
– External interrupts
– CPU timers
– EPWMxSOC signals
– SPIx transmit and receive
– SDFM
– Software trigger
• Data sources and destinations:
– GSx RAM
– ADC result registers
– ePWMx
– SPI
– McBSP
– EMIF
• Word Size: 16-bit or 32-bit (SPI and McBSP limited to 16-bit)
• Throughput: four cycles/word (without arbitration)

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Figure 8-3 shows a device-level block diagram of the DMA.

ADC ADC Global Shared
WRAPPER XINT TIMER
RESULTS 8x 4Kx16
(3) (5) (3)
(3) GS0-7 RAMs

C28x Bus
DMA Bus

TINT (0-2)

DMA_CHx (1-6)
XINT (1-5) DMA Trigger
Source Selection
ADC INT (A,B,D) (1-4), EVT (A,B,D) DMACHSRCSEL1.CHx DMA C28x
SDxFLTy (x = 1 to 2, y = 1 to 4) DMACHSRCSEL2.CHx
SOCA (1-12), SOCB (1-12) CHx.MODE.PERINTSEL
MXEVT (A-B), MREVT (A-B) (x = 1 to 6)
PIE
SPITX (A-C), SPIRX (A-C)

DMA Trigger Source

CPU and DMA Data Path
CMPSS

eQEP
eCAP
DAC

SDFM EPWM McBSP SPI

(8) (12) (2) (3) EMIF1

Figure 8-3. DMA Block Diagram

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8.9 Boot ROM and Peripheral Booting

The device boot ROM contains bootloading software. The device boot ROM is executed each time the device
comes out of reset. Users can configure the device to boot to flash (using GET mode) or choose to boot the
device through one of the bootable peripherals by configuring the boot mode GPIO pins.
Table 8-10 shows the possible boot modes supported on the device. The default boot mode pins are GPIO72
(boot mode pin 1) and GPIO 84 (boot mode pin 0). Users may choose to have weak pullups for boot mode pins if
they use a peripheral on these pins as well, so the pullups can be overdriven. On this device, customers can
change the factory default boot mode pins by programming OTP locations. This is recommended only for cases
in which the factory default boot mode pins do not fit into the customer design. More details on the locations to
be programmed is available in the TMS320F2807x Microcontrollers Technical Reference Manual .
Table 8-10. Device Boot Mode
GPIO72 GPIO84
(BOOT (BOOT
MODE NO. CPU1 BOOT MODE TRST
MODE MODE
PIN 1) PIN 0)
0 Parallel I/O 0 0 0
1 SCI Mode 0 0 1
2 Wait Boot Mode 0 1 0
3 Get Mode 0 1 1
4-7 EMU Boot Mode (JTAG debug probe connected) 1 X X

Note
The default behavior of Get mode is boot-to-flash. On unprogrammed devices, using Get mode will
result in repeated watchdog resets, which may prevent proper JTAG connection and device
initialization. Use Wait mode or another boot mode for unprogrammed devices.

CAUTION
Some reset sources are internally driven by the device. The user must ensure the pins used for boot
mode are not actively driven by other devices in the system for these cases. The boot configuration
has a provision for changing the boot pins in OTP. For more details, see the TMS320F2807x
Microcontrollers Technical Reference Manual .

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8.9.1 EMU Boot or Emulation Boot

The CPU enters this boot when it detects that TRST is HIGH (that is, when a JTAG debug probe/debugger is
connected). In this mode, the user can program the EMU_BOOTCTRL control-word (at location 0xD00) to
instruct the device on how to boot. If the contents of the EMU_BOOTCTRL location are invalid, then the device
would default to WAIT Boot mode. The emulation boot allows users to verify the device boot before
programming the boot mode into OTP. Note that EMU_BOOTCTRL is not actually a register, but refers to a
location in RAM (PIE RAM). PIE RAM starts at 0xD00, but the first few locations are reserved (when initializing
the PIE vector table in application code) for these boot ROM variables.
8.9.2 WAIT Boot Mode
The device in this boot mode loops in the boot ROM. This mode is useful if users want to connect a debugger on
a secure device or if users do not want the device to execute an application in flash yet.
8.9.3 Get Mode
The default behavior of Get mode is boot-to-flash. This behavior can be changed by programming the Zx-
OTPBOOTCTRL locations in user configurable DCSM OTP. The user configurable DCSM OTP on this device is
divided in to two secure zones: Z1 and Z2. The Get mode function in boot ROM first checks if a valid
OTPBOOTCTRL value is programmed in Z1. If the answer is yes, then the device boots as per the Z1-
OTPBOOTCTRL location. The Z2-OTPBOOTCTRL location is read and decodes only if Z1-OTPBOOTCTRL is
invalid or not programmed. If either Zx-OTPBOOTCTRL location is not programmed, then the device defaults to
factory default operation, which is to use factory default boot mode pins to boot to flash if the boot mode pins are
set to GET MODE. Users can choose the device through which to boot—SPI, I2C, CAN, and USB—by
programming proper values into the user configurable DCSM OTP. More details on this can be found in the
TMS320F2807x Microcontrollers Technical Reference Manual .

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8.9.4 Peripheral Pins Used by Bootloaders

Table 8-11 shows the GPIO pins used by each peripheral bootloader. This device supports two sets of GPIOs for
each mode, as shown in Table 8-11.
Table 8-11. GPIO Pins Used by Each Peripheral Bootloader
BOOTLOADER GPIO PINS NOTES
SCITXDA: GPIO84 SCIA Boot I/O option 1 (default SCI option
SCI-Boot0
SCIRXDA: GPIO85 when chosen through Boot Mode GPIOs)
SCIRXDA: GPIO28
SCI-Boot1 SCIA Boot option 2 – with alternate I/Os.
SCITXDA: GPIO29
D0 – GPIO65
D1 – GPIO64
D2 – GPIO58
D3 – GPIO59
D4 – GPIO60
Parallel Boot
D5 – GPIO61
D6 – GPIO62
D7 – GPIO63
HOST_CTRL – GPIO70
DSP_CTRL – GPIO69
CANRXA: GPIO70
CAN-Boot0 CAN-A Boot – I/O option 1
CANTXA: GPIO71
CANRXA: GPIO62
CAN-Boot1 CAN-A Boot – I/O option 2
CANTXA: GPIO63
SDAA: GPIO91
I2C-Boot0 I2CA Boot – I/O option 1
SCLA: GPIO92
SDAA: GPIO32
I2C-Boot1 I2CA Boot – I/O option 2
SCLA: GPIO33
SPISIMOA - GPIO58
SPISOMIA - GPIO59
SPI-Boot0 SPIA Boot – I/O option 1
SPICLKA - GPIO60
SPISTEA - GPIO61
SPISIMOA – GPIO16
SPISOMIA – GPIO17
SPI-Boot1 SPIA Boot – I/O option 2
SPICLKA – GPIO18
SPISTEA – GPIO19
The USB Bootloader will switch the clock
source to the external crystal oscillator (X1
USB0DM - GPIO42
USB Boot and X2 pins). A 20-MHz crystal should be
USB0DP - GPIO43
present on the board if this boot mode is
selected.

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8.10 Dual Code Security Module

The dual code security module (DCSM) prevents access to on-chip secure memories. The term “secure” means
access to secure memories and resources is blocked. The term “unsecure” means access is allowed; for
example, through a debugging tool such as Code Composer Studio™ (CSS).
The code security mechanism offers protection for two zones, Zone 1 (Z1) and Zone 2 (Z2). The security
implementation for both the zones is identical. Each zone has its own dedicated secure resource (OTP memory
and secure ROM) and allocated secure resource (CLA, LSx RAM, and flash sectors).
The security of each zone is ensured by its own 128-bit password (CSM password). The password for each zone
is stored in an OTP memory location based on a zone-specific link pointer. The link pointer value can be
changed to program a different set of security settings (including passwords) in OTP.

Note

THE CODE SECURITY MODULE (CSM) INCLUDED ON THIS DEVICE WAS DESIGNED TO
PASSWORD PROTECT THE DATA STORED IN THE ASSOCIATED MEMORY AND IS
WARRANTED BY TEXAS INSTRUMENTS (TI), IN ACCORDANCE WITH ITS STANDARD TERMS
AND CONDITIONS, TO CONFORM TO TI'S PUBLISHED SPECIFICATIONS FOR THE WARRANTY
PERIOD APPLICABLE FOR THIS DEVICE.
TI DOES NOT, HOWEVER, WARRANT OR REPRESENT THAT THE CSM CANNOT BE
COMPROMISED OR BREACHED OR THAT THE DATA STORED IN THE ASSOCIATED MEMORY
CANNOT BE ACCESSED THROUGH OTHER MEANS. MOREOVER, EXCEPT AS SET FORTH
ABOVE, TI MAKES NO WARRANTIES OR REPRESENTATIONS CONCERNING THE CSM OR
OPERATION OF THIS DEVICE, INCLUDING ANY IMPLIED WARRANTIES OF MERCHANTABILITY
OR FITNESS FOR A PARTICULAR PURPOSE.
IN NO EVENT SHALL TI BE LIABLE FOR ANY CONSEQUENTIAL, SPECIAL, INDIRECT,
INCIDENTAL, OR PUNITIVE DAMAGES, HOWEVER CAUSED, ARISING IN ANY WAY OUT OF
YOUR USE OF THE CSM OR THIS DEVICE, WHETHER OR NOT TI HAS BEEN ADVISED OF THE
POSSIBILITY OF SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITED
TO LOSS OF DATA, LOSS OF GOODWILL, LOSS OF USE OR INTERRUPTION OF BUSINESS OR
OTHER ECONOMIC LOSS.

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8.11 Timers
CPU-Timers 0, 1, and 2 are identical 32-bit timers with presettable periods and with 16-bit clock prescaling. The
timers have a 32-bit count-down register that generates an interrupt when the counter reaches zero. The counter
is decremented at the CPU clock speed divided by the prescale value setting. When the counter reaches zero, it
is automatically reloaded with a 32-bit period value.
CPU-Timer 0 is for general use and is connected to the PIE block. CPU-Timer 1 is also for general use and is
connected to INT13 of the CPU. CPU-Timer 2 is reserved for TI-RTOS. It is connected to INT14 of the CPU. If
TI-RTOS is not being used, CPU-Timer 2 is available for general use.
CPU-Timer 2 can be clocked by any one of the following:
• SYSCLK (default)
• Internal zero-pin oscillator 1 (INTOSC1)
• Internal zero-pin oscillator 2 (INTOSC2)
• X1 (XTAL)
• AUXPLLCLK
8.12 Nonmaskable Interrupt With Watchdog Timer (NMIWD)
The NMIWD module is used to handle system-level errors. The conditions monitored are:
• Missing system clock due to oscillator failure
• Uncorrectable ECC error on CPU access to flash memory
• Uncorrectable ECC error on CPU, CLA, or DMA access to RAM
If the CPU does not respond to the latched error condition, then the NMI watchdog will trigger a reset after a
programmable time interval. The default time is 65536 SYSCLK cycles.

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8.13 Watchdog
The watchdog module is the same as the one on previous TMS320C2000™ MCUs, but with an optional lower
limit on the time between software resets of the counter. This windowed countdown is disabled by default, so the
watchdog is fully backwards-compatible.
The watchdog generates either a reset or an interrupt. It is clocked from the internal oscillator with a selectable
frequency divider.
Figure 8-4 shows the various functional blocks within the watchdog module.

WDCR(WDPS(2:0)) WDCR(WDDIS)

WDCNTR(7:0)

WDCLK Watchdog 8-bit 1-count

(INTOSC1)
/512 Overflow
Prescaler Watchdog delay
Counter
SYSRSn
Clear
Count

WDWCR(MIN(7:0))
WDKEY(7:0) Watchdog
Watchdog Window
Good Key Out of Window
Key Detector Detector
Bad Key
55 + AA

WDRSTn
Generate
512-WDCLK
WDINTn Watchdog Time-out
Output Pulse

SCSR(WDENINT)

Figure 8-4. Windowed Watchdog

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8.14 Configurable Logic Block (CLB)

The C2000 configurable logic block (CLB) is a collection of blocks that can be interconnected using software to
implement custom digital logic functions or enhance existing on-chip peripherals. The CLB is able to enhance
existing peripherals through a set of crossbar interconnections, which provide a high level of connectivity to
existing control peripherals such as enhanced pulse width modulators (ePWM), enhanced capture modules
(eCAP), and enhanced quadrature encoder pulse modules (eQEP). The crossbars also allow the CLB to be
connected to external GPIO pins. In this way, the CLB can be configured to interact with device peripherals to
perform small logical functions such as comparators, or to implement custom serial data exchange protocols.
Through the CLB, functions that would otherwise be accomplished using external logic devices can now be
implemented inside the MCU.
The CLB peripheral is configured through the CLB tool. For more information on the CLB tool, available
examples, application reports and users guide, please refer to the following location in your C2000Ware package
(C2000Ware_2_00_00_03 and higher):
C2000WARE_INSTALL_LOCATION\utilities\clb_tool\clb_syscfg\doc
CLB Tool User Guide
How to Design with the C2000™ CLB Application Report
How to Migrate Custom Logic From an FPGA/CPLD to C2000™ CLB Application Report
The CLB module and its interconnects are shown in Figure 8-5.

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Figure 8-5. CLB Overview

Absolute encoder protocol interfaces are now provided as Position Manager solutions in the C2000Ware
MotorControl SDK. Configuration files, application programmer interface (API), and use examples for such
solutions are provided with C2000Ware MotorControl SDK. In some solutions, the TI-configured CLB is used
with other on-chip resources, such as the SPI port or the C28x CPU, to perform more complex functionality. See
Table 5-1 for the devices that support the CLB feature.

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8.15 Functional Safety

TMS320C2000™ MCUs are equipped with a TI release validation-based C28x and CLA Compiler Qualification
Kit (CQ-Kit), which is available for free and may be requested at the Compiler Qualification Kit web page.
Additionally, C2000™ MCUs are supported by the TI C2000 Support from Embedded Coder from MathWorks® to
generate C2000-optimized code from a Simulink® model. Simulink® enables Model-Based Design to ease the
systematic compliance process with certified tools, including Embedded Coder®, Simulink® model verification
tools, Polyspace® code verification tools, and the IEC Certification Kit for ISO 26262 and IEC 61508 compliance.
For more information, see the How to Use Simulink for ISO 26262 Projects article.
The Error Detection in SRAM Application Report provides technical information about the nature of the SRAM bit
cell and bit array, as well as the sources of SRAM failures. It then presents methods for managing memory
failures in electronic systems. This discussion is intended for electronic system developers or integrators who
are interested in improving the robustness of the embedded SRAM.
Functional Safety-Compliant products are developed using an ISO 26262/IEC 61508-compliant hardware
development process that is independently assessed and certified to meet ASIL D/SIL 3 systematic capability
(see certificate). The TMS320F2837D, TMS320F2837xS, and TMS320F2807x MCUs have been certified to
meet a component-level random hardware capability of ASIL B/SIL 2 (see certificate).
The Functional Safety-Compliant enablers include:
• A Functional Safety Manual
• A detailed, tunable, quantitative Failure Modes, Effects, and Diagnostics Analysis (FMEDA)
• A software diagnostic library that will help shorten the time to implement various software safety mechanisms
• A collection of application reports to help in the development of functionally safe systems.
A functional safety manual that describes all of the hardware and software functional safety mechanisms is
available. See the Safety Manual for TMS320F2837xD, TMS320F2837xS, and TMS320F2807x.
A detailed, tunable, fault-injected, quantitative FMEDA that enables the calculation of random hardware metrics
—as outlined in the International Organization for Standardization ISO 26262 and the International
Electrotechnical Commission IEC 61508 for automotive and industrial applications, respectively—is also
available. This tunable FMEDA must be requested; see the C2000™ Package for Automotive and Industrial
MCUs User's Guide.
• A white paper outlining the value (or benefit) of a tunable FMEDA is available. See the Functional Safety: A
tunable FMEDA for C2000™ MCUs publication.
• Parts 1 and 2 of a five-part FMEDA tuning training are available. See the C2000™ Tunable FMEDA Training
page.
Parts 3, 4, and 5 are packaged with the tunable FMEDA, and must be requested.
The C2000 Diagnostic Software Library is a collection of different safety mechanisms designed to detect faults.
These safety mechanisms target different device components, including the C28x core, the control law
accelerator (CLA), system control, static random access memory (SRAM), flash, and communications and
control peripherals. The software safety mechanisms leverage available hardware safety features such as the
C28x hardware built-in self-test (HWBIST); error detection and correction functionality on memories; parallel
signature analysis circuitry; missing clock detection logic; watchdog counters; and hardware redundancy.
Also included are software functional safety manual, user guides, example projects, and source code to help
users shorten system integration time. The library package includes a compliance support package (CSP), a
series of documents that TI used to develop and test the diagnostic software library. The CSP provides the
necessary documentation and reports to assist users with compliance to functional safety standards: software
safety requirements specifications; a software architecture document; software module design documents;
software module unit test plans; software module unit test documents; static analysis reports; unit test reports;
dynamic analysis reports; functional test reports; and traceability documents. Users can use these documents to
comply with route 1s (as described in IEC 61508-3, section 7.4.2.12) to reuse a preexisting software element to
implement all or part of a safety function. The contents of the CSP could also help users make important
decisions for overall system safety compliance.

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Two application reports offer details about how to develop functionally safe systems with C2000 real-time control
devices:
• C2000™ Hardware Built-In Self-Test discusses the HWBIST safety mechanism, along with its functions and
features, in the F2807x/F2837xS/F2837xD series of C2000 devices. The report also addresses some
system-level considerations when using the HWBIST feature and explains how customers can use the
diagnostic library on their system.
• C2000™ CPU Memory Built-In Self-Test describes embedded memory validation using the C28x central
processing unit (CPU) during an active control loop. It discusses system challenges to memory validation as
well as the different solutions provided by C2000 devices and software. Finally, it presents the Diagnostic
Library implementations for memory testing.

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9 Applications, Implementation, and Layout

Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.

9.1 TI Reference Design

The TI Reference Design Library is a robust reference design library spanning analog, embedded processor,
and connectivity. Created by TI experts to help you jump start your system design, all reference designs include
schematic or block diagrams, BOMs, and design files to speed your time to market. Search and download
designs at the Select TI reference designs page.
Industrial Servo Drive and AC Inverter Drive Reference Design
The DesignDRIVE Development Kit is a reference design for a complete industrial drive directly connecting to a
three-phase ACI or PMSM motor. Many drive topologies can be created from the combined control, power, and
communications technologies included on this single platform. This platform includes multiple position sensor
interfaces, diverse current sensing techniques, hot-side partitioning options, and expansion for safety and
industrial Ethernet.
Differential Signal Conditioning Circuit for Current and Voltage Measurement Using Fluxgate Sensors
This design provides a 4-channel signal conditioning solution for differential ADCs integrated into a
microcontroller measuring motor current using fluxgate sensors. Also provided is an alternative measurement
circuit with external differential SAR ADCs as well as circuits for high-speed overcurrent and earth fault
detection. Proper differential signal conditioning improves noise immunity on critical current measurements in
motor drives. This reference design can help increase the effective resolution of the analog-to-digital conversion,
improving motor drive efficiency.

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10 Device and Documentation Support

10.1 Device and Development Support Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
TMS320™ MCU devices and support tools. Each TMS320 MCU commercial family member has one of three
prefixes: TMX, TMP, or TMS (for example, TMS320F28075). Texas Instruments recommends two of three
possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages
of product development from engineering prototypes (with TMX for devices and TMDX for tools) through fully
qualified production devices and tools (with TMS for devices and TMDS for tools).
Device development evolutionary flow:
TMX Experimental device that is not necessarily representative of the final device's electrical specifications
TMP Final silicon die that conforms to the device's electrical specifications but has not completed quality and reliability
verification
TMS Fully qualified production device

Support tool development evolutionary flow:

TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing
TMDS Fully qualified development-support product

TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability
of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system because their
expected end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type
(for example, PTP) and temperature range (for example, T). Figure 10-1 provides a legend for reading the
complete device name for any family member.
For device part numbers and further ordering information, see the TI website (www.ti.com) or contact your TI
sales representative.
For additional description of the device nomenclature markings on the die, see the TMS320F2807x MCUs
Silicon Errata .

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Figure 10-1. Device Nomenclature

10.2 Markings
Figure 10-2 provides an example of the 2807x device markings and defines each of the markings. The device
revision can be determined by the symbols marked on the top of the package as shown in Figure 10-2. Some
prototype devices may have markings different from those illustrated.

YMLLLLS = Lot Trace Code

YM = 2-Digit Year/Month Code

LLLL = Assembly Lot
TMS320 S = Assembly Site Code
$$ = Wafer Fab Code as applicable
F28075PTPT # = Silicon Revision Code
$$#-YMLLLLS G4 = Green (Low Halogen and RoHS-compliant)
G4

Package
Pin 1

Figure 10-2. Example of Device Markings

Table 10-1. Determining Silicon Revision From Lot Trace Code

REVID(1)
SILICON REVISION CODE SILICON REVISION COMMENTS
Address: 0x5D00C
B B 0x0002 This silicon revision is available as TMX.
C C 0x0003 This silicon revision is available as TMS.

(1) Silicon Revision ID

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10.3 Tools and Software

TI offers an extensive line of development tools. Some of the tools and software to evaluate the performance of
the device, generate code, and develop solutions are listed below. To view all available tools and software for
C2000™ real-time control MCUs, visit the C2000 real-time control MCUs – Design & development page.
Development Tools
F28379D controlCARD for C2000 Real time control development kits
The F28379D controlCARD from Texas Instruments is Position Manager-ready and an ideal product for initial
software development and short run builds for system prototypes, test stands, and many other projects that
require easy access to high-performance controllers. All C2000 controlCARDs are complete board-level modules
that utilize a HSEC180 or DIMM100 form factor to provide a low-profile single-board controller solution. The host
system needs to provide only a single 5V power rail to the controlCARD for it to be fully functional.
F28379D Experimenter Kit
C2000™ MCU Experimenter Kits provide a robust hardware prototyping platform for real-time, closed loop
control development with Texas Instruments C2000 32-bit microcontroller family. This platform is a great tool to
customize and prove-out solutions for many common power electronics applications, including motor control,
digital power supplies, solar inverters, digital LED lighting, precision sensing, and more.
Software Tools
C2000Ware for C2000 MCUs
C2000Ware for C2000 microcontrollers is a cohesive set of development software and documentation designed
to minimize software development time. From device-specific drivers and libraries to device peripheral examples,
C2000Ware provides a solid foundation to begin development and evaluation. C2000Ware is now the
recommended content delivery tool versus controlSUITE™.
Code Composer Studio™ (CCS) Integrated Development Environment (IDE) for C2000 Microcontrollers
Code Composer Studio is an integrated development environment (IDE) that supports TI's Microcontroller and
Embedded Processors portfolio. Code Composer Studio comprises a suite of tools used to develop and debug
embedded applications. It includes an optimizing C/C++ compiler, source code editor, project build environment,
debugger, profiler, and many other features. The intuitive IDE provides a single user interface taking the user
through each step of the application development flow. Familiar tools and interfaces allow users to get started
faster than ever before. Code Composer Studio combines the advantages of the Eclipse software framework
with advanced embedded debug capabilities from TI resulting in a compelling feature-rich development
environment for embedded developers.
Pin Mux Tool
The Pin Mux Utility is a software tool which provides a Graphical User Interface for configuring pin multiplexing
settings, resolving conflicts and specifying I/O cell characteristics for TI MPUs.
F021 Flash Application Programming Interface (API)
The F021 Flash Application Programming Interface (API) provides a software library of functions to program,
erase, and verify F021 on-chip Flash memory.
UniFlash Standalone Flash Tool
UniFlash is a standalone tool used to program on-chip flash memory through a GUI, command line, or scripting
interface.

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Models
Various models are available for download from the product Tools & Software pages. These include I/O Buffer
Information Specification (IBIS) Models and Boundary-Scan Description Language (BSDL) Models. To view all
available models, visit the Models section of the Tools & Software page for each device.
Training
To help assist design engineers in taking full advantage of the C2000 microcontroller features and performance,
TI has developed a variety of training resources. Utilizing the online training materials and downloadable hands-
on workshops provides an easy means for gaining a complete working knowledge of the C2000 microcontroller
family. These training resources have been designed to decrease the learning curve, while reducing
development time, and accelerating product time to market. For more information on the various training
resources, visit the C2000™ real-time control MCUs – Support & training site.
Specific F2837xD/F2837xS/F2807x hands-on training resources can be found at C2000™ MCU Device
Workshops.

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10.4 Documentation Support

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
The current documentation that describes the processor, related peripherals, and other technical collateral is
listed below.
Errata
TMS320F2807x MCUs Silicon Errata describes known advisories on silicon and provides workarounds.
Technical Reference Manual
TMS320F2807x Microcontrollers Technical Reference Manual details the integration, the environment, the
functional description, and the programming models for each peripheral and subsystem in the 2807x
microcontrollers.
CPU User's Guides
TMS320C28x CPU and Instruction Set Reference Guide describes the central processing unit (CPU) and the
assembly language instructions of the TMS320C28x fixed-point digital signal processors (DSPs). This Reference
Guide also describes emulation features available on these DSPs.
TMS320C28x Extended Instruction Sets Technical Reference Manual describes the architecture, pipeline, and
instruction set of the TMU, VCU-II, and FPU accelerators.
Peripheral Guides
C2000 Real-Time Control Peripherals Reference Guide describes the peripheral reference guides of the 28x
DSPs.
Tools Guides
TMS320C28x Assembly Language Tools v20.2.0.LTS User's Guide describes the assembly language tools
(assembler and other tools used to develop assembly language code), assembler directives, macros, common
object file format, and symbolic debugging directives for the TMS320C28x device.
TMS320C28x Optimizing C/C++ Compiler v20.2.0.LTS User's Guide describes the TMS320C28x C/C++
compiler. This compiler accepts ANSI standard C/C++ source code and produces TMS320 DSP assembly
language source code for the TMS320C28x device.
Application Reports
Semiconductor Packing Methodology describes the packing methodologies employed to prepare semiconductor
devices for shipment to end users.
Calculating Useful Lifetimes of Embedded Processors provides a methodology for calculating the useful lifetime
of TI embedded processors (EPs) under power when used in electronic systems. It is aimed at general
engineers who wish to determine if the reliability of the TI EP meets the end system reliability requirement.
An Introduction to IBIS (I/O Buffer Information Specification) Modeling discusses various aspects of IBIS
including its history, advantages, compatibility, model generation flow, data requirements in modeling the input/
output structures and future trends.
Serial Flash Programming of C2000™ Microcontrollers discusses using a flash kernel and ROM loaders for
serial programming a device.
10.5 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
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10.6 Trademarks
PowerPAD™, Code Composer Studio™, TMS320C2000™, C2000™, TMS320™, controlSUITE™, TI E2E™ are
trademarks of Texas Instruments.
Bosch® is a registered trademark of Robert Bosch GmbH Corporation.
MathWorks®, Simulink®, Embedded Coder®, Polyspace® are registered trademarks of The MathWorks, Inc.
All trademarks are the property of their respective owners.
10.7 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

10.8 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

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11 Mechanical, Packaging, and Orderable Information

11.1 Packaging Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE OUTLINE
PZP0100N SCALE 1.000
PowerPAD TM TQFP - 1.2 mm max height
PLASTIC QUAD FLATPACK

14.2
B
13.8
PIN 1 ID NOTE 3
100 76

1 75

14.2 16.2
TYP
13.8 15.8
NOTE 3

25
51

26
A 50 0.27
100X
96X 0.5 0.17
0.08 C A B
4X 12

SEATING PLANE

(0.127) SEE DETAIL A 1.2 MAX

TYP
26 50

25 51
0.25
GAGE PLANE (1)

8.64 0.15
101 0 -7 0.08 C 0.05
7.45
0.75
0.45
DETAIL A
TYPICAL

4X (0.3) 4X (0.3)
1 NOTE 4 75 NOTE 4

100 76
4223383/A 04/2017
PowerPAD is a trademark of Texas Instruments.
NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs.
4. Strap features may not be present.
5. Reference JEDEC registration MS-026.

www.ti.com DETAIL A
SCALE: 14

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EXAMPLE BOARD LAYOUT

PZP0100N PowerPAD TM TQFP - 1.2 mm max height
PLASTIC QUAD FLATPACK

( 12)
NOTE 10
( 8.64)
SYMM
SOLDER MASK
100 76 DEFINED PAD
100X (1.5)

1
75

100X (0.3)

96X (0.5)

101 (1) TYP

SYMM
(15.4)

(R0.05) TYP
25 51

( 0.2) TYP
VIA
26 50 METAL COVERED
SEE DETAILS (1) TYP BY SOLDER MASK

(15.4)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:5X
0.05 MAX 0.05 MIN
ALL AROUND ALL AROUND
METAL SOLDER MASK
OPENING
EXPOSED METAL

EXPOSED METAL
METAL UNDER
SOLDER MASK SOLDER MASK
OPENING

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
SOLDER MASK DETAILS
4223383/A 04/2017

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. See technical brief, Powerpad thermally enhanced package,
Texas Instruments Literature No. SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled,
plugged or tented.
10. Size of metal pad may vary due to creepage requirement.

www.ti.com

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EXAMPLE STENCIL DESIGN

PZP0100N PowerPAD TM TQFP - 1.2 mm max height
PLASTIC QUAD FLATPACK

( 8.64)
BASED ON
0.125 THICK STENCIL

SYMM SEE TABLE FOR

DIFFERENT OPENINGS
100 76 FOR OTHER STENCIL
THICKNESSES
100X (1.5)

1
75

100X (0.3)

96X (0.5)

SYMM 101
(15.4)

(R0.05) TYP

25 51

METAL COVERED
BY SOLDER MASK
26 50
(15.4)

SOLDER PASTE EXAMPLE

EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:6X

STENCIL SOLDER STENCIL

THICKNESS OPENING
0.1 9.66 X 9.66
0.125 8.64 X 8.64 (SHOWN)
0.150 7.89 X 7.89
0.175 7.3 X 7.3

4223383/A 04/2017

NOTES: (continued)

11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.

www.ti.com

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PACKAGE OUTLINE
TM
PTP0176F SCALE 0.550
PowerPAD HLQFP - 1.6 mm max height
PLASTIC QUAD FLATPACK

24.2
NOTE 3 B
23.8
PIN 1 ID 176 133

1 132

24.2 26.2
TYP
23.8 25.8
NOTE 3

44
89
45
88 0.27
A 172X 0.5 176X
0.17
4X 21.5 0.08 C A B

SEATING PLANE

(0.13) SEE DETAIL A 1.6 MAX

TYP
45 88

44 89

0.25
4X 0.78 MAX (1.4)
GAGE PLANE
NOTE 4

4X
0.54 MAX 0.08 C 0.15
7.33 0 -7 0.05
177 NOTE 4
6.78
0.75
0.45
DETAIL A
4X TYPICAL
0.2 MAX EXPOSED
NOTE 4 THERMAL PAD

1 132

176 133
8.07
7.53
4223382/A 03/2017
PowerPAD is a trademark of Texas Instruments.
NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs.
4. Strap features my not present.
5. Reference JEDEC registration MS-026.

www.ti.com
DETAIL A
SCALE: 12

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EXAMPLE BOARD LAYOUT

PTP0176F PowerPAD
TM
HLQFP - 1.6 mm max height
PLASTIC QUAD FLATPACK

(8.07)
SYMM
SOLDER MASK
176 133 DEFINED PAD
176X (1.45)

1
132
176X (0.3)

172X (0.5)

SYMM 177 (1.5 TYP)

(25.5)
(7.33)
( 22)
NOTE 10

(R0.05) TYP

( 0.2) TYP
VIA

44 89

SEE DETAILS

45 88 METAL COVERED
(1.5 TYP) BY SOLDER MASK
(25.5)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:4X
0.05 MAX 0.05 MIN
ALL AROUND ALL AROUND
METAL SOLDER MASK
OPENING

EXPOSED METAL EXPOSED METAL

SOLDER MASK METAL UNDER
OPENING SOLDER MASK

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
SOLDER MASK DETAILS
4223382/A 03/2017
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. See technical brief, Powerpad thermally enhanced package,
Texas Instruments Literature No. SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged
or tented.
10. Size of metal pad may vary due to creepage requirement.

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EXAMPLE STENCIL DESIGN

PTP0176F PowerPAD
TM
HLQFP - 1.6 mm max height
PLASTIC QUAD FLATPACK

(8.07)
BASED ON
SYMM 0.125 THICK STENCIL
176 133
176X (1.45)

1
132

176X (0.3)

172X (0.5)

(25.5)
SYMM (7.33)
177
BASED ON
0.125 THICK
STENCIL
(R0.05) TYP

SEE TABLE FOR

DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES

44 89

METAL COVERED
BY SOLDER MASK 45 88
(25.5)

SOLDER PASTE EXAMPLE

EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:4X

STENCIL SOLDER STENCIL

THICKNESS OPENING
0.1 9.02 X 8.2
0.125 8.07 X 7.33 (SHOWN)
0.150 7.37 X 6.69
0.175 6.82 X 6.2

4223382/A 03/2017

NOTES: (continued)

11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.

www.ti.com

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 PACKAGE OPTION ADDENDUM

www.ti.com 29-Jan-2021

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

TMS320F28075PTPQ ACTIVE HLQFP PTP 176 40 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 TMS320
F28075PTPQ
TMS320F28075PTPQR ACTIVE HLQFP PTP 176 200 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 TMS320
F28075PTPQ
TMS320F28075PTPS ACTIVE HLQFP PTP 176 40 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 TMS320
F28075PTPS
TMS320F28075PTPT ACTIVE HLQFP PTP 176 40 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 105 TMS320
F28075PTPT
TMS320F28075PZPQ ACTIVE HTQFP PZP 100 90 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 TMS320
F28075PZPQ
TMS320F28075PZPS ACTIVE HTQFP PZP 100 90 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 TMS320
F28075PZPS
TMS320F28075PZPT ACTIVE HTQFP PZP 100 90 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 105 TMS320
F28075PZPT
TMS320F28076PTPS ACTIVE HLQFP PTP 176 40 RoHS & Green NIPDAU Level-3-260C-168 HR -45 to 125 TMS320
F28076PTPS
TMS320F28076PZPS ACTIVE HTQFP PZP 100 90 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 TMS320
F28076PZPS

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

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(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
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